FORMAT_CONTROL__ALPHA_EN 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); FORMAT_CONTROL__ALPHA_EN 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ FORMAT_CONTROL__ALPHA_EN 1077 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h type FORMAT_CONTROL__ALPHA_EN; \ FORMAT_CONTROL__ALPHA_EN 728 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c FORMAT_CONTROL__ALPHA_EN, 0, FORMAT_CONTROL__ALPHA_EN 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);