FORMAT_CONTROL    322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_SET_3(FORMAT_CONTROL, 0,
FORMAT_CONTROL    328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_SET_3(FORMAT_CONTROL, 0,
FORMAT_CONTROL    399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
FORMAT_CONTROL    117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
FORMAT_CONTROL   1330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t FORMAT_CONTROL; \
FORMAT_CONTROL    726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET_3(FORMAT_CONTROL, 0,
FORMAT_CONTROL     35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
FORMAT_CONTROL    172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	uint32_t FORMAT_CONTROL;
FORMAT_CONTROL    113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_SET_2(FORMAT_CONTROL, 0,
FORMAT_CONTROL    122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
FORMAT_CONTROL    123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
FORMAT_CONTROL    124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
FORMAT_CONTROL    125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
FORMAT_CONTROL    219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);