FMT_CLAMP_CNTL    330 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 	REG_SET_2(FMT_CLAMP_CNTL, 0,
FMT_CLAMP_CNTL    338 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_SET_2(FMT_CLAMP_CNTL, 0,
FMT_CLAMP_CNTL    343 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_SET_2(FMT_CLAMP_CNTL, 0,
FMT_CLAMP_CNTL    348 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_SET_2(FMT_CLAMP_CNTL, 0,
FMT_CLAMP_CNTL    354 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c 		REG_SET_2(FMT_CLAMP_CNTL, 0,
FMT_CLAMP_CNTL     50 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CLAMP_CNTL, FMT, id), \
FMT_CLAMP_CNTL    112 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
FMT_CLAMP_CNTL    113 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
FMT_CLAMP_CNTL    258 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	uint32_t FMT_CLAMP_CNTL;
FMT_CLAMP_CNTL    194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 	REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_CNTL    200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_CNTL    205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_CNTL    210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_CNTL    216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 		REG_UPDATE_2(FMT_CLAMP_CNTL,
FMT_CLAMP_CNTL     42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_CLAMP_CNTL, FMT, id), \
FMT_CLAMP_CNTL     59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	uint32_t FMT_CLAMP_CNTL; \