eqc 258 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t eqc:1, eqc 30 arch/s390/include/asm/eadm.h u8 eqc; eqc 1570 drivers/crypto/hisilicon/qm.c struct qm_eqc *eqc; eqc 1578 drivers/crypto/hisilicon/qm.c eqc = kzalloc(sizeof(struct qm_eqc), GFP_KERNEL); eqc 1579 drivers/crypto/hisilicon/qm.c if (!eqc) eqc 1581 drivers/crypto/hisilicon/qm.c eqc_dma = dma_map_single(dev, eqc, sizeof(struct qm_eqc), eqc 1584 drivers/crypto/hisilicon/qm.c kfree(eqc); eqc 1588 drivers/crypto/hisilicon/qm.c eqc->base_l = lower_32_bits(qm->eqe_dma); eqc 1589 drivers/crypto/hisilicon/qm.c eqc->base_h = upper_32_bits(qm->eqe_dma); eqc 1591 drivers/crypto/hisilicon/qm.c eqc->dw3 = QM_EQE_AEQE_SIZE; eqc 1592 drivers/crypto/hisilicon/qm.c eqc->dw6 = (QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT); eqc 1595 drivers/crypto/hisilicon/qm.c kfree(eqc); eqc 4198 drivers/infiniband/hw/hns/hns_roce_hw_v1.c void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num]; eqc 4202 drivers/infiniband/hw/hns/hns_roce_hw_v1.c val = readl(eqc); eqc 4217 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel(val, eqc); eqc 4223 drivers/infiniband/hw/hns/hns_roce_hw_v1.c void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn]; eqc 4269 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel(eqshift_val, eqc); eqc 4272 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel((u32)(eq->buf_list[0].map >> 12), eqc + 4); eqc 4286 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel(eqcuridx_val, eqc + 8); eqc 4292 drivers/infiniband/hw/hns/hns_roce_hw_v1.c writel(eqconsindx_val, eqc + 0xc); eqc 5399 drivers/infiniband/hw/hns/hns_roce_hw_v2.c struct hns_roce_eq_context *eqc; eqc 5401 drivers/infiniband/hw/hns/hns_roce_hw_v2.c eqc = mb_buf; eqc 5402 drivers/infiniband/hw/hns/hns_roce_hw_v2.c memset(eqc, 0, sizeof(struct hns_roce_eq_context)); eqc 5421 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5427 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5432 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5437 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5442 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5447 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5452 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_4, eqc 5458 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_8, eqc 5464 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_8, eqc 5470 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_8, eqc 5476 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_12, eqc 5481 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_12, eqc 5486 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->eqe_report_timer, eqc 5492 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->eqe_ba0, eqc 5497 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->eqe_ba1, eqc 5502 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_28, eqc 5507 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_28, eqc 5513 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_28, eqc 5518 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_32, eqc 5523 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_36, eqc 5528 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->byte_36, eqc 5534 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->nxt_eqe_ba0, eqc 5539 drivers/infiniband/hw/hns/hns_roce_hw_v2.c roce_set_field(eqc->nxt_eqe_ba1, eqc 3060 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c static int eq_get_mtt_addr(struct mlx4_eq_context *eqc) eqc 3062 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8; eqc 3065 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c static int eq_get_mtt_size(struct mlx4_eq_context *eqc) eqc 3067 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int log_eq_size = eqc->log_eq_size & 0x1f; eqc 3068 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int page_shift = (eqc->log_page_size & 0x3f) + 12; eqc 3101 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c struct mlx4_eq_context *eqc = inbox->buf; eqc 3102 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz; eqc 3103 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int mtt_size = eq_get_mtt_size(eqc); eqc 319 drivers/net/ethernet/mellanox/mlx5/core/debugfs.c param = 1 << MLX5_GET(eqc, ctx, log_eq_size); eqc 322 drivers/net/ethernet/mellanox/mlx5/core/debugfs.c param = MLX5_GET(eqc, ctx, intr); eqc 325 drivers/net/ethernet/mellanox/mlx5/core/debugfs.c param = MLX5_GET(eqc, ctx, log_page_size) + 12; eqc 251 drivers/net/ethernet/mellanox/mlx5/core/eq.c void *eqc; eqc 290 drivers/net/ethernet/mellanox/mlx5/core/eq.c eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry); eqc 291 drivers/net/ethernet/mellanox/mlx5/core/eq.c MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent)); eqc 292 drivers/net/ethernet/mellanox/mlx5/core/eq.c MLX5_SET(eqc, eqc, uar_page, priv->uar->index); eqc 293 drivers/net/ethernet/mellanox/mlx5/core/eq.c MLX5_SET(eqc, eqc, intr, vecidx); eqc 294 drivers/net/ethernet/mellanox/mlx5/core/eq.c MLX5_SET(eqc, eqc, log_page_size, eqc 380 drivers/s390/block/scm_blk.c switch (scmrq->aob->response.eqc) {