engn 22 drivers/gpu/drm/nouveau/include/nvkm/core/oclass.h const void *engn; engn 32 drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h struct nvkm_fifo_engn engn[NVKM_SUBDEV_NR]; engn 18 drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); engn 168 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c const struct nvkm_disp_oclass *sclass = oclass->engn; engn 202 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c oclass->engn = root; engn 74 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c sclass->engn = oclass; engn 237 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c const struct nvkm_fifo_chan_oclass *sclass = oclass->engn; engn 265 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c oclass->engn = sclass; engn 45 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; engn 49 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (--engn->usecount) engn 61 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (engn->object) { engn 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c ret = nvkm_object_fini(engn->object, suspend); engn 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; engn 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (engn->usecount++) engn 85 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (engn->object) { engn 86 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c ret = nvkm_object_init(engn->object); engn 111 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; engn 116 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (!--engn->refcount) { engn 119 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_object_del(&engn->object); engn 138 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; engn 148 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (!engn->refcount++) { engn 159 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c &engn->object); engn 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c NULL, 0, &engn->object); engn 170 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c engn->object); engn 178 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .engn = oclass->engn, engn 182 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .parent = engn->object ? engn 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c engn->object : engn 97 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c u32 engn, save; engn 105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c engn = g84_fifo_chan_engine(engine); engn 106 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); engn 137 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; engn 144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c limit = engn->addr + engn->size - 1; engn 145 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c start = engn->addr; engn 165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c int engn = engine->subdev.index; engn 170 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); engn 18 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h } engn[NVKM_SUBDEV_NR]; engn 22 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h } engn[NVKM_SUBDEV_NR]; engn 12 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; engn 106 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; engn 113 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c limit = engn->addr + engn->size - 1; engn 114 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c start = engn->addr; engn 133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); engn 142 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c int engn = engine->subdev.index; engn 147 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); engn 18 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; engn 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c inst = chan->engn[engine->subdev.index]->addr >> 4; engn 124 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); engn 133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c const int engn = engine->subdev.index; engn 139 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); engn 109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) engn 111 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c switch (engn) { engn 112 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case NVKM_ENGINE_GR : engn = 0; break; engn 113 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case NVKM_ENGINE_MSVLD : engn = 1; break; engn 114 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case NVKM_ENGINE_MSPPP : engn = 2; break; engn 115 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case NVKM_ENGINE_MSPDEC: engn = 3; break; engn 116 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case NVKM_ENGINE_CE0 : engn = 4; break; engn 117 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case NVKM_ENGINE_CE1 : engn = 5; break; engn 122 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c return engn; engn 126 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) engn 130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c switch (engn) { engn 131 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case 0: engn = NVKM_ENGINE_GR; break; engn 132 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case 1: engn = NVKM_ENGINE_MSVLD; break; engn 133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case 2: engn = NVKM_ENGINE_MSPPP; break; engn 134 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case 3: engn = NVKM_ENGINE_MSPDEC; break; engn 135 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case 4: engn = NVKM_ENGINE_CE0; break; engn 136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c case 5: engn = NVKM_ENGINE_CE1; break; engn 141 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c return nvkm_device_engine(device, engn); engn 151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 engn, engm = 0; engn 159 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) engn 160 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c engm |= 1 << gf100_fifo_engidx(fifo, engn); engn 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) { engn 164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c if ((engine = nvkm_device_engine(device, engn))) { engn 323 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 engn; engn 326 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c for (engn = 0; engn < 6; engn++) { engn 327 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); engn 338 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c engine = gf100_fifo_engine(fifo, engn); engn 462 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) engn 466 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); engn 470 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); engn 480 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c engn, unkn, ints); engn 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, engn 55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_engine *engine = fifo->engine[engn].engine; engn 58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); engn 90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c engn, status->busy, status->faulted, engn 103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (oclass->engn == &fifo->func->chan) { engn 104 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const struct gk104_fifo_chan_user *user = oclass->engn; engn 107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (oclass->engn == &fifo->func->user) { engn 108 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const struct gk104_fifo_user_user *user = oclass->engn; engn 124 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->engn = &fifo->func->user; engn 130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->engn = &fifo->func->chan; engn 282 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int engn, runl; engn 293 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { engn 294 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if ((engine = fifo->engine[engn].engine)) { engn 307 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c static void gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn); engn 364 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c unsigned long engn, engm = fifo->runlist[runl].engm; engn 386 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for_each_set_bit(engn, &engm, fifo->engine_nr) { engn 388 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_engine_status(fifo, engn, &status); engn 391 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_engn(fifo, engn); engn 396 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) engn 398 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_engine *engine = fifo->engine[engn].engine; engn 401 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 runl = fifo->engine[engn].runl; engn 402 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const u32 engm = BIT(engn); engn 415 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_engine_status(fifo, engn, &status); engn 444 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000100 | mmui); engn 448 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_engine_status(fifo, engn, &status); engn 454 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000000); engn 460 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn); engn 475 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int engn; engn 538 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for (engn = 0; engn < fifo->engine_nr && engine; engn++) { engn 539 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (fifo->engine[engn].engine == engine) { engn 540 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_engn(fifo, engn); engn 583 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 engn; engn 592 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for (engn = 0; engn < fifo->engine_nr; engn++) { engn 595 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_engine_status(fifo, engn, &status); engn 599 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c engm |= BIT(engn); engn 602 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for_each_set_bit(engn, &engm, fifo->engine_nr) engn 603 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_engn(fifo, engn); engn 884 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int runl = mthd - NV_DEVICE_FIFO_RUNLIST_ENGINES(0), engn; engn 889 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c for_each_set_bit(engn, &engm, fifo->engine_nr) { engn 890 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if ((engine = fifo->engine[engn].engine)) engn 909 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int engn, runl, pbid, ret, i, j; engn 925 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) { engn 935 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c engn, runl, pbid, nvkm_subdev_name[engidx]); engn 937 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->engine[engn].engine = nvkm_device_engine(device, engidx); engn 938 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->engine[engn].runl = runl; engn 939 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->engine[engn].pbid = pbid; engn 940 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->engine_nr = max(fifo->engine_nr, engn + 1); engn 941 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->runlist[runl].engm |= 1 << engn; engn 114 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c u64 addr = chan->engn[engine->subdev.index].vma->addr; engn 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); engn 130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); engn 139 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c int engn = engine->subdev.index; engn 145 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); engn 149 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, engn 150 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c &chan->engn[engn].vma); engn 154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, engn 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c chan->engn[engn].vma, NULL, 0); engn 133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c u64 addr = chan->engn[engine->subdev.index].vma->addr; engn 154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); engn 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); engn 164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c int engn = engine->subdev.index; engn 170 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); engn 174 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, engn 175 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c &chan->engn[engn].vma); engn 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, engn 180 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c chan->engn[engn].vma, NULL, 0); engn 100 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c addr = chan->engn[engine->subdev.index].vma->addr; engn 54 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c const struct nvkm_sw_chan_sclass *sclass = oclass->engn; engn 66 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c oclass->engn = &sw->func->sclass[index]; engn 143 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c nvkm_top_engine(struct nvkm_device *device, int index, int *runl, int *engn) engn 152 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c *engn = info->engine;