engine_mask      2110 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	return hweight64(INTEL_INFO(i915)->engine_mask &
engine_mask       401 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
engine_mask       406 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	WARN_ON(engine_mask == 0);
engine_mask       407 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	WARN_ON(engine_mask &
engine_mask       429 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (WARN_ON(mask != engine_mask))
engine_mask       430 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		device_info->engine_mask = mask;
engine_mask        55 drivers/gpu/drm/i915/gt/intel_gt.c 			       intel_engine_mask_t engine_mask)
engine_mask        92 drivers/gpu/drm/i915/gt/intel_gt.c 		for_each_engine_masked(engine, i915, engine_mask, id)
engine_mask        37 drivers/gpu/drm/i915/gt/intel_gt.h 				    intel_engine_mask_t engine_mask);
engine_mask       146 drivers/gpu/drm/i915/gt/intel_reset.c 			 intel_engine_mask_t engine_mask,
engine_mask       175 drivers/gpu/drm/i915/gt/intel_reset.c 			intel_engine_mask_t engine_mask,
engine_mask       185 drivers/gpu/drm/i915/gt/intel_reset.c 			intel_engine_mask_t engine_mask,
engine_mask       222 drivers/gpu/drm/i915/gt/intel_reset.c 			     intel_engine_mask_t engine_mask,
engine_mask       282 drivers/gpu/drm/i915/gt/intel_reset.c 			      intel_engine_mask_t engine_mask,
engine_mask       295 drivers/gpu/drm/i915/gt/intel_reset.c 	if (engine_mask == ALL_ENGINES) {
engine_mask       301 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine_mask       406 drivers/gpu/drm/i915/gt/intel_reset.c 			       intel_engine_mask_t engine_mask,
engine_mask       424 drivers/gpu/drm/i915/gt/intel_reset.c 	if (engine_mask == ALL_ENGINES) {
engine_mask       428 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine_mask       437 drivers/gpu/drm/i915/gt/intel_reset.c 	if (engine_mask != ALL_ENGINES)
engine_mask       438 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
engine_mask       489 drivers/gpu/drm/i915/gt/intel_reset.c 			      intel_engine_mask_t engine_mask,
engine_mask       497 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine_mask       518 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = gen11_reset_engines(gt, engine_mask, retry);
engine_mask       520 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = gen6_reset_engines(gt, engine_mask, retry);
engine_mask       523 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
engine_mask       530 drivers/gpu/drm/i915/gt/intel_reset.c 			  intel_engine_mask_t engine_mask,
engine_mask       551 drivers/gpu/drm/i915/gt/intel_reset.c int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
engine_mask       553 drivers/gpu/drm/i915/gt/intel_reset.c 	const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
engine_mask       568 drivers/gpu/drm/i915/gt/intel_reset.c 		GEM_TRACE("engine_mask=%x\n", engine_mask);
engine_mask       570 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = reset(gt, engine_mask, retry);
engine_mask      1081 drivers/gpu/drm/i915/gt/intel_reset.c 				  u32 engine_mask,
engine_mask      1102 drivers/gpu/drm/i915/gt/intel_reset.c 		intel_gt_reset(gt, engine_mask, reason);
engine_mask      1125 drivers/gpu/drm/i915/gt/intel_reset.c 			   intel_engine_mask_t engine_mask,
engine_mask      1154 drivers/gpu/drm/i915/gt/intel_reset.c 	engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
engine_mask      1157 drivers/gpu/drm/i915/gt/intel_reset.c 		i915_capture_error_state(gt->i915, engine_mask, msg);
engine_mask      1158 drivers/gpu/drm/i915/gt/intel_reset.c 		intel_gt_clear_error_registers(gt, engine_mask);
engine_mask      1166 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine_mask      1173 drivers/gpu/drm/i915/gt/intel_reset.c 				engine_mask &= ~engine->mask;
engine_mask      1180 drivers/gpu/drm/i915/gt/intel_reset.c 	if (!engine_mask)
engine_mask      1202 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_gt_reset_global(gt, engine_mask, msg);
engine_mask        28 drivers/gpu/drm/i915/gt/intel_reset.h 			   intel_engine_mask_t engine_mask,
engine_mask        48 drivers/gpu/drm/i915/gt/intel_reset.h int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
engine_mask       530 drivers/gpu/drm/i915/gvt/execlist.c 			   intel_engine_mask_t engine_mask)
engine_mask       537 drivers/gpu/drm/i915/gvt/execlist.c 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
engine_mask       545 drivers/gpu/drm/i915/gvt/execlist.c 			   intel_engine_mask_t engine_mask)
engine_mask       551 drivers/gpu/drm/i915/gvt/execlist.c 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
engine_mask       556 drivers/gpu/drm/i915/gvt/execlist.c 			 intel_engine_mask_t engine_mask)
engine_mask       558 drivers/gpu/drm/i915/gvt/execlist.c 	reset_execlist(vgpu, engine_mask);
engine_mask       183 drivers/gpu/drm/i915/gvt/execlist.h 			       intel_engine_mask_t engine_mask);
engine_mask       144 drivers/gpu/drm/i915/gvt/gvt.h 	int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
engine_mask       145 drivers/gpu/drm/i915/gvt/gvt.h 	void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
engine_mask       146 drivers/gpu/drm/i915/gvt/gvt.h 	void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
engine_mask       488 drivers/gpu/drm/i915/gvt/gvt.h 				 intel_engine_mask_t engine_mask);
engine_mask       314 drivers/gpu/drm/i915/gvt/handlers.c 	intel_engine_mask_t engine_mask = 0;
engine_mask       322 drivers/gpu/drm/i915/gvt/handlers.c 		engine_mask = ALL_ENGINES;
engine_mask       326 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(RCS0);
engine_mask       330 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(VCS0);
engine_mask       334 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(BCS0);
engine_mask       338 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(VECS0);
engine_mask       342 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(VCS1);
engine_mask       344 drivers/gpu/drm/i915/gvt/handlers.c 		engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
engine_mask       348 drivers/gpu/drm/i915/gvt/handlers.c 	intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
engine_mask       885 drivers/gpu/drm/i915/gvt/scheduler.c 				intel_engine_mask_t engine_mask)
engine_mask       894 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
engine_mask      1195 drivers/gpu/drm/i915/gvt/scheduler.c 				 intel_engine_mask_t engine_mask)
engine_mask      1202 drivers/gpu/drm/i915/gvt/scheduler.c 	intel_vgpu_clean_workloads(vgpu, engine_mask);
engine_mask      1203 drivers/gpu/drm/i915/gvt/scheduler.c 	s->ops->reset(vgpu, engine_mask);
engine_mask      1330 drivers/gpu/drm/i915/gvt/scheduler.c 				     intel_engine_mask_t engine_mask,
engine_mask      1343 drivers/gpu/drm/i915/gvt/scheduler.c 	if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
engine_mask      1347 drivers/gpu/drm/i915/gvt/scheduler.c 		s->ops->clean(vgpu, engine_mask);
engine_mask      1357 drivers/gpu/drm/i915/gvt/scheduler.c 	ret = ops[interface]->init(vgpu, engine_mask);
engine_mask       146 drivers/gpu/drm/i915/gvt/scheduler.h 				 intel_engine_mask_t engine_mask);
engine_mask       151 drivers/gpu/drm/i915/gvt/scheduler.h 				     intel_engine_mask_t engine_mask,
engine_mask       164 drivers/gpu/drm/i915/gvt/scheduler.h 				intel_engine_mask_t engine_mask);
engine_mask       533 drivers/gpu/drm/i915/gvt/vgpu.c 				 intel_engine_mask_t engine_mask)
engine_mask       537 drivers/gpu/drm/i915/gvt/vgpu.c 	intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
engine_mask       541 drivers/gpu/drm/i915/gvt/vgpu.c 		     vgpu->id, dmlr, engine_mask);
engine_mask       558 drivers/gpu/drm/i915/gvt/vgpu.c 	if (engine_mask == ALL_ENGINES || dmlr) {
engine_mask      1800 drivers/gpu/drm/i915/i915_drv.h 	for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
engine_mask      2067 drivers/gpu/drm/i915/i915_drv.h #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
engine_mask      2072 drivers/gpu/drm/i915/i915_drv.h 	(INTEL_INFO(dev_priv)->engine_mask &				\
engine_mask      1735 drivers/gpu/drm/i915/i915_gpu_error.c 			      intel_engine_mask_t engine_mask,
engine_mask      1752 drivers/gpu/drm/i915/i915_gpu_error.c 	dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg));
engine_mask       203 drivers/gpu/drm/i915/i915_gpu_error.h 			      intel_engine_mask_t engine_mask,
engine_mask       230 drivers/gpu/drm/i915/i915_gpu_error.h 					    u32 engine_mask,
engine_mask       158 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0), \
engine_mask       175 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0), \
engine_mask       209 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0), \
engine_mask       294 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0), \
engine_mask       324 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0),
engine_mask       334 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0),
engine_mask       342 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0), \
engine_mask       369 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
engine_mask       417 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
engine_mask       483 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
engine_mask       493 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
engine_mask       556 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask =
engine_mask       566 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
engine_mask       615 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = \
engine_mask       633 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
engine_mask       689 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask =
engine_mask       710 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask =
engine_mask       759 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask =
engine_mask       767 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
engine_mask       798 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask =
engine_mask      1017 drivers/gpu/drm/i915/intel_device_info.c 			info->engine_mask &= ~BIT(_VCS(i));
engine_mask      1039 drivers/gpu/drm/i915/intel_device_info.c 			info->engine_mask &= ~BIT(_VECS(i));
engine_mask       153 drivers/gpu/drm/i915/intel_device_info.h 	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
engine_mask       203 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	mkwrite_device_info(i915)->engine_mask = BIT(0);
engine_mask       616 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	u32 engine_mask;
engine_mask       640 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	engine_mask = mt76_rr(dev, MT_BBP(DFS, 1));
engine_mask       641 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	if (!(engine_mask & 0xf))
engine_mask       647 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (!(engine_mask & (1 << i)))