engine_clock     1850 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				    u32 engine_clock,
engine_clock     4739 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					    u32 engine_clock)
engine_clock     4752 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
engine_clock     5245 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				    u32 engine_clock,
engine_clock     5264 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					     engine_clock, false, &dividers);
engine_clock     5270 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
engine_clock     5287 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
engine_clock     5303 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	sclk->sclk_value = engine_clock;
engine_clock     5315 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				  u32 engine_clock,
engine_clock     5321 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
engine_clock     5336 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				  u32 engine_clock,
engine_clock      174 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		uint32_t engine_clock,
engine_clock      183 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) |
engine_clock     1290 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		const uint32_t engine_clock,
engine_clock     1294 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 			ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
engine_clock      295 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
engine_clock      297 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
engine_clock      755 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->levels[index].engine_clock = 0;
engine_clock      961 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
engine_clock      962 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
engine_clock       76 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h 	uint32_t engine_clock;
engine_clock     2919 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
engine_clock     2920 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
engine_clock     2964 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	sclk = smu7_ps->performance_levels[0].engine_clock;
engine_clock     2979 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_ps->performance_levels[0].engine_clock = sclk;
engine_clock     2982 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_ps->performance_levels[1].engine_clock =
engine_clock     2983 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		(smu7_ps->performance_levels[1].engine_clock >=
engine_clock     2984 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smu7_ps->performance_levels[0].engine_clock) ?
engine_clock     2985 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 						smu7_ps->performance_levels[1].engine_clock :
engine_clock     2986 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 						smu7_ps->performance_levels[0].engine_clock;
engine_clock     3004 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
engine_clock     3052 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smu7_ps->performance_levels[0].engine_clock;
engine_clock     3055 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				[smu7_ps->performance_level_count-1].engine_clock;
engine_clock     3096 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
engine_clock     3186 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
engine_clock     3189 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
engine_clock     3202 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
engine_clock     3205 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
engine_clock     3326 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	uint32_t engine_clock, memory_clock;
engine_clock     3329 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
engine_clock     3351 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	performance_level->engine_clock = engine_clock;
engine_clock     3601 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			[smu7_ps->performance_level_count - 1].engine_clock;
engine_clock     3655 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		sclk = smu7_ps->performance_levels[i].engine_clock;
engine_clock     3837 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_ps->performance_levels[0].engine_clock,
engine_clock     3838 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_ps->performance_levels[high_limit_count].engine_clock);
engine_clock     4189 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		  (pl1->engine_clock == pl2->engine_clock) &&
engine_clock     4600 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
engine_clock     5089 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	level->coreClock = ps->performance_levels[i].engine_clock;
engine_clock       56 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  engine_clock;
engine_clock      307 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	uint32_t engine_clock;
engine_clock     1621 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		uint32_t engine_clock,
engine_clock     1632 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				engine_clock, memory_clock);
engine_clock      796 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
engine_clock      811 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
engine_clock      842 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
engine_clock      863 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	sclk->SclkFrequency        = engine_clock;
engine_clock      892 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 						uint32_t engine_clock,
engine_clock      898 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
engine_clock      902 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
engine_clock      908 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	graphic_level->SclkFrequency = engine_clock;
engine_clock      914 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				engine_clock,
engine_clock      937 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				smu7_get_sleep_divider_id_from_clock(engine_clock,
engine_clock     1584 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		uint32_t engine_clock,
engine_clock     1595 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				engine_clock, memory_clock);
engine_clock      539 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
engine_clock      554 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
engine_clock      585 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
engine_clock      606 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	sclk->SclkFrequency        = engine_clock;
engine_clock      617 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 						uint32_t engine_clock,
engine_clock      627 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
engine_clock      636 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		vdd_dep_table, engine_clock,
engine_clock      643 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	graphic_level->SclkFrequency = engine_clock;
engine_clock      664 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				smu7_get_sleep_divider_id_from_clock(engine_clock,
engine_clock     1459 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		uint32_t engine_clock,
engine_clock     1470 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				engine_clock, memory_clock);
engine_clock     2496 drivers/gpu/drm/radeon/ci_dpm.c 					const u32 engine_clock,
engine_clock     2510 drivers/gpu/drm/radeon/ci_dpm.c 			tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
engine_clock     2514 drivers/gpu/drm/radeon/ci_dpm.c 			tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
engine_clock     3160 drivers/gpu/drm/radeon/ci_dpm.c 				    u32 engine_clock,
engine_clock     3176 drivers/gpu/drm/radeon/ci_dpm.c 					     engine_clock, false, &dividers);
engine_clock     3189 drivers/gpu/drm/radeon/ci_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
engine_clock     3205 drivers/gpu/drm/radeon/ci_dpm.c 	sclk->SclkFrequency = engine_clock;
engine_clock     3216 drivers/gpu/drm/radeon/ci_dpm.c 					    u32 engine_clock,
engine_clock     3223 drivers/gpu/drm/radeon/ci_dpm.c 	ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
engine_clock     3229 drivers/gpu/drm/radeon/ci_dpm.c 					    engine_clock, &graphic_level->MinVddc);
engine_clock     3233 drivers/gpu/drm/radeon/ci_dpm.c 	graphic_level->SclkFrequency = engine_clock;
engine_clock     3241 drivers/gpu/drm/radeon/ci_dpm.c 						      engine_clock,
engine_clock     3256 drivers/gpu/drm/radeon/ci_dpm.c 										   engine_clock,
engine_clock      475 drivers/gpu/drm/radeon/cypress_dpm.c 				       u32 engine_clock, u32 memory_clock,
engine_clock      905 drivers/gpu/drm/radeon/cypress_dpm.c 				 u32 engine_clock, u32 memory_clock)
engine_clock      909 drivers/gpu/drm/radeon/cypress_dpm.c 	u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
engine_clock      125 drivers/gpu/drm/radeon/cypress_dpm.h 				 u32 engine_clock, u32 memory_clock);
engine_clock     1999 drivers/gpu/drm/radeon/ni_dpm.c 				    u32 engine_clock,
engine_clock     2018 drivers/gpu/drm/radeon/ni_dpm.c 					     engine_clock, false, &dividers);
engine_clock     2025 drivers/gpu/drm/radeon/ni_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
engine_clock     2042 drivers/gpu/drm/radeon/ni_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
engine_clock     2058 drivers/gpu/drm/radeon/ni_dpm.c 	sclk->sclk_value = engine_clock;
engine_clock     2070 drivers/gpu/drm/radeon/ni_dpm.c 				  u32 engine_clock,
engine_clock     2076 drivers/gpu/drm/radeon/ni_dpm.c 	ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
engine_clock     2161 drivers/gpu/drm/radeon/ni_dpm.c 				  u32 engine_clock,
engine_clock      782 drivers/gpu/drm/radeon/rv6xx_dpm.c 					 u32 engine_clock)
engine_clock      791 drivers/gpu/drm/radeon/rv6xx_dpm.c 	return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
engine_clock       40 drivers/gpu/drm/radeon/rv730_dpm.c 			      u32 engine_clock,
engine_clock       57 drivers/gpu/drm/radeon/rv730_dpm.c 					     engine_clock, false, &dividers);
engine_clock       69 drivers/gpu/drm/radeon/rv730_dpm.c 	tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
engine_clock       92 drivers/gpu/drm/radeon/rv730_dpm.c 		u32 vco_freq = engine_clock * post_divider;
engine_clock      108 drivers/gpu/drm/radeon/rv730_dpm.c 	sclk->sclk_value = cpu_to_be32(engine_clock);
engine_clock      119 drivers/gpu/drm/radeon/rv730_dpm.c 			      u32 engine_clock, u32 memory_clock,
engine_clock      120 drivers/gpu/drm/radeon/rv740_dpm.c int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
engine_clock      137 drivers/gpu/drm/radeon/rv740_dpm.c 					     engine_clock, false, &dividers);
engine_clock      143 drivers/gpu/drm/radeon/rv740_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
engine_clock      160 drivers/gpu/drm/radeon/rv740_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
engine_clock      176 drivers/gpu/drm/radeon/rv740_dpm.c 	sclk->sclk_value = cpu_to_be32(engine_clock);
engine_clock      187 drivers/gpu/drm/radeon/rv740_dpm.c 			      u32 engine_clock, u32 memory_clock,
engine_clock      386 drivers/gpu/drm/radeon/rv770_dpm.c 				     u32 engine_clock, u32 memory_clock,
engine_clock      484 drivers/gpu/drm/radeon/rv770_dpm.c 				     u32 engine_clock,
engine_clock      506 drivers/gpu/drm/radeon/rv770_dpm.c 					     engine_clock, false, &dividers);
engine_clock      517 drivers/gpu/drm/radeon/rv770_dpm.c 	tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
engine_clock      539 drivers/gpu/drm/radeon/rv770_dpm.c 		u32 vco_freq = engine_clock * post_divider;
engine_clock      555 drivers/gpu/drm/radeon/rv770_dpm.c 	sclk->sclk_value = cpu_to_be32(engine_clock);
engine_clock      722 drivers/gpu/drm/radeon/rv770_dpm.c 					u32 engine_clock)
engine_clock      733 drivers/gpu/drm/radeon/rv770_dpm.c 	mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
engine_clock      181 drivers/gpu/drm/radeon/rv770_dpm.h 			      u32 engine_clock,
engine_clock      184 drivers/gpu/drm/radeon/rv770_dpm.h 			      u32 engine_clock, u32 memory_clock,
engine_clock      202 drivers/gpu/drm/radeon/rv770_dpm.h int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
engine_clock      205 drivers/gpu/drm/radeon/rv770_dpm.h 			      u32 engine_clock, u32 memory_clock,
engine_clock      227 drivers/gpu/drm/radeon/rv770_dpm.h 					u32 engine_clock);
engine_clock     1759 drivers/gpu/drm/radeon/si_dpm.c 				    u32 engine_clock,
engine_clock     4275 drivers/gpu/drm/radeon/si_dpm.c 					    u32 engine_clock)
engine_clock     4288 drivers/gpu/drm/radeon/si_dpm.c 	mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
engine_clock     4783 drivers/gpu/drm/radeon/si_dpm.c 				    u32 engine_clock,
engine_clock     4802 drivers/gpu/drm/radeon/si_dpm.c 					     engine_clock, false, &dividers);
engine_clock     4808 drivers/gpu/drm/radeon/si_dpm.c 	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
engine_clock     4825 drivers/gpu/drm/radeon/si_dpm.c 		u32 vco_freq = engine_clock * dividers.post_div;
engine_clock     4841 drivers/gpu/drm/radeon/si_dpm.c 	sclk->sclk_value = engine_clock;
engine_clock     4853 drivers/gpu/drm/radeon/si_dpm.c 				  u32 engine_clock,
engine_clock     4859 drivers/gpu/drm/radeon/si_dpm.c 	ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
engine_clock     4874 drivers/gpu/drm/radeon/si_dpm.c 				  u32 engine_clock,