engine             24 crypto/crypto_engine.c static void crypto_finalize_request(struct crypto_engine *engine,
engine             32 crypto/crypto_engine.c 	spin_lock_irqsave(&engine->queue_lock, flags);
engine             33 crypto/crypto_engine.c 	if (engine->cur_req == req)
engine             35 crypto/crypto_engine.c 	spin_unlock_irqrestore(&engine->queue_lock, flags);
engine             39 crypto/crypto_engine.c 		if (engine->cur_req_prepared &&
engine             41 crypto/crypto_engine.c 			ret = enginectx->op.unprepare_request(engine, req);
engine             43 crypto/crypto_engine.c 				dev_err(engine->dev, "failed to unprepare request\n");
engine             45 crypto/crypto_engine.c 		spin_lock_irqsave(&engine->queue_lock, flags);
engine             46 crypto/crypto_engine.c 		engine->cur_req = NULL;
engine             47 crypto/crypto_engine.c 		engine->cur_req_prepared = false;
engine             48 crypto/crypto_engine.c 		spin_unlock_irqrestore(&engine->queue_lock, flags);
engine             53 crypto/crypto_engine.c 	kthread_queue_work(engine->kworker, &engine->pump_requests);
engine             65 crypto/crypto_engine.c static void crypto_pump_requests(struct crypto_engine *engine,
engine             74 crypto/crypto_engine.c 	spin_lock_irqsave(&engine->queue_lock, flags);
engine             77 crypto/crypto_engine.c 	if (engine->cur_req)
engine             81 crypto/crypto_engine.c 	if (engine->idling) {
engine             82 crypto/crypto_engine.c 		kthread_queue_work(engine->kworker, &engine->pump_requests);
engine             87 crypto/crypto_engine.c 	if (!crypto_queue_len(&engine->queue) || !engine->running) {
engine             88 crypto/crypto_engine.c 		if (!engine->busy)
engine             93 crypto/crypto_engine.c 			kthread_queue_work(engine->kworker,
engine             94 crypto/crypto_engine.c 					   &engine->pump_requests);
engine             98 crypto/crypto_engine.c 		engine->busy = false;
engine             99 crypto/crypto_engine.c 		engine->idling = true;
engine            100 crypto/crypto_engine.c 		spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            102 crypto/crypto_engine.c 		if (engine->unprepare_crypt_hardware &&
engine            103 crypto/crypto_engine.c 		    engine->unprepare_crypt_hardware(engine))
engine            104 crypto/crypto_engine.c 			dev_err(engine->dev, "failed to unprepare crypt hardware\n");
engine            106 crypto/crypto_engine.c 		spin_lock_irqsave(&engine->queue_lock, flags);
engine            107 crypto/crypto_engine.c 		engine->idling = false;
engine            112 crypto/crypto_engine.c 	backlog = crypto_get_backlog(&engine->queue);
engine            113 crypto/crypto_engine.c 	async_req = crypto_dequeue_request(&engine->queue);
engine            117 crypto/crypto_engine.c 	engine->cur_req = async_req;
engine            121 crypto/crypto_engine.c 	if (engine->busy)
engine            124 crypto/crypto_engine.c 		engine->busy = true;
engine            126 crypto/crypto_engine.c 	spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            129 crypto/crypto_engine.c 	if (!was_busy && engine->prepare_crypt_hardware) {
engine            130 crypto/crypto_engine.c 		ret = engine->prepare_crypt_hardware(engine);
engine            132 crypto/crypto_engine.c 			dev_err(engine->dev, "failed to prepare crypt hardware\n");
engine            140 crypto/crypto_engine.c 		ret = enginectx->op.prepare_request(engine, async_req);
engine            142 crypto/crypto_engine.c 			dev_err(engine->dev, "failed to prepare request: %d\n",
engine            146 crypto/crypto_engine.c 		engine->cur_req_prepared = true;
engine            149 crypto/crypto_engine.c 		dev_err(engine->dev, "failed to do request\n");
engine            153 crypto/crypto_engine.c 	ret = enginectx->op.do_one_request(engine, async_req);
engine            155 crypto/crypto_engine.c 		dev_err(engine->dev, "Failed to do one request from queue: %d\n", ret);
engine            161 crypto/crypto_engine.c 	crypto_finalize_request(engine, async_req, ret);
engine            165 crypto/crypto_engine.c 	spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            170 crypto/crypto_engine.c 	struct crypto_engine *engine =
engine            173 crypto/crypto_engine.c 	crypto_pump_requests(engine, true);
engine            181 crypto/crypto_engine.c static int crypto_transfer_request(struct crypto_engine *engine,
engine            188 crypto/crypto_engine.c 	spin_lock_irqsave(&engine->queue_lock, flags);
engine            190 crypto/crypto_engine.c 	if (!engine->running) {
engine            191 crypto/crypto_engine.c 		spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            195 crypto/crypto_engine.c 	ret = crypto_enqueue_request(&engine->queue, req);
engine            197 crypto/crypto_engine.c 	if (!engine->busy && need_pump)
engine            198 crypto/crypto_engine.c 		kthread_queue_work(engine->kworker, &engine->pump_requests);
engine            200 crypto/crypto_engine.c 	spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            210 crypto/crypto_engine.c static int crypto_transfer_request_to_engine(struct crypto_engine *engine,
engine            213 crypto/crypto_engine.c 	return crypto_transfer_request(engine, req, true);
engine            223 crypto/crypto_engine.c int crypto_transfer_ablkcipher_request_to_engine(struct crypto_engine *engine,
engine            226 crypto/crypto_engine.c 	return crypto_transfer_request_to_engine(engine, &req->base);
engine            236 crypto/crypto_engine.c int crypto_transfer_aead_request_to_engine(struct crypto_engine *engine,
engine            239 crypto/crypto_engine.c 	return crypto_transfer_request_to_engine(engine, &req->base);
engine            249 crypto/crypto_engine.c int crypto_transfer_akcipher_request_to_engine(struct crypto_engine *engine,
engine            252 crypto/crypto_engine.c 	return crypto_transfer_request_to_engine(engine, &req->base);
engine            262 crypto/crypto_engine.c int crypto_transfer_hash_request_to_engine(struct crypto_engine *engine,
engine            265 crypto/crypto_engine.c 	return crypto_transfer_request_to_engine(engine, &req->base);
engine            275 crypto/crypto_engine.c int crypto_transfer_skcipher_request_to_engine(struct crypto_engine *engine,
engine            278 crypto/crypto_engine.c 	return crypto_transfer_request_to_engine(engine, &req->base);
engine            290 crypto/crypto_engine.c void crypto_finalize_ablkcipher_request(struct crypto_engine *engine,
engine            293 crypto/crypto_engine.c 	return crypto_finalize_request(engine, &req->base, err);
engine            304 crypto/crypto_engine.c void crypto_finalize_aead_request(struct crypto_engine *engine,
engine            307 crypto/crypto_engine.c 	return crypto_finalize_request(engine, &req->base, err);
engine            318 crypto/crypto_engine.c void crypto_finalize_akcipher_request(struct crypto_engine *engine,
engine            321 crypto/crypto_engine.c 	return crypto_finalize_request(engine, &req->base, err);
engine            332 crypto/crypto_engine.c void crypto_finalize_hash_request(struct crypto_engine *engine,
engine            335 crypto/crypto_engine.c 	return crypto_finalize_request(engine, &req->base, err);
engine            346 crypto/crypto_engine.c void crypto_finalize_skcipher_request(struct crypto_engine *engine,
engine            349 crypto/crypto_engine.c 	return crypto_finalize_request(engine, &req->base, err);
engine            359 crypto/crypto_engine.c int crypto_engine_start(struct crypto_engine *engine)
engine            363 crypto/crypto_engine.c 	spin_lock_irqsave(&engine->queue_lock, flags);
engine            365 crypto/crypto_engine.c 	if (engine->running || engine->busy) {
engine            366 crypto/crypto_engine.c 		spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            370 crypto/crypto_engine.c 	engine->running = true;
engine            371 crypto/crypto_engine.c 	spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            373 crypto/crypto_engine.c 	kthread_queue_work(engine->kworker, &engine->pump_requests);
engine            385 crypto/crypto_engine.c int crypto_engine_stop(struct crypto_engine *engine)
engine            391 crypto/crypto_engine.c 	spin_lock_irqsave(&engine->queue_lock, flags);
engine            397 crypto/crypto_engine.c 	while ((crypto_queue_len(&engine->queue) || engine->busy) && limit--) {
engine            398 crypto/crypto_engine.c 		spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            400 crypto/crypto_engine.c 		spin_lock_irqsave(&engine->queue_lock, flags);
engine            403 crypto/crypto_engine.c 	if (crypto_queue_len(&engine->queue) || engine->busy)
engine            406 crypto/crypto_engine.c 		engine->running = false;
engine            408 crypto/crypto_engine.c 	spin_unlock_irqrestore(&engine->queue_lock, flags);
engine            411 crypto/crypto_engine.c 		dev_warn(engine->dev, "could not stop engine\n");
engine            429 crypto/crypto_engine.c 	struct crypto_engine *engine;
engine            434 crypto/crypto_engine.c 	engine = devm_kzalloc(dev, sizeof(*engine), GFP_KERNEL);
engine            435 crypto/crypto_engine.c 	if (!engine)
engine            438 crypto/crypto_engine.c 	engine->dev = dev;
engine            439 crypto/crypto_engine.c 	engine->rt = rt;
engine            440 crypto/crypto_engine.c 	engine->running = false;
engine            441 crypto/crypto_engine.c 	engine->busy = false;
engine            442 crypto/crypto_engine.c 	engine->idling = false;
engine            443 crypto/crypto_engine.c 	engine->cur_req_prepared = false;
engine            444 crypto/crypto_engine.c 	engine->priv_data = dev;
engine            445 crypto/crypto_engine.c 	snprintf(engine->name, sizeof(engine->name),
engine            448 crypto/crypto_engine.c 	crypto_init_queue(&engine->queue, CRYPTO_ENGINE_MAX_QLEN);
engine            449 crypto/crypto_engine.c 	spin_lock_init(&engine->queue_lock);
engine            451 crypto/crypto_engine.c 	engine->kworker = kthread_create_worker(0, "%s", engine->name);
engine            452 crypto/crypto_engine.c 	if (IS_ERR(engine->kworker)) {
engine            456 crypto/crypto_engine.c 	kthread_init_work(&engine->pump_requests, crypto_pump_work);
engine            458 crypto/crypto_engine.c 	if (engine->rt) {
engine            460 crypto/crypto_engine.c 		sched_setscheduler(engine->kworker->task, SCHED_FIFO, &param);
engine            463 crypto/crypto_engine.c 	return engine;
engine            473 crypto/crypto_engine.c int crypto_engine_exit(struct crypto_engine *engine)
engine            477 crypto/crypto_engine.c 	ret = crypto_engine_stop(engine);
engine            481 crypto/crypto_engine.c 	kthread_destroy_worker(engine->kworker);
engine            158 drivers/crypto/ccp/ccp-crypto-aes-cmac.c 	rctx->cmd.engine = CCP_ENGINE_AES;
engine            119 drivers/crypto/ccp/ccp-crypto-aes-galois.c 	rctx->cmd.engine = CCP_ENGINE_AES;
engine            170 drivers/crypto/ccp/ccp-crypto-aes-xts.c 	rctx->cmd.engine = CCP_ENGINE_XTS_AES_128;
engine             95 drivers/crypto/ccp/ccp-crypto-aes.c 	rctx->cmd.engine = CCP_ENGINE_AES;
engine             89 drivers/crypto/ccp/ccp-crypto-des3.c 	rctx->cmd.engine = CCP_ENGINE_DES3;
engine             73 drivers/crypto/ccp/ccp-crypto-rsa.c 	rctx->cmd.engine = CCP_ENGINE_RSA;
engine            133 drivers/crypto/ccp/ccp-crypto-sha.c 	rctx->cmd.engine = CCP_ENGINE_SHA;
engine             93 drivers/crypto/ccp/ccp-crypto.h 	enum ccp_engine engine;
engine            162 drivers/crypto/ccp/ccp-crypto.h 	enum ccp_engine engine;
engine            162 drivers/crypto/ccp/ccp-dev-v5.c #define CCP5_CMD_ENGINE(p)	(CCP5_CMD_DW0(p).engine)
engine            585 drivers/crypto/ccp/ccp-dev.h 	unsigned int engine:4;
engine            431 drivers/crypto/ccp/ccp-dmaengine.c 		ccp_cmd->engine = CCP_ENGINE_PASSTHRU;
engine           1785 drivers/crypto/ccp/ccp-ops.c 		hmac_cmd.engine = CCP_ENGINE_SHA;
engine           2456 drivers/crypto/ccp/ccp-ops.c 	switch (cmd->engine) {
engine             38 drivers/crypto/marvell/cesa.c mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
engine             43 drivers/crypto/marvell/cesa.c 	*backlog = crypto_get_backlog(&engine->queue);
engine             44 drivers/crypto/marvell/cesa.c 	req = crypto_dequeue_request(&engine->queue);
engine             52 drivers/crypto/marvell/cesa.c static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine)
engine             58 drivers/crypto/marvell/cesa.c 	spin_lock_bh(&engine->lock);
engine             59 drivers/crypto/marvell/cesa.c 	if (!engine->req) {
engine             60 drivers/crypto/marvell/cesa.c 		req = mv_cesa_dequeue_req_locked(engine, &backlog);
engine             61 drivers/crypto/marvell/cesa.c 		engine->req = req;
engine             63 drivers/crypto/marvell/cesa.c 	spin_unlock_bh(&engine->lock);
engine             75 drivers/crypto/marvell/cesa.c static int mv_cesa_std_process(struct mv_cesa_engine *engine, u32 status)
engine             81 drivers/crypto/marvell/cesa.c 	req = engine->req;
engine             87 drivers/crypto/marvell/cesa.c 		mv_cesa_engine_enqueue_complete_request(engine, req);
engine             95 drivers/crypto/marvell/cesa.c static int mv_cesa_int_process(struct mv_cesa_engine *engine, u32 status)
engine             97 drivers/crypto/marvell/cesa.c 	if (engine->chain.first && engine->chain.last)
engine             98 drivers/crypto/marvell/cesa.c 		return mv_cesa_tdma_process(engine, status);
engine            100 drivers/crypto/marvell/cesa.c 	return mv_cesa_std_process(engine, status);
engine            115 drivers/crypto/marvell/cesa.c 	struct mv_cesa_engine *engine = priv;
engine            124 drivers/crypto/marvell/cesa.c 		mask = mv_cesa_get_int_mask(engine);
engine            125 drivers/crypto/marvell/cesa.c 		status = readl(engine->regs + CESA_SA_INT_STATUS);
engine            134 drivers/crypto/marvell/cesa.c 		writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);
engine            135 drivers/crypto/marvell/cesa.c 		writel(~status, engine->regs + CESA_SA_INT_STATUS);
engine            138 drivers/crypto/marvell/cesa.c 		res = mv_cesa_int_process(engine, status & mask);
engine            141 drivers/crypto/marvell/cesa.c 		spin_lock_bh(&engine->lock);
engine            142 drivers/crypto/marvell/cesa.c 		req = engine->req;
engine            144 drivers/crypto/marvell/cesa.c 			engine->req = NULL;
engine            145 drivers/crypto/marvell/cesa.c 		spin_unlock_bh(&engine->lock);
engine            153 drivers/crypto/marvell/cesa.c 		mv_cesa_rearm_engine(engine);
engine            157 drivers/crypto/marvell/cesa.c 			req = mv_cesa_engine_dequeue_complete_request(engine);
engine            173 drivers/crypto/marvell/cesa.c 	struct mv_cesa_engine *engine = creq->engine;
engine            175 drivers/crypto/marvell/cesa.c 	spin_lock_bh(&engine->lock);
engine            176 drivers/crypto/marvell/cesa.c 	ret = crypto_enqueue_request(&engine->queue, req);
engine            179 drivers/crypto/marvell/cesa.c 		mv_cesa_tdma_chain(engine, creq);
engine            180 drivers/crypto/marvell/cesa.c 	spin_unlock_bh(&engine->lock);
engine            185 drivers/crypto/marvell/cesa.c 	mv_cesa_rearm_engine(engine);
engine            315 drivers/crypto/marvell/cesa.c mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine,
engine            318 drivers/crypto/marvell/cesa.c 	void __iomem *iobase = engine->regs;
engine            377 drivers/crypto/marvell/cesa.c 	struct mv_cesa_engine *engine = &cesa->engines[idx];
engine            381 drivers/crypto/marvell/cesa.c 	engine->pool = of_gen_pool_get(cesa->dev->of_node,
engine            383 drivers/crypto/marvell/cesa.c 	if (engine->pool) {
engine            384 drivers/crypto/marvell/cesa.c 		engine->sram = gen_pool_dma_alloc(engine->pool,
engine            386 drivers/crypto/marvell/cesa.c 						  &engine->sram_dma);
engine            387 drivers/crypto/marvell/cesa.c 		if (engine->sram)
engine            390 drivers/crypto/marvell/cesa.c 		engine->pool = NULL;
engine            406 drivers/crypto/marvell/cesa.c 	engine->sram = devm_ioremap_resource(cesa->dev, res);
engine            407 drivers/crypto/marvell/cesa.c 	if (IS_ERR(engine->sram))
engine            408 drivers/crypto/marvell/cesa.c 		return PTR_ERR(engine->sram);
engine            410 drivers/crypto/marvell/cesa.c 	engine->sram_dma = dma_map_resource(cesa->dev, res->start,
engine            413 drivers/crypto/marvell/cesa.c 	if (dma_mapping_error(cesa->dev, engine->sram_dma))
engine            422 drivers/crypto/marvell/cesa.c 	struct mv_cesa_engine *engine = &cesa->engines[idx];
engine            424 drivers/crypto/marvell/cesa.c 	if (engine->pool)
engine            425 drivers/crypto/marvell/cesa.c 		gen_pool_free(engine->pool, (unsigned long)engine->sram,
engine            428 drivers/crypto/marvell/cesa.c 		dma_unmap_resource(cesa->dev, engine->sram_dma,
engine            492 drivers/crypto/marvell/cesa.c 		struct mv_cesa_engine *engine = &cesa->engines[i];
engine            495 drivers/crypto/marvell/cesa.c 		engine->id = i;
engine            496 drivers/crypto/marvell/cesa.c 		spin_lock_init(&engine->lock);
engine            513 drivers/crypto/marvell/cesa.c 		engine->clk = devm_clk_get(dev, res_name);
engine            514 drivers/crypto/marvell/cesa.c 		if (IS_ERR(engine->clk)) {
engine            515 drivers/crypto/marvell/cesa.c 			engine->clk = devm_clk_get(dev, NULL);
engine            516 drivers/crypto/marvell/cesa.c 			if (IS_ERR(engine->clk))
engine            517 drivers/crypto/marvell/cesa.c 				engine->clk = NULL;
engine            521 drivers/crypto/marvell/cesa.c 		engine->zclk = devm_clk_get(dev, res_name);
engine            522 drivers/crypto/marvell/cesa.c 		if (IS_ERR(engine->zclk))
engine            523 drivers/crypto/marvell/cesa.c 			engine->zclk = NULL;
engine            525 drivers/crypto/marvell/cesa.c 		ret = clk_prepare_enable(engine->clk);
engine            529 drivers/crypto/marvell/cesa.c 		ret = clk_prepare_enable(engine->zclk);
engine            533 drivers/crypto/marvell/cesa.c 		engine->regs = cesa->regs + CESA_ENGINE_OFF(i);
engine            536 drivers/crypto/marvell/cesa.c 			mv_cesa_conf_mbus_windows(engine, dram);
engine            538 drivers/crypto/marvell/cesa.c 		writel(0, engine->regs + CESA_SA_INT_STATUS);
engine            540 drivers/crypto/marvell/cesa.c 		       engine->regs + CESA_SA_CFG);
engine            541 drivers/crypto/marvell/cesa.c 		writel(engine->sram_dma & CESA_SA_SRAM_MSK,
engine            542 drivers/crypto/marvell/cesa.c 		       engine->regs + CESA_SA_DESC_P0);
engine            547 drivers/crypto/marvell/cesa.c 						engine);
engine            551 drivers/crypto/marvell/cesa.c 		crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN);
engine            552 drivers/crypto/marvell/cesa.c 		atomic_set(&engine->load, 0);
engine            553 drivers/crypto/marvell/cesa.c 		INIT_LIST_HEAD(&engine->complete_queue);
engine            527 drivers/crypto/marvell/cesa.h 	struct mv_cesa_engine *engine;
engine            622 drivers/crypto/marvell/cesa.h mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
engine            625 drivers/crypto/marvell/cesa.h 	list_add_tail(&req->list, &engine->complete_queue);
engine            629 drivers/crypto/marvell/cesa.h mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
engine            633 drivers/crypto/marvell/cesa.h 	req = list_first_entry_or_null(&engine->complete_queue,
engine            666 drivers/crypto/marvell/cesa.h static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
engine            669 drivers/crypto/marvell/cesa.h 	u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
engine            700 drivers/crypto/marvell/cesa.h static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
engine            703 drivers/crypto/marvell/cesa.h 	if (int_mask == engine->int_mask)
engine            706 drivers/crypto/marvell/cesa.h 	writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
engine            707 drivers/crypto/marvell/cesa.h 	engine->int_mask = int_mask;
engine            710 drivers/crypto/marvell/cesa.h static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
engine            712 drivers/crypto/marvell/cesa.h 	return engine->int_mask;
engine            725 drivers/crypto/marvell/cesa.h mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
engine            735 drivers/crypto/marvell/cesa.h 		struct mv_cesa_engine *engine = cesa_dev->engines + i;
engine            736 drivers/crypto/marvell/cesa.h 		u32 load = atomic_read(&engine->load);
engine            739 drivers/crypto/marvell/cesa.h 			selected = engine;
engine            831 drivers/crypto/marvell/cesa.h 			 struct mv_cesa_engine *engine);
engine            833 drivers/crypto/marvell/cesa.h void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
engine            835 drivers/crypto/marvell/cesa.h int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
engine             85 drivers/crypto/marvell/cipher.c 	struct mv_cesa_engine *engine = creq->base.engine;
engine             89 drivers/crypto/marvell/cipher.c 	mv_cesa_adjust_op(engine, &sreq->op);
engine             90 drivers/crypto/marvell/cipher.c 	memcpy_toio(engine->sram, &sreq->op, sizeof(sreq->op));
engine             93 drivers/crypto/marvell/cipher.c 				 engine->sram + CESA_SA_DATA_SRAM_OFFSET,
engine            101 drivers/crypto/marvell/cipher.c 		memcpy_toio(engine->sram, &sreq->op, sizeof(sreq->op));
engine            104 drivers/crypto/marvell/cipher.c 		memcpy_toio(engine->sram, &sreq->op, sizeof(sreq->op.desc));
engine            107 drivers/crypto/marvell/cipher.c 	mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
engine            108 drivers/crypto/marvell/cipher.c 	writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
engine            109 drivers/crypto/marvell/cipher.c 	BUG_ON(readl(engine->regs + CESA_SA_CMD) &
engine            111 drivers/crypto/marvell/cipher.c 	writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
engine            119 drivers/crypto/marvell/cipher.c 	struct mv_cesa_engine *engine = creq->base.engine;
engine            123 drivers/crypto/marvell/cipher.c 				   engine->sram + CESA_SA_DATA_SRAM_OFFSET,
engine            163 drivers/crypto/marvell/cipher.c 	mv_cesa_dma_prepare(basereq, basereq->engine);
engine            177 drivers/crypto/marvell/cipher.c 					    struct mv_cesa_engine *engine)
engine            181 drivers/crypto/marvell/cipher.c 	creq->base.engine = engine;
engine            202 drivers/crypto/marvell/cipher.c 	struct mv_cesa_engine *engine = creq->base.engine;
engine            205 drivers/crypto/marvell/cipher.c 	atomic_sub(skreq->cryptlen, &engine->load);
engine            216 drivers/crypto/marvell/cipher.c 			      engine->sram + CESA_SA_CRYPT_IV_SRAM_OFFSET,
engine            448 drivers/crypto/marvell/cipher.c 	struct mv_cesa_engine *engine;
engine            454 drivers/crypto/marvell/cipher.c 	engine = mv_cesa_select_engine(req->cryptlen);
engine            455 drivers/crypto/marvell/cipher.c 	mv_cesa_skcipher_prepare(&req->base, engine);
engine            157 drivers/crypto/marvell/hash.c 	struct mv_cesa_engine *engine = creq->base.engine;
engine            165 drivers/crypto/marvell/hash.c 	mv_cesa_adjust_op(engine, &creq->op_tmpl);
engine            166 drivers/crypto/marvell/hash.c 	memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
engine            171 drivers/crypto/marvell/hash.c 			writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
engine            175 drivers/crypto/marvell/hash.c 		memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
engine            188 drivers/crypto/marvell/hash.c 						   engine->sram +
engine            218 drivers/crypto/marvell/hash.c 					      engine->sram +
engine            223 drivers/crypto/marvell/hash.c 						engine->sram + len +
engine            238 drivers/crypto/marvell/hash.c 	memcpy_toio(engine->sram, op, sizeof(*op));
engine            246 drivers/crypto/marvell/hash.c 	mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
engine            247 drivers/crypto/marvell/hash.c 	writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
engine            248 drivers/crypto/marvell/hash.c 	BUG_ON(readl(engine->regs + CESA_SA_CMD) &
engine            250 drivers/crypto/marvell/hash.c 	writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
engine            269 drivers/crypto/marvell/hash.c 	mv_cesa_dma_prepare(basereq, basereq->engine);
engine            287 drivers/crypto/marvell/hash.c 		struct mv_cesa_engine *engine = base->engine;
engine            292 drivers/crypto/marvell/hash.c 			writel_relaxed(creq->state[i], engine->regs +
engine            325 drivers/crypto/marvell/hash.c 	struct mv_cesa_engine *engine = creq->base.engine;
engine            346 drivers/crypto/marvell/hash.c 			creq->state[i] = readl_relaxed(engine->regs +
engine            367 drivers/crypto/marvell/hash.c 	atomic_sub(ahashreq->nbytes, &engine->load);
engine            371 drivers/crypto/marvell/hash.c 				  struct mv_cesa_engine *engine)
engine            376 drivers/crypto/marvell/hash.c 	creq->base.engine = engine;
engine            751 drivers/crypto/marvell/hash.c 	struct mv_cesa_engine *engine;
engine            762 drivers/crypto/marvell/hash.c 	engine = mv_cesa_select_engine(req->nbytes);
engine            763 drivers/crypto/marvell/hash.c 	mv_cesa_ahash_prepare(&req->base, engine);
engine             39 drivers/crypto/marvell/tdma.c 	struct mv_cesa_engine *engine = dreq->engine;
engine             41 drivers/crypto/marvell/tdma.c 	writel_relaxed(0, engine->regs + CESA_SA_CFG);
engine             43 drivers/crypto/marvell/tdma.c 	mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
engine             46 drivers/crypto/marvell/tdma.c 		       engine->regs + CESA_TDMA_CONTROL);
engine             50 drivers/crypto/marvell/tdma.c 		       engine->regs + CESA_SA_CFG);
engine             52 drivers/crypto/marvell/tdma.c 		       engine->regs + CESA_TDMA_NEXT_ADDR);
engine             53 drivers/crypto/marvell/tdma.c 	BUG_ON(readl(engine->regs + CESA_SA_CMD) &
engine             55 drivers/crypto/marvell/tdma.c 	writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
engine             80 drivers/crypto/marvell/tdma.c 			 struct mv_cesa_engine *engine)
engine             86 drivers/crypto/marvell/tdma.c 			tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma);
engine             89 drivers/crypto/marvell/tdma.c 			tdma->src = cpu_to_le32(tdma->src + engine->sram_dma);
engine             92 drivers/crypto/marvell/tdma.c 			mv_cesa_adjust_op(engine, tdma->op);
engine             96 drivers/crypto/marvell/tdma.c void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
engine             99 drivers/crypto/marvell/tdma.c 	if (engine->chain.first == NULL && engine->chain.last == NULL) {
engine            100 drivers/crypto/marvell/tdma.c 		engine->chain.first = dreq->chain.first;
engine            101 drivers/crypto/marvell/tdma.c 		engine->chain.last  = dreq->chain.last;
engine            105 drivers/crypto/marvell/tdma.c 		last = engine->chain.last;
engine            107 drivers/crypto/marvell/tdma.c 		engine->chain.last = dreq->chain.last;
engine            121 drivers/crypto/marvell/tdma.c int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status)
engine            128 drivers/crypto/marvell/tdma.c 	tdma_cur = readl(engine->regs + CESA_TDMA_CUR);
engine            130 drivers/crypto/marvell/tdma.c 	for (tdma = engine->chain.first; tdma; tdma = next) {
engine            131 drivers/crypto/marvell/tdma.c 		spin_lock_bh(&engine->lock);
engine            133 drivers/crypto/marvell/tdma.c 		spin_unlock_bh(&engine->lock);
engine            140 drivers/crypto/marvell/tdma.c 			spin_lock_bh(&engine->lock);
engine            146 drivers/crypto/marvell/tdma.c 				req = engine->req;
engine            148 drivers/crypto/marvell/tdma.c 				req = mv_cesa_dequeue_req_locked(engine,
engine            152 drivers/crypto/marvell/tdma.c 			engine->chain.first = tdma->next;
engine            156 drivers/crypto/marvell/tdma.c 			if (engine->chain.first == NULL)
engine            157 drivers/crypto/marvell/tdma.c 				engine->chain.last  = NULL;
engine            158 drivers/crypto/marvell/tdma.c 			spin_unlock_bh(&engine->lock);
engine            167 drivers/crypto/marvell/tdma.c 				mv_cesa_engine_enqueue_complete_request(engine,
engine            181 drivers/crypto/marvell/tdma.c 		spin_lock_bh(&engine->lock);
engine            182 drivers/crypto/marvell/tdma.c 		engine->req = req;
engine            183 drivers/crypto/marvell/tdma.c 		spin_unlock_bh(&engine->lock);
engine            389 drivers/crypto/omap-aes.c 	crypto_finalize_ablkcipher_request(dd->engine, req, err);
engine            409 drivers/crypto/omap-aes.c 		return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
engine            414 drivers/crypto/omap-aes.c static int omap_aes_prepare_req(struct crypto_engine *engine,
engine            469 drivers/crypto/omap-aes.c static int omap_aes_crypt_req(struct crypto_engine *engine,
engine            604 drivers/crypto/omap-aes.c static int omap_aes_prepare_req(struct crypto_engine *engine,
engine            606 drivers/crypto/omap-aes.c static int omap_aes_crypt_req(struct crypto_engine *engine,
engine           1071 drivers/crypto/omap-aes.c 	return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
engine           1098 drivers/crypto/omap-aes.c 		dd->engine->queue.max_qlen = value;
engine           1203 drivers/crypto/omap-aes.c 	dd->engine = crypto_engine_alloc_init(dev, 1);
engine           1204 drivers/crypto/omap-aes.c 	if (!dd->engine) {
engine           1209 drivers/crypto/omap-aes.c 	err = crypto_engine_start(dd->engine);
engine           1264 drivers/crypto/omap-aes.c 	if (dd->engine)
engine           1265 drivers/crypto/omap-aes.c 		crypto_engine_exit(dd->engine);
engine           1301 drivers/crypto/omap-aes.c 	crypto_engine_exit(dd->engine);
engine            167 drivers/crypto/omap-aes.h 	struct crypto_engine		*engine;
engine            143 drivers/crypto/omap-des.c 	struct crypto_engine		*engine;
engine            498 drivers/crypto/omap-des.c 	crypto_finalize_ablkcipher_request(dd->engine, req, err);
engine            520 drivers/crypto/omap-des.c 		return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
engine            525 drivers/crypto/omap-des.c static int omap_des_prepare_req(struct crypto_engine *engine,
engine            582 drivers/crypto/omap-des.c static int omap_des_crypt_req(struct crypto_engine *engine,
engine            705 drivers/crypto/omap-des.c static int omap_des_prepare_req(struct crypto_engine *engine,
engine            707 drivers/crypto/omap-des.c static int omap_des_crypt_req(struct crypto_engine *engine,
engine           1060 drivers/crypto/omap-des.c 	dd->engine = crypto_engine_alloc_init(dev, 1);
engine           1061 drivers/crypto/omap-des.c 	if (!dd->engine) {
engine           1066 drivers/crypto/omap-des.c 	err = crypto_engine_start(dd->engine);
engine           1093 drivers/crypto/omap-des.c 	if (dd->engine)
engine           1094 drivers/crypto/omap-des.c 		crypto_engine_exit(dd->engine);
engine             81 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine		*engine;
engine             95 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine		*engine;
engine            138 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine		*engine;
engine            146 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine		*engine;
engine            186 drivers/crypto/picoxcell_crypto.c static inline int spacc_fifo_cmd_full(struct spacc_engine *engine)
engine            188 drivers/crypto/picoxcell_crypto.c 	u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET);
engine            204 drivers/crypto/picoxcell_crypto.c 	return is_cipher_ctx ? ctx->engine->cipher_ctx_base +
engine            205 drivers/crypto/picoxcell_crypto.c 			(indx * ctx->engine->cipher_pg_sz) :
engine            206 drivers/crypto/picoxcell_crypto.c 		ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz);
engine            240 drivers/crypto/picoxcell_crypto.c 	unsigned indx = ctx->engine->next_ctx++;
engine            246 drivers/crypto/picoxcell_crypto.c 	ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1;
engine            251 drivers/crypto/picoxcell_crypto.c 	       ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
engine            256 drivers/crypto/picoxcell_crypto.c 		       ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
engine            273 drivers/crypto/picoxcell_crypto.c static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine,
engine            287 drivers/crypto/picoxcell_crypto.c 		dev_err(engine->dev, "Invalid numbers of SG.\n");
engine            290 drivers/crypto/picoxcell_crypto.c 	mapped_ents = dma_map_sg(engine->dev, payload, nents, dir);
engine            295 drivers/crypto/picoxcell_crypto.c 	ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys);
engine            306 drivers/crypto/picoxcell_crypto.c 	dma_unmap_sg(engine->dev, payload, nents, dir);
engine            314 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = req->engine;
engine            327 drivers/crypto/picoxcell_crypto.c 		dev_err(engine->dev, "Invalid numbers of src SG.\n");
engine            337 drivers/crypto/picoxcell_crypto.c 			dev_err(engine->dev, "Invalid numbers of dst SG.\n");
engine            344 drivers/crypto/picoxcell_crypto.c 	src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr);
engine            348 drivers/crypto/picoxcell_crypto.c 	dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr);
engine            356 drivers/crypto/picoxcell_crypto.c 		src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
engine            361 drivers/crypto/picoxcell_crypto.c 		dst_ents = dma_map_sg(engine->dev, areq->dst, dst_nents,
engine            365 drivers/crypto/picoxcell_crypto.c 			dma_unmap_sg(engine->dev, areq->src, src_nents,
engine            370 drivers/crypto/picoxcell_crypto.c 		src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
engine            403 drivers/crypto/picoxcell_crypto.c 	dma_pool_free(engine->req_pool, dst_ddt, req->dst_addr);
engine            405 drivers/crypto/picoxcell_crypto.c 	dma_pool_free(engine->req_pool, src_ddt, req->src_addr);
engine            418 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = aead_ctx->generic.engine;
engine            423 drivers/crypto/picoxcell_crypto.c 		dev_err(engine->dev, "Invalid numbers of src SG.\n");
engine            428 drivers/crypto/picoxcell_crypto.c 		dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE);
engine            431 drivers/crypto/picoxcell_crypto.c 			dev_err(engine->dev, "Invalid numbers of dst SG.\n");
engine            434 drivers/crypto/picoxcell_crypto.c 		dma_unmap_sg(engine->dev, areq->dst, nents, DMA_FROM_DEVICE);
engine            436 drivers/crypto/picoxcell_crypto.c 		dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL);
engine            438 drivers/crypto/picoxcell_crypto.c 	dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr);
engine            439 drivers/crypto/picoxcell_crypto.c 	dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr);
engine            449 drivers/crypto/picoxcell_crypto.c 		dev_err(req->engine->dev, "Invalid numbers of SG.\n");
engine            453 drivers/crypto/picoxcell_crypto.c 	dma_unmap_sg(req->engine->dev, payload, nents, dir);
engine            454 drivers/crypto/picoxcell_crypto.c 	dma_pool_free(req->engine->req_pool, ddt, ddt_addr);
engine            564 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = ctx->generic.engine;
engine            573 drivers/crypto/picoxcell_crypto.c 	writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
engine            574 drivers/crypto/picoxcell_crypto.c 	writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
engine            575 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
engine            587 drivers/crypto/picoxcell_crypto.c 	writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET);
engine            588 drivers/crypto/picoxcell_crypto.c 	writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET);
engine            589 drivers/crypto/picoxcell_crypto.c 	writel(authsize, engine->regs + SPA_ICV_LEN_REG_OFFSET);
engine            590 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
engine            591 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
engine            600 drivers/crypto/picoxcell_crypto.c 	mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
engine            602 drivers/crypto/picoxcell_crypto.c 	writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
engine            609 drivers/crypto/picoxcell_crypto.c static void spacc_push(struct spacc_engine *engine)
engine            613 drivers/crypto/picoxcell_crypto.c 	while (!list_empty(&engine->pending) &&
engine            614 drivers/crypto/picoxcell_crypto.c 	       engine->in_flight + 1 <= engine->fifo_sz) {
engine            616 drivers/crypto/picoxcell_crypto.c 		++engine->in_flight;
engine            617 drivers/crypto/picoxcell_crypto.c 		req = list_first_entry(&engine->pending, struct spacc_req,
engine            619 drivers/crypto/picoxcell_crypto.c 		list_move_tail(&req->list, &engine->in_progress);
engine            634 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = to_spacc_aead(alg)->engine;
engine            642 drivers/crypto/picoxcell_crypto.c 	dev_req->engine		= engine;
engine            653 drivers/crypto/picoxcell_crypto.c 	spin_lock_irqsave(&engine->hw_lock, flags);
engine            654 drivers/crypto/picoxcell_crypto.c 	if (unlikely(spacc_fifo_cmd_full(engine)) ||
engine            655 drivers/crypto/picoxcell_crypto.c 	    engine->in_flight + 1 > engine->fifo_sz) {
engine            658 drivers/crypto/picoxcell_crypto.c 			spin_unlock_irqrestore(&engine->hw_lock, flags);
engine            661 drivers/crypto/picoxcell_crypto.c 		list_add_tail(&dev_req->list, &engine->pending);
engine            663 drivers/crypto/picoxcell_crypto.c 		list_add_tail(&dev_req->list, &engine->pending);
engine            664 drivers/crypto/picoxcell_crypto.c 		spacc_push(engine);
engine            666 drivers/crypto/picoxcell_crypto.c 	spin_unlock_irqrestore(&engine->hw_lock, flags);
engine            701 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = spacc_alg->engine;
engine            704 drivers/crypto/picoxcell_crypto.c 	ctx->generic.engine = engine;
engine            883 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = ctx->generic.engine;
engine            890 drivers/crypto/picoxcell_crypto.c 	writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
engine            891 drivers/crypto/picoxcell_crypto.c 	writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
engine            892 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
engine            894 drivers/crypto/picoxcell_crypto.c 	writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET);
engine            895 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
engine            896 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
engine            897 drivers/crypto/picoxcell_crypto.c 	writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET);
engine            903 drivers/crypto/picoxcell_crypto.c 	mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
engine            905 drivers/crypto/picoxcell_crypto.c 	writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
engine            939 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = to_spacc_alg(alg)->engine;
engine            946 drivers/crypto/picoxcell_crypto.c 	dev_req->engine		= engine;
engine            958 drivers/crypto/picoxcell_crypto.c 		dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src,
engine            963 drivers/crypto/picoxcell_crypto.c 		dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
engine            968 drivers/crypto/picoxcell_crypto.c 		dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
engine            978 drivers/crypto/picoxcell_crypto.c 	spin_lock_irqsave(&engine->hw_lock, flags);
engine            984 drivers/crypto/picoxcell_crypto.c 	if (unlikely(spacc_fifo_cmd_full(engine)) ||
engine            985 drivers/crypto/picoxcell_crypto.c 	    engine->in_flight + 1 > engine->fifo_sz) {
engine            988 drivers/crypto/picoxcell_crypto.c 			spin_unlock_irqrestore(&engine->hw_lock, flags);
engine            991 drivers/crypto/picoxcell_crypto.c 		list_add_tail(&dev_req->list, &engine->pending);
engine            993 drivers/crypto/picoxcell_crypto.c 		list_add_tail(&dev_req->list, &engine->pending);
engine            994 drivers/crypto/picoxcell_crypto.c 		spacc_push(engine);
engine            996 drivers/crypto/picoxcell_crypto.c 	spin_unlock_irqrestore(&engine->hw_lock, flags);
engine           1017 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = spacc_alg->engine;
engine           1020 drivers/crypto/picoxcell_crypto.c 	ctx->generic.engine = engine;
engine           1025 drivers/crypto/picoxcell_crypto.c 			dev_warn(engine->dev, "failed to allocate fallback for %s\n",
engine           1063 drivers/crypto/picoxcell_crypto.c static inline int spacc_fifo_stat_empty(struct spacc_engine *engine)
engine           1065 drivers/crypto/picoxcell_crypto.c 	return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) &
engine           1069 drivers/crypto/picoxcell_crypto.c static void spacc_process_done(struct spacc_engine *engine)
engine           1074 drivers/crypto/picoxcell_crypto.c 	spin_lock_irqsave(&engine->hw_lock, flags);
engine           1076 drivers/crypto/picoxcell_crypto.c 	while (!spacc_fifo_stat_empty(engine)) {
engine           1077 drivers/crypto/picoxcell_crypto.c 		req = list_first_entry(&engine->in_progress, struct spacc_req,
engine           1079 drivers/crypto/picoxcell_crypto.c 		list_move_tail(&req->list, &engine->completed);
engine           1080 drivers/crypto/picoxcell_crypto.c 		--engine->in_flight;
engine           1083 drivers/crypto/picoxcell_crypto.c 		writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET);
engine           1084 drivers/crypto/picoxcell_crypto.c 		req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) &
engine           1098 drivers/crypto/picoxcell_crypto.c 				dev_warn(engine->dev,
engine           1104 drivers/crypto/picoxcell_crypto.c 				dev_warn(engine->dev,
engine           1112 drivers/crypto/picoxcell_crypto.c 	tasklet_schedule(&engine->complete);
engine           1114 drivers/crypto/picoxcell_crypto.c 	spin_unlock_irqrestore(&engine->hw_lock, flags);
engine           1119 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = (struct spacc_engine *)dev;
engine           1120 drivers/crypto/picoxcell_crypto.c 	u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET);
engine           1122 drivers/crypto/picoxcell_crypto.c 	writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET);
engine           1123 drivers/crypto/picoxcell_crypto.c 	spacc_process_done(engine);
engine           1130 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = from_timer(engine, t, packet_timeout);
engine           1132 drivers/crypto/picoxcell_crypto.c 	spacc_process_done(engine);
engine           1147 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = (struct spacc_engine *)data;
engine           1152 drivers/crypto/picoxcell_crypto.c 	spin_lock_irqsave(&engine->hw_lock, flags);
engine           1154 drivers/crypto/picoxcell_crypto.c 	list_splice_init(&engine->completed, &completed);
engine           1155 drivers/crypto/picoxcell_crypto.c 	spacc_push(engine);
engine           1156 drivers/crypto/picoxcell_crypto.c 	if (engine->in_flight)
engine           1157 drivers/crypto/picoxcell_crypto.c 		mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
engine           1159 drivers/crypto/picoxcell_crypto.c 	spin_unlock_irqrestore(&engine->hw_lock, flags);
engine           1170 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = dev_get_drvdata(dev);
engine           1177 drivers/crypto/picoxcell_crypto.c 	clk_disable(engine->clk);
engine           1184 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = dev_get_drvdata(dev);
engine           1186 drivers/crypto/picoxcell_crypto.c 	return clk_enable(engine->clk);
engine           1204 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = spacc_dev_to_engine(dev);
engine           1206 drivers/crypto/picoxcell_crypto.c 	return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh);
engine           1213 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = spacc_dev_to_engine(dev);
engine           1219 drivers/crypto/picoxcell_crypto.c 	thresh = clamp(thresh, 1UL, engine->fifo_sz - 1);
engine           1221 drivers/crypto/picoxcell_crypto.c 	engine->stat_irq_thresh = thresh;
engine           1222 drivers/crypto/picoxcell_crypto.c 	writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
engine           1223 drivers/crypto/picoxcell_crypto.c 	       engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
engine           1626 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine),
engine           1628 drivers/crypto/picoxcell_crypto.c 	if (!engine)
engine           1632 drivers/crypto/picoxcell_crypto.c 		engine->max_ctxs	= SPACC_CRYPTO_IPSEC_MAX_CTXS;
engine           1633 drivers/crypto/picoxcell_crypto.c 		engine->cipher_pg_sz	= SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ;
engine           1634 drivers/crypto/picoxcell_crypto.c 		engine->hash_pg_sz	= SPACC_CRYPTO_IPSEC_HASH_PG_SZ;
engine           1635 drivers/crypto/picoxcell_crypto.c 		engine->fifo_sz		= SPACC_CRYPTO_IPSEC_FIFO_SZ;
engine           1636 drivers/crypto/picoxcell_crypto.c 		engine->algs		= ipsec_engine_algs;
engine           1637 drivers/crypto/picoxcell_crypto.c 		engine->num_algs	= ARRAY_SIZE(ipsec_engine_algs);
engine           1638 drivers/crypto/picoxcell_crypto.c 		engine->aeads		= ipsec_engine_aeads;
engine           1639 drivers/crypto/picoxcell_crypto.c 		engine->num_aeads	= ARRAY_SIZE(ipsec_engine_aeads);
engine           1641 drivers/crypto/picoxcell_crypto.c 		engine->max_ctxs	= SPACC_CRYPTO_L2_MAX_CTXS;
engine           1642 drivers/crypto/picoxcell_crypto.c 		engine->cipher_pg_sz	= SPACC_CRYPTO_L2_CIPHER_PG_SZ;
engine           1643 drivers/crypto/picoxcell_crypto.c 		engine->hash_pg_sz	= SPACC_CRYPTO_L2_HASH_PG_SZ;
engine           1644 drivers/crypto/picoxcell_crypto.c 		engine->fifo_sz		= SPACC_CRYPTO_L2_FIFO_SZ;
engine           1645 drivers/crypto/picoxcell_crypto.c 		engine->algs		= l2_engine_algs;
engine           1646 drivers/crypto/picoxcell_crypto.c 		engine->num_algs	= ARRAY_SIZE(l2_engine_algs);
engine           1651 drivers/crypto/picoxcell_crypto.c 	engine->name = dev_name(&pdev->dev);
engine           1653 drivers/crypto/picoxcell_crypto.c 	engine->regs = devm_platform_ioremap_resource(pdev, 0);
engine           1654 drivers/crypto/picoxcell_crypto.c 	if (IS_ERR(engine->regs))
engine           1655 drivers/crypto/picoxcell_crypto.c 		return PTR_ERR(engine->regs);
engine           1663 drivers/crypto/picoxcell_crypto.c 	tasklet_init(&engine->complete, spacc_spacc_complete,
engine           1664 drivers/crypto/picoxcell_crypto.c 		     (unsigned long)engine);
engine           1667 drivers/crypto/picoxcell_crypto.c 			      &engine->complete);
engine           1672 drivers/crypto/picoxcell_crypto.c 			     engine->name, engine)) {
engine           1673 drivers/crypto/picoxcell_crypto.c 		dev_err(engine->dev, "failed to request IRQ\n");
engine           1677 drivers/crypto/picoxcell_crypto.c 	engine->dev		= &pdev->dev;
engine           1678 drivers/crypto/picoxcell_crypto.c 	engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET;
engine           1679 drivers/crypto/picoxcell_crypto.c 	engine->hash_key_base	= engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET;
engine           1681 drivers/crypto/picoxcell_crypto.c 	engine->req_pool = dmam_pool_create(engine->name, engine->dev,
engine           1683 drivers/crypto/picoxcell_crypto.c 	if (!engine->req_pool)
engine           1686 drivers/crypto/picoxcell_crypto.c 	spin_lock_init(&engine->hw_lock);
engine           1688 drivers/crypto/picoxcell_crypto.c 	engine->clk = clk_get(&pdev->dev, "ref");
engine           1689 drivers/crypto/picoxcell_crypto.c 	if (IS_ERR(engine->clk)) {
engine           1691 drivers/crypto/picoxcell_crypto.c 		return PTR_ERR(engine->clk);
engine           1694 drivers/crypto/picoxcell_crypto.c 	if (clk_prepare_enable(engine->clk)) {
engine           1710 drivers/crypto/picoxcell_crypto.c 	engine->stat_irq_thresh = (engine->fifo_sz / 2);
engine           1717 drivers/crypto/picoxcell_crypto.c 	writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
engine           1718 drivers/crypto/picoxcell_crypto.c 	       engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
engine           1720 drivers/crypto/picoxcell_crypto.c 	       engine->regs + SPA_IRQ_EN_REG_OFFSET);
engine           1722 drivers/crypto/picoxcell_crypto.c 	timer_setup(&engine->packet_timeout, spacc_packet_timeout, 0);
engine           1724 drivers/crypto/picoxcell_crypto.c 	INIT_LIST_HEAD(&engine->pending);
engine           1725 drivers/crypto/picoxcell_crypto.c 	INIT_LIST_HEAD(&engine->completed);
engine           1726 drivers/crypto/picoxcell_crypto.c 	INIT_LIST_HEAD(&engine->in_progress);
engine           1727 drivers/crypto/picoxcell_crypto.c 	engine->in_flight = 0;
engine           1729 drivers/crypto/picoxcell_crypto.c 	platform_set_drvdata(pdev, engine);
engine           1732 drivers/crypto/picoxcell_crypto.c 	INIT_LIST_HEAD(&engine->registered_algs);
engine           1733 drivers/crypto/picoxcell_crypto.c 	for (i = 0; i < engine->num_algs; ++i) {
engine           1734 drivers/crypto/picoxcell_crypto.c 		engine->algs[i].engine = engine;
engine           1735 drivers/crypto/picoxcell_crypto.c 		err = crypto_register_alg(&engine->algs[i].alg);
engine           1737 drivers/crypto/picoxcell_crypto.c 			list_add_tail(&engine->algs[i].entry,
engine           1738 drivers/crypto/picoxcell_crypto.c 				      &engine->registered_algs);
engine           1742 drivers/crypto/picoxcell_crypto.c 			dev_err(engine->dev, "failed to register alg \"%s\"\n",
engine           1743 drivers/crypto/picoxcell_crypto.c 				engine->algs[i].alg.cra_name);
engine           1745 drivers/crypto/picoxcell_crypto.c 			dev_dbg(engine->dev, "registered alg \"%s\"\n",
engine           1746 drivers/crypto/picoxcell_crypto.c 				engine->algs[i].alg.cra_name);
engine           1749 drivers/crypto/picoxcell_crypto.c 	INIT_LIST_HEAD(&engine->registered_aeads);
engine           1750 drivers/crypto/picoxcell_crypto.c 	for (i = 0; i < engine->num_aeads; ++i) {
engine           1751 drivers/crypto/picoxcell_crypto.c 		engine->aeads[i].engine = engine;
engine           1752 drivers/crypto/picoxcell_crypto.c 		err = crypto_register_aead(&engine->aeads[i].alg);
engine           1754 drivers/crypto/picoxcell_crypto.c 			list_add_tail(&engine->aeads[i].entry,
engine           1755 drivers/crypto/picoxcell_crypto.c 				      &engine->registered_aeads);
engine           1759 drivers/crypto/picoxcell_crypto.c 			dev_err(engine->dev, "failed to register alg \"%s\"\n",
engine           1760 drivers/crypto/picoxcell_crypto.c 				engine->aeads[i].alg.base.cra_name);
engine           1762 drivers/crypto/picoxcell_crypto.c 			dev_dbg(engine->dev, "registered alg \"%s\"\n",
engine           1763 drivers/crypto/picoxcell_crypto.c 				engine->aeads[i].alg.base.cra_name);
engine           1769 drivers/crypto/picoxcell_crypto.c 	del_timer_sync(&engine->packet_timeout);
engine           1772 drivers/crypto/picoxcell_crypto.c 	clk_disable_unprepare(engine->clk);
engine           1774 drivers/crypto/picoxcell_crypto.c 	clk_put(engine->clk);
engine           1783 drivers/crypto/picoxcell_crypto.c 	struct spacc_engine *engine = platform_get_drvdata(pdev);
engine           1785 drivers/crypto/picoxcell_crypto.c 	del_timer_sync(&engine->packet_timeout);
engine           1788 drivers/crypto/picoxcell_crypto.c 	list_for_each_entry_safe(aead, an, &engine->registered_aeads, entry) {
engine           1793 drivers/crypto/picoxcell_crypto.c 	list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) {
engine           1798 drivers/crypto/picoxcell_crypto.c 	clk_disable_unprepare(engine->clk);
engine           1799 drivers/crypto/picoxcell_crypto.c 	clk_put(engine->clk);
engine            361 drivers/crypto/s5p-sss.c 	u32			engine;
engine            941 drivers/crypto/s5p-sss.c 	configflags = ctx->engine | SSS_HASH_INIT_BIT;
engine           1643 drivers/crypto/s5p-sss.c 		ctx->engine = SSS_HASH_ENGINE_MD5;
engine           1647 drivers/crypto/s5p-sss.c 		ctx->engine = SSS_HASH_ENGINE_SHA1;
engine           1651 drivers/crypto/s5p-sss.c 		ctx->engine = SSS_HASH_ENGINE_SHA256;
engine            138 drivers/crypto/stm32/stm32-cryp.c 	struct crypto_engine    *engine;
engine            668 drivers/crypto/stm32/stm32-cryp.c 		crypto_finalize_aead_request(cryp->engine, cryp->areq, err);
engine            670 drivers/crypto/stm32/stm32-cryp.c 		crypto_finalize_ablkcipher_request(cryp->engine, cryp->req,
engine            684 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_cipher_one_req(struct crypto_engine *engine, void *areq);
engine            685 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
engine            700 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq);
engine            701 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_prepare_aead_req(struct crypto_engine *engine,
engine            729 drivers/crypto/stm32/stm32-cryp.c 	return crypto_transfer_ablkcipher_request_to_engine(cryp->engine, req);
engine            743 drivers/crypto/stm32/stm32-cryp.c 	return crypto_transfer_aead_request_to_engine(cryp->engine, req);
engine           1016 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
engine           1026 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_cipher_one_req(struct crypto_engine *engine, void *areq)
engine           1041 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_prepare_aead_req(struct crypto_engine *engine, void *areq)
engine           1049 drivers/crypto/stm32/stm32-cryp.c static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq)
engine           2000 drivers/crypto/stm32/stm32-cryp.c 	cryp->engine = crypto_engine_alloc_init(dev, 1);
engine           2001 drivers/crypto/stm32/stm32-cryp.c 	if (!cryp->engine) {
engine           2007 drivers/crypto/stm32/stm32-cryp.c 	ret = crypto_engine_start(cryp->engine);
engine           2033 drivers/crypto/stm32/stm32-cryp.c 	crypto_engine_exit(cryp->engine);
engine           2064 drivers/crypto/stm32/stm32-cryp.c 	crypto_engine_exit(cryp->engine);
engine            171 drivers/crypto/stm32/stm32-hash.c 	struct crypto_engine	*engine;
engine            807 drivers/crypto/stm32/stm32-hash.c 	crypto_finalize_hash_request(hdev->engine, req, err);
engine            826 drivers/crypto/stm32/stm32-hash.c static int stm32_hash_one_request(struct crypto_engine *engine, void *areq);
engine            827 drivers/crypto/stm32/stm32-hash.c static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq);
engine            832 drivers/crypto/stm32/stm32-hash.c 	return crypto_transfer_hash_request_to_engine(hdev->engine, req);
engine            835 drivers/crypto/stm32/stm32-hash.c static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq)
engine            856 drivers/crypto/stm32/stm32-hash.c static int stm32_hash_one_request(struct crypto_engine *engine, void *areq)
engine           1504 drivers/crypto/stm32/stm32-hash.c 	hdev->engine = crypto_engine_alloc_init(dev, 1);
engine           1505 drivers/crypto/stm32/stm32-hash.c 	if (!hdev->engine) {
engine           1510 drivers/crypto/stm32/stm32-hash.c 	ret = crypto_engine_start(hdev->engine);
engine           1530 drivers/crypto/stm32/stm32-hash.c 	crypto_engine_exit(hdev->engine);
engine           1562 drivers/crypto/stm32/stm32-hash.c 	crypto_engine_exit(hdev->engine);
engine            507 drivers/crypto/virtio/virtio_crypto_algs.c 	return crypto_transfer_ablkcipher_request_to_engine(data_vq->engine, req);
engine            532 drivers/crypto/virtio/virtio_crypto_algs.c 	return crypto_transfer_ablkcipher_request_to_engine(data_vq->engine, req);
engine            562 drivers/crypto/virtio/virtio_crypto_algs.c 	struct crypto_engine *engine, void *vreq)
engine            592 drivers/crypto/virtio/virtio_crypto_algs.c 	crypto_finalize_ablkcipher_request(vc_sym_req->base.dataq->engine,
engine             29 drivers/crypto/virtio/virtio_crypto_common.h 	struct crypto_engine *engine;
engine            116 drivers/crypto/virtio/virtio_crypto_common.h 	struct crypto_engine *engine, void *vreq);
engine             97 drivers/crypto/virtio/virtio_crypto_core.c 		vi->data_vq[i].engine = crypto_engine_alloc_init(dev, 1);
engine             98 drivers/crypto/virtio/virtio_crypto_core.c 		if (!vi->data_vq[i].engine) {
engine            250 drivers/crypto/virtio/virtio_crypto_core.c 		if (vcrypto->data_vq[i].engine) {
engine            251 drivers/crypto/virtio/virtio_crypto_core.c 			ret = crypto_engine_start(vcrypto->data_vq[i].engine);
engine            261 drivers/crypto/virtio/virtio_crypto_core.c 		if (vcrypto->data_vq[i].engine)
engine            262 drivers/crypto/virtio/virtio_crypto_core.c 			crypto_engine_exit(vcrypto->data_vq[i].engine);
engine            272 drivers/crypto/virtio/virtio_crypto_core.c 		if (vcrypto->data_vq[i].engine)
engine            273 drivers/crypto/virtio/virtio_crypto_core.c 			crypto_engine_exit(vcrypto->data_vq[i].engine);
engine            199 drivers/dma/sh/rcar-dmac.c 	struct dma_device engine;
engine            211 drivers/dma/sh/rcar-dmac.c #define to_rcar_dmac(d)		container_of(d, struct rcar_dmac, engine)
engine           1764 drivers/dma/sh/rcar-dmac.c 	chan->device = &dmac->engine;
engine           1767 drivers/dma/sh/rcar-dmac.c 	list_add_tail(&chan->device_node, &dmac->engine.channels);
engine           1814 drivers/dma/sh/rcar-dmac.c 	struct dma_device *engine;
engine           1873 drivers/dma/sh/rcar-dmac.c 	engine = &dmac->engine;
engine           1875 drivers/dma/sh/rcar-dmac.c 	dma_cap_set(DMA_MEMCPY, engine->cap_mask);
engine           1876 drivers/dma/sh/rcar-dmac.c 	dma_cap_set(DMA_SLAVE, engine->cap_mask);
engine           1878 drivers/dma/sh/rcar-dmac.c 	engine->dev		= &pdev->dev;
engine           1879 drivers/dma/sh/rcar-dmac.c 	engine->copy_align	= ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE);
engine           1881 drivers/dma/sh/rcar-dmac.c 	engine->src_addr_widths	= widths;
engine           1882 drivers/dma/sh/rcar-dmac.c 	engine->dst_addr_widths	= widths;
engine           1883 drivers/dma/sh/rcar-dmac.c 	engine->directions	= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
engine           1884 drivers/dma/sh/rcar-dmac.c 	engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
engine           1886 drivers/dma/sh/rcar-dmac.c 	engine->device_alloc_chan_resources	= rcar_dmac_alloc_chan_resources;
engine           1887 drivers/dma/sh/rcar-dmac.c 	engine->device_free_chan_resources	= rcar_dmac_free_chan_resources;
engine           1888 drivers/dma/sh/rcar-dmac.c 	engine->device_prep_dma_memcpy		= rcar_dmac_prep_dma_memcpy;
engine           1889 drivers/dma/sh/rcar-dmac.c 	engine->device_prep_slave_sg		= rcar_dmac_prep_slave_sg;
engine           1890 drivers/dma/sh/rcar-dmac.c 	engine->device_prep_dma_cyclic		= rcar_dmac_prep_dma_cyclic;
engine           1891 drivers/dma/sh/rcar-dmac.c 	engine->device_config			= rcar_dmac_device_config;
engine           1892 drivers/dma/sh/rcar-dmac.c 	engine->device_pause			= rcar_dmac_chan_pause;
engine           1893 drivers/dma/sh/rcar-dmac.c 	engine->device_terminate_all		= rcar_dmac_chan_terminate_all;
engine           1894 drivers/dma/sh/rcar-dmac.c 	engine->device_tx_status		= rcar_dmac_tx_status;
engine           1895 drivers/dma/sh/rcar-dmac.c 	engine->device_issue_pending		= rcar_dmac_issue_pending;
engine           1896 drivers/dma/sh/rcar-dmac.c 	engine->device_synchronize		= rcar_dmac_device_synchronize;
engine           1898 drivers/dma/sh/rcar-dmac.c 	INIT_LIST_HEAD(&engine->channels);
engine           1920 drivers/dma/sh/rcar-dmac.c 	ret = dma_async_device_register(engine);
engine           1937 drivers/dma/sh/rcar-dmac.c 	dma_async_device_unregister(&dmac->engine);
engine             98 drivers/dma/sh/usb-dmac.c 	struct dma_device engine;
engine            106 drivers/dma/sh/usb-dmac.c #define to_usb_dmac(d)		container_of(d, struct usb_dmac, engine)
engine            737 drivers/dma/sh/usb-dmac.c 	vchan_init(&uchan->vc, &dmac->engine);
engine            767 drivers/dma/sh/usb-dmac.c 	struct dma_device *engine;
engine            811 drivers/dma/sh/usb-dmac.c 	INIT_LIST_HEAD(&dmac->engine.channels);
engine            830 drivers/dma/sh/usb-dmac.c 	engine = &dmac->engine;
engine            831 drivers/dma/sh/usb-dmac.c 	dma_cap_set(DMA_SLAVE, engine->cap_mask);
engine            833 drivers/dma/sh/usb-dmac.c 	engine->dev = &pdev->dev;
engine            835 drivers/dma/sh/usb-dmac.c 	engine->src_addr_widths = widths;
engine            836 drivers/dma/sh/usb-dmac.c 	engine->dst_addr_widths = widths;
engine            837 drivers/dma/sh/usb-dmac.c 	engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
engine            838 drivers/dma/sh/usb-dmac.c 	engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
engine            840 drivers/dma/sh/usb-dmac.c 	engine->device_alloc_chan_resources = usb_dmac_alloc_chan_resources;
engine            841 drivers/dma/sh/usb-dmac.c 	engine->device_free_chan_resources = usb_dmac_free_chan_resources;
engine            842 drivers/dma/sh/usb-dmac.c 	engine->device_prep_slave_sg = usb_dmac_prep_slave_sg;
engine            843 drivers/dma/sh/usb-dmac.c 	engine->device_terminate_all = usb_dmac_chan_terminate_all;
engine            844 drivers/dma/sh/usb-dmac.c 	engine->device_tx_status = usb_dmac_tx_status;
engine            845 drivers/dma/sh/usb-dmac.c 	engine->device_issue_pending = usb_dmac_issue_pending;
engine            847 drivers/dma/sh/usb-dmac.c 	ret = dma_async_device_register(engine);
engine            877 drivers/dma/sh/usb-dmac.c 	dma_async_device_unregister(&dmac->engine);
engine            600 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
engine            611 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 	switch (engine) {
engine            622 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 		pr_err("Invalid engine in IB submission: %d\n", engine);
engine            134 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
engine           5128 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
engine           1688 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
engine            359 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 		.engine = DDC_I2C_COMMAND_ENGINE,
engine            565 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 			.engine = DDC_I2C_COMMAND_ENGINE,
engine            106 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h 	enum i2c_command_engine engine;
engine             41 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	engine->ctx->logger
engine             59 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct dce_aux *engine)
engine             61 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
engine             63 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	dal_ddc_close(engine->ddc);
engine             65 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	engine->ddc = NULL;
engine             74 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct dce_aux *engine)
engine             76 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
engine             87 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct dce_aux *engine)
engine             89 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
engine            163 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct dce_aux *engine,
engine            166 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
engine            256 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
engine            260 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c static int read_channel_reply(struct dce_aux *engine, uint32_t size,
engine            264 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
engine            314 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct dce_aux *engine,
engine            317 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
engine            378 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 		const struct dce_aux *engine)
engine            384 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct dce_aux *engine,
engine            389 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	if ((engine == NULL) || !is_engine_available(engine))
engine            398 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	if (!acquire_engine(engine)) {
engine            403 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	engine->ddc = ddc;
engine            408 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c void dce110_engine_destroy(struct dce_aux **engine)
engine            411 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine);
engine            414 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	*engine = NULL;
engine            130 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h void dce110_engine_destroy(struct dce_aux **engine);
engine            368 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct dce_i2c_sw *engine,
engine            373 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	engine->speed = speed ? speed : DCE_I2C_DEFAULT_I2C_SW_SPEED;
engine            375 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	engine->clock_delay = 1000 / engine->speed;
engine            377 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (engine->clock_delay < 12)
engine            378 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		engine->clock_delay = 12;
engine            382 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct dce_i2c_sw *engine,
engine            393 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	engine->ddc = ddc;
engine            426 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct dce_i2c_sw *engine,
engine            429 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct ddc *ddc = engine->ddc;
engine            430 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	uint16_t clock_delay_div_4 = engine->clock_delay >> 2;
engine            434 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4);
engine            442 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 			result = i2c_write_sw(engine->ctx, ddc, clock_delay_div_4,
engine            447 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 			result = i2c_read_sw(engine->ctx, ddc, clock_delay_div_4,
engine            461 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		if (!stop_sync_sw(engine->ctx, ddc, clock_delay_div_4))
engine            469 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct dce_i2c_sw *engine,
engine            488 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	dce_i2c_sw_engine_submit_channel_request(engine, &request);
engine            532 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	struct dce_i2c_sw *engine = NULL;
engine            535 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 		engine = pool->sw_i2cs[line];
engine            537 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!engine)
engine            540 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	if (!dce_i2c_engine_acquire_sw(engine, ddc))
engine            543 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c 	return engine;
engine            456 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	enum engine_id engine)
engine            458 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	switch (engine) {
engine           1350 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	enum engine_id engine,
engine           1356 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	if (engine != ENGINE_ID_UNKNOWN) {
engine           1361 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 			field |= get_frontend_source(engine);
engine           1363 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 			field &= ~get_frontend_source(engine);
engine            255 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	enum engine_id engine,
engine            427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	enum engine_id engine)
engine            429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	switch (engine) {
engine           1317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	enum engine_id engine,
engine           1323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	if (engine != ENGINE_ID_UNKNOWN) {
engine           1328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 			field |= get_frontend_source(engine);
engine           1330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 			field &= ~get_frontend_source(engine);
engine            495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	enum engine_id engine,
engine            146 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine);
engine            148 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            151 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            154 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            157 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            163 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            165 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 	bool (*is_engine_available)(struct aux_engine *engine);
engine            167 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		const struct aux_engine *engine);
engine            169 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            172 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine,
engine            176 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine *engine);
engine            178 drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h 		struct aux_engine **engine);
engine            169 drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h 		enum engine_id engine,
engine             78 drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c 	enum engine_id engine,
engine           1361 drivers/gpu/drm/i915/display/intel_overlay.c 	overlay->context = dev_priv->engine[RCS0]->kernel_context;
engine             60 drivers/gpu/drm/i915/gem/i915_gem_busy.c 	BUILD_BUG_ON(!typecheck(u16, rq->engine->uabi_class));
engine             61 drivers/gpu/drm/i915/gem/i915_gem_busy.c 	return flag(rq->engine->uabi_class);
engine            158 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c 	struct drm_i915_private *i915 = w->ce->engine->i915;
engine            203 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c 	if (w->ce->engine->emit_init_breadcrumb) {
engine            204 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c 		err = w->ce->engine->emit_init_breadcrumb(rq);
engine            218 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c 	err = w->ce->engine->emit_bb_start(rq,
engine            154 drivers/gpu/drm/i915/gem/i915_gem_context.c 		struct intel_engine_cs *engine;
engine            156 drivers/gpu/drm/i915/gem/i915_gem_context.c 		engine = intel_engine_lookup_user(ctx->i915,
engine            159 drivers/gpu/drm/i915/gem/i915_gem_context.c 		if (!engine)
engine            162 drivers/gpu/drm/i915/gem/i915_gem_context.c 		idx = engine->legacy_idx;
engine            285 drivers/gpu/drm/i915/gem/i915_gem_context.c 	struct intel_engine_cs *engine;
engine            294 drivers/gpu/drm/i915/gem/i915_gem_context.c 	for_each_engine(engine, gt, id) {
engine            297 drivers/gpu/drm/i915/gem/i915_gem_context.c 		ce = intel_context_create(ctx, engine);
engine            897 drivers/gpu/drm/i915/gem/i915_gem_context.c 				       ce->engine->mask)) {
engine            902 drivers/gpu/drm/i915/gem/i915_gem_context.c 		if (!(ce->engine->mask & engines))
engine            987 drivers/gpu/drm/i915/gem/i915_gem_context.c 	struct intel_engine_cs *engine = rq->engine;
engine            988 drivers/gpu/drm/i915/gem/i915_gem_context.c 	u32 base = engine->mmio_base;
engine           1009 drivers/gpu/drm/i915/gem/i915_gem_context.c 	} else if (HAS_LOGICAL_RING_CONTEXTS(engine->i915)) {
engine           1037 drivers/gpu/drm/i915/gem/i915_gem_context.c 	if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
engine           1149 drivers/gpu/drm/i915/gem/i915_gem_context.c 	rq = i915_request_create(ce->engine->kernel_context);
engine           1168 drivers/gpu/drm/i915/gem/i915_gem_context.c 	GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
engine           1190 drivers/gpu/drm/i915/gem/i915_gem_context.c 	struct drm_i915_private *i915 = ce->engine->i915;
engine           1332 drivers/gpu/drm/i915/gem/i915_gem_context.c 	ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
engine           1337 drivers/gpu/drm/i915/gem/i915_gem_context.c 	if (ce->engine->class != RENDER_CLASS) {
engine           1480 drivers/gpu/drm/i915/gem/i915_gem_context.c 	virtual = set->engines->engines[idx]->engine;
engine           1586 drivers/gpu/drm/i915/gem/i915_gem_context.c 		struct intel_engine_cs *engine;
engine           1600 drivers/gpu/drm/i915/gem/i915_gem_context.c 		engine = intel_engine_lookup_user(ctx->i915,
engine           1603 drivers/gpu/drm/i915/gem/i915_gem_context.c 		if (!engine) {
engine           1610 drivers/gpu/drm/i915/gem/i915_gem_context.c 		ce = intel_context_create(ctx, engine);
engine           1729 drivers/gpu/drm/i915/gem/i915_gem_context.c 			ci.engine_class = e->engines[n]->engine->uabi_class;
engine           1730 drivers/gpu/drm/i915/gem/i915_gem_context.c 			ci.engine_instance = e->engines[n]->engine->uabi_instance;
engine           1865 drivers/gpu/drm/i915/gem/i915_gem_context.c 		struct intel_engine_cs *engine;
engine           1871 drivers/gpu/drm/i915/gem/i915_gem_context.c 		engine = e->engines[n]->engine;
engine           1882 drivers/gpu/drm/i915/gem/i915_gem_context.c 		if (intel_engine_is_virtual(engine))
engine           1884 drivers/gpu/drm/i915/gem/i915_gem_context.c 				intel_execlists_clone_virtual(dst, engine);
engine           1886 drivers/gpu/drm/i915/gem/i915_gem_context.c 			clone->engines[n] = intel_context_create(dst, engine);
engine           1941 drivers/gpu/drm/i915/gem/i915_gem_context.c 		if (clone->engines[n]->engine->class != ce->engine->class) {
engine           2185 drivers/gpu/drm/i915/gem/i915_gem_context.c 	ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
engine            224 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	struct intel_engine_cs *engine; /** engine to queue the request to */
engine            299 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	return intel_engine_requires_cmd_parser(eb->engine) ||
engine            300 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 		(intel_engine_using_cmd_parser(eb->engine) &&
engine            942 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	intel_gt_chipset_flush(cache->rq->engine->gt);
engine           1153 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	pool = intel_engine_pool_get(&eb->engine->pool, PAGE_SIZE);
engine           1190 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	err = eb->engine->emit_bb_start(rq,
engine           1244 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 		if (!intel_engine_can_store_dword(eb->engine))
engine           1906 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	intel_gt_chipset_flush(eb->engine->gt);
engine           1943 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) {
engine           1998 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	pool = intel_engine_pool_get(&eb->engine->pool, eb->batch_len);
engine           2012 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 				      eb->engine,
engine           2091 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	if (eb->engine->emit_init_breadcrumb) {
engine           2092 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 		err = eb->engine->emit_init_breadcrumb(eb->request);
engine           2097 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	err = eb->engine->emit_bb_start(eb->request,
engine           2213 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	err = intel_gt_terminally_wedged(ce->engine->gt);
engine           2257 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	eb->engine = ce->engine;
engine           2657 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 						   eb.engine->bond_execute);
engine            372 drivers/gpu/drm/i915/gem/i915_gem_object.h 	struct intel_engine_cs *engine = NULL;
engine            380 drivers/gpu/drm/i915/gem/i915_gem_object.h 		engine = to_request(fence)->engine;
engine            383 drivers/gpu/drm/i915/gem/i915_gem_object.h 	return engine;
engine             29 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	GEM_BUG_ON(intel_engine_is_virtual(ce->engine));
engine             30 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	intel_engine_pm_get(ce->engine);
engine             35 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	pool = intel_engine_pool_get(&ce->engine->pool, size);
engine            100 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	intel_engine_pm_put(ce->engine);
engine            123 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	intel_engine_pm_put(ce->engine);
engine            169 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	if (ce->engine->emit_init_breadcrumb) {
engine            170 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 		err = ce->engine->emit_init_breadcrumb(rq);
engine            183 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	err = ce->engine->emit_bb_start(rq,
engine            213 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	GEM_BUG_ON(intel_engine_is_virtual(ce->engine));
engine            214 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	intel_engine_pm_get(ce->engine);
engine            219 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	pool = intel_engine_pool_get(&ce->engine->pool, size);
engine            299 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	intel_engine_pm_put(ce->engine);
engine            374 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	if (rq->engine->emit_init_breadcrumb) {
engine            375 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 		err = rq->engine->emit_init_breadcrumb(rq);
engine            380 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c 	err = rq->engine->emit_bb_start(rq,
engine             14 drivers/gpu/drm/i915/gem/i915_gem_pm.c static void call_idle_barriers(struct intel_engine_cs *engine)
engine             18 drivers/gpu/drm/i915/gem/i915_gem_pm.c 	llist_for_each_safe(node, next, llist_del_all(&engine->barrier_tasks)) {
engine             32 drivers/gpu/drm/i915/gem/i915_gem_pm.c 	struct intel_engine_cs *engine;
engine             37 drivers/gpu/drm/i915/gem/i915_gem_pm.c 	for_each_engine(engine, i915, id)
engine             38 drivers/gpu/drm/i915/gem/i915_gem_pm.c 		call_idle_barriers(engine); /* cleanup after wedging */
engine            100 drivers/gpu/drm/i915/gem/i915_gem_wait.c 	struct intel_engine_cs *engine;
engine            106 drivers/gpu/drm/i915/gem/i915_gem_wait.c 	engine = rq->engine;
engine            110 drivers/gpu/drm/i915/gem/i915_gem_wait.c 	if (engine->schedule)
engine            111 drivers/gpu/drm/i915/gem/i915_gem_wait.c 		engine->schedule(rq, attr);
engine            884 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		     struct intel_engine_cs *engine,
engine            896 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	return igt_gpu_fill_dw(vma, ctx, engine, dw * sizeof(u32),
engine            933 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 			    struct intel_engine_cs *engine,
engine            938 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
engine            967 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	err = gpu_write(vma, ctx, engine, dword, val);
engine            993 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	struct intel_engine_cs *engine;
engine           1015 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	for_each_engine(engine, i915, id) {
engine           1016 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		if (!intel_engine_can_store_dword(engine)) {
engine           1021 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		engines[n++] = engine;
engine           1047 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		engine = engines[order[i] % n];
engine           1060 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		err = __igt_write_huge(ctx, engine, obj, size, offset_low,
engine           1065 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		err = __igt_write_huge(ctx, engine, obj, size, offset_high,
engine           1072 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 				__func__, engine->id, offset_low, offset_high,
engine           1321 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	struct intel_engine_cs *engine;
engine           1422 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	for_each_engine(engine, dev_priv, id) {
engine           1423 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		if (!intel_engine_can_store_dword(engine))
engine           1426 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf);
engine           1510 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	struct intel_engine_cs *engine;
engine           1551 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	for_each_engine(engine, i915, id) {
engine           1552 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		if (!intel_engine_can_store_dword(engine))
engine           1555 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf);
engine             18 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
engine            199 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c 	rq = i915_request_create(i915->engine[RCS0]->kernel_context);
engine            260 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c 	return intel_engine_can_store_dword(i915->engine[RCS0]);
engine             32 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct intel_engine_cs *engine;
engine             71 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	for_each_engine(engine, i915, id) {
engine             78 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			rq = igt_request_alloc(ctx[n], engine);
engine             95 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			nctx, engine->name, ktime_to_ns(times[1] - times[0]));
engine             97 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		err = igt_live_test_begin(&t, i915, __func__, engine->name);
engine            106 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 				rq = igt_request_alloc(ctx[n % nctx], engine);
engine            148 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			engine->name,
engine            171 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		    struct intel_engine_cs *engine,
engine            174 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
engine            179 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	GEM_BUG_ON(!intel_engine_can_store_dword(engine));
engine            205 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			      engine,
engine            354 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct intel_engine_cs *engine;
engine            367 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	for_each_engine(engine, i915, id) {
engine            375 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		if (!intel_engine_can_store_dword(engine))
engine            378 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		if (!engine->context_size)
engine            387 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		err = igt_live_test_begin(&t, i915, __func__, engine->name);
engine            411 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			err = gpu_fill(obj, ctx, engine, dw);
engine            415 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 				       engine->name, ctx->hw_id,
engine            430 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			ncontexts, engine->name, ndwords);
engine            463 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct intel_engine_cs *engine;
engine            498 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	for_each_engine(engine, i915, id) {
engine            504 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		if (!intel_engine_can_store_dword(engine))
engine            530 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			err = gpu_fill(obj, ctx, engine, dw);
engine            534 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 				       engine->name, ctx->hw_id,
engine            551 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			ncontexts, engine->name, ndwords);
engine            634 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
engine            662 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	err = rq->engine->emit_bb_start(rq,
engine            730 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	ret = igt_spinner_init(*spin, ce->engine->gt);
engine            789 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	if (INTEL_GEN(ce->engine->i915) >= 11) {
engine            839 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	unsigned int slices = hweight32(ce->engine->sseu.slice_mask);
engine            844 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		ret = intel_engine_reset(ce->engine, "sseu");
engine            855 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	ret = __read_slice_count(ce->engine->kernel_context, obj, NULL, &rpcs);
engine            863 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		ret = i915_gem_wait_for_idle(ce->engine->i915,
engine            911 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct intel_engine_cs *engine = i915->engine[RCS0];
engine            919 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	if (INTEL_GEN(i915) < 9 || !engine)
engine            925 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	if (hweight32(engine->sseu.slice_mask) < 2)
engine            932 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	pg_sseu = engine->sseu;
engine            935 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		~(~0 << (hweight32(engine->sseu.subslice_mask) / 2));
engine            938 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		name, flags, hweight32(engine->sseu.slice_mask),
engine            974 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	ret = __sseu_test(name, flags, ce, obj, engine->sseu);
engine            984 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	ret = __sseu_test(name, flags, ce, obj, engine->sseu);
engine           1085 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		struct intel_engine_cs *engine;
engine           1088 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		for_each_engine(engine, i915, id) {
engine           1089 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			if (!intel_engine_can_store_dword(engine))
engine           1103 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			err = gpu_fill(obj, ctx, engine, dw);
engine           1107 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 				       engine->name, ctx->hw_id,
engine           1165 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			    struct intel_engine_cs *engine,
engine           1214 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	rq = igt_request_alloc(ctx, engine);
engine           1220 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
engine           1252 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			     struct intel_engine_cs *engine,
engine           1313 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	rq = igt_request_alloc(ctx, engine);
engine           1319 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
engine           1369 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct intel_engine_cs *engine;
engine           1417 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	for_each_engine(engine, i915, id) {
engine           1421 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		if (!intel_engine_can_store_dword(engine))
engine           1433 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 			err = write_to_scratch(ctx_a, engine,
engine           1436 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 				err = read_from_scratch(ctx_b, engine,
engine           1443 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 				       engine->name, value,
engine           1470 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	struct intel_engine_cs *engine;
engine           1476 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	for_each_engine_masked(engine, i915, engines, tmp)
engine           1477 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 		return engine->name;
engine           1546 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	rq = igt_request_alloc(ctx, i915->engine[RCS0]);
engine            331 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	struct intel_engine_cs *engine;
engine            344 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	for_each_engine(engine, i915, id) {
engine            347 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		rq = i915_request_create(engine->kernel_context);
engine             18 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
engine            109 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
engine             18 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c igt_request_alloc(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
engine             28 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 	ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
engine            106 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 		    struct intel_engine_cs *engine,
engine            111 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
engine            118 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 	GEM_BUG_ON(!intel_engine_can_store_dword(engine));
engine            125 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 	rq = igt_request_alloc(ctx, engine);
engine            135 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c 	err = engine->emit_bb_start(rq,
engine             18 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h igt_request_alloc(struct i915_gem_context *ctx, struct intel_engine_cs *engine);
engine             28 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h 		    struct intel_engine_cs *engine,
engine             32 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c static void irq_enable(struct intel_engine_cs *engine)
engine             34 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	if (!engine->irq_enable)
engine             38 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	spin_lock(&engine->gt->irq_lock);
engine             39 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	engine->irq_enable(engine);
engine             40 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	spin_unlock(&engine->gt->irq_lock);
engine             43 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c static void irq_disable(struct intel_engine_cs *engine)
engine             45 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	if (!engine->irq_disable)
engine             49 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	spin_lock(&engine->gt->irq_lock);
engine             50 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	engine->irq_disable(engine);
engine             51 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	spin_unlock(&engine->gt->irq_lock);
engine             67 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
engine             69 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_breadcrumbs *b = &engine->breadcrumbs;
engine            131 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine)
engine            133 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_breadcrumbs *b = &engine->breadcrumbs;
engine            202 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine)
engine            205 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	intel_engine_breadcrumbs_irq(engine);
engine            211 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_engine_cs *engine =
engine            212 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 		container_of(work, typeof(*engine), breadcrumbs.irq_work);
engine            214 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	intel_engine_breadcrumbs_irq(engine);
engine            219 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_engine_cs *engine =
engine            243 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 		irq_enable(engine);
engine            246 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
engine            248 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_breadcrumbs *b = &engine->breadcrumbs;
engine            256 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine)
engine            258 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_breadcrumbs *b = &engine->breadcrumbs;
engine            264 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 		irq_enable(engine);
engine            266 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 		irq_disable(engine);
engine            271 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
engine            281 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 		struct intel_breadcrumbs *b = &rq->engine->breadcrumbs;
engine            325 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_breadcrumbs *b = &rq->engine->breadcrumbs;
engine            349 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
engine            352 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 	struct intel_breadcrumbs *b = &engine->breadcrumbs;
engine             34 drivers/gpu/drm/i915/gt/intel_context.c 		     struct intel_engine_cs *engine)
engine             42 drivers/gpu/drm/i915/gt/intel_context.c 	intel_context_init(ce, ctx, engine);
engine             65 drivers/gpu/drm/i915/gt/intel_context.c 		with_intel_runtime_pm(&ce->engine->i915->runtime_pm, wakeref)
engine             71 drivers/gpu/drm/i915/gt/intel_context.c 			  ce->engine->name, ce->timeline->fence_context,
engine            101 drivers/gpu/drm/i915/gt/intel_context.c 			  ce->engine->name, ce->timeline->fence_context);
engine            146 drivers/gpu/drm/i915/gt/intel_context.c 		  ce->engine->name, ce->timeline->fence_context);
engine            200 drivers/gpu/drm/i915/gt/intel_context.c 							      ce->engine);
engine            220 drivers/gpu/drm/i915/gt/intel_context.c 		   struct intel_engine_cs *engine)
engine            222 drivers/gpu/drm/i915/gt/intel_context.c 	GEM_BUG_ON(!engine->cops);
engine            227 drivers/gpu/drm/i915/gt/intel_context.c 	ce->vm = i915_vm_get(ctx->vm ?: &engine->gt->ggtt->vm);
engine            231 drivers/gpu/drm/i915/gt/intel_context.c 	ce->engine = engine;
engine            232 drivers/gpu/drm/i915/gt/intel_context.c 	ce->ops = engine->cops;
engine            233 drivers/gpu/drm/i915/gt/intel_context.c 	ce->sseu = engine->sseu;
engine            282 drivers/gpu/drm/i915/gt/intel_context.c 	intel_engine_pm_get(ce->engine);
engine            289 drivers/gpu/drm/i915/gt/intel_context.c 	intel_engine_pm_put(ce->engine);
engine             19 drivers/gpu/drm/i915/gt/intel_context.h 			struct intel_engine_cs *engine);
engine             24 drivers/gpu/drm/i915/gt/intel_context.h 		     struct intel_engine_cs *engine);
engine             41 drivers/gpu/drm/i915/gt/intel_context_types.h 	struct intel_engine_cs *engine;
engine            157 drivers/gpu/drm/i915/gt/intel_engine.h intel_read_status_page(const struct intel_engine_cs *engine, int reg)
engine            160 drivers/gpu/drm/i915/gt/intel_engine.h 	return READ_ONCE(engine->status_page.addr[reg]);
engine            164 drivers/gpu/drm/i915/gt/intel_engine.h intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
engine            173 drivers/gpu/drm/i915/gt/intel_engine.h 		clflush(&engine->status_page.addr[reg]);
engine            174 drivers/gpu/drm/i915/gt/intel_engine.h 		engine->status_page.addr[reg] = value;
engine            175 drivers/gpu/drm/i915/gt/intel_engine.h 		clflush(&engine->status_page.addr[reg]);
engine            178 drivers/gpu/drm/i915/gt/intel_engine.h 		WRITE_ONCE(engine->status_page.addr[reg], value);
engine            210 drivers/gpu/drm/i915/gt/intel_engine.h intel_engine_create_ring(struct intel_engine_cs *engine, int size);
engine            228 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_stop(struct intel_engine_cs *engine);
engine            229 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_cleanup(struct intel_engine_cs *engine);
engine            338 drivers/gpu/drm/i915/gt/intel_engine.h int intel_engine_init_common(struct intel_engine_cs *engine);
engine            339 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_cleanup_common(struct intel_engine_cs *engine);
engine            341 drivers/gpu/drm/i915/gt/intel_engine.h int intel_ring_submission_setup(struct intel_engine_cs *engine);
engine            342 drivers/gpu/drm/i915/gt/intel_engine.h int intel_ring_submission_init(struct intel_engine_cs *engine);
engine            344 drivers/gpu/drm/i915/gt/intel_engine.h int intel_engine_stop_cs(struct intel_engine_cs *engine);
engine            345 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
engine            347 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
engine            349 drivers/gpu/drm/i915/gt/intel_engine.h u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
engine            350 drivers/gpu/drm/i915/gt/intel_engine.h u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
engine            352 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_get_instdone(struct intel_engine_cs *engine,
engine            355 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_init_execlists(struct intel_engine_cs *engine);
engine            357 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
engine            358 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
engine            360 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine);
engine            361 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
engine            364 drivers/gpu/drm/i915/gt/intel_engine.h intel_engine_queue_breadcrumbs(struct intel_engine_cs *engine)
engine            366 drivers/gpu/drm/i915/gt/intel_engine.h 	irq_work_queue(&engine->breadcrumbs.irq_work);
engine            369 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine);
engine            371 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
engine            372 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
engine            374 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
engine            425 drivers/gpu/drm/i915/gt/intel_engine.h static inline void __intel_engine_reset(struct intel_engine_cs *engine,
engine            428 drivers/gpu/drm/i915/gt/intel_engine.h 	if (engine->reset.reset)
engine            429 drivers/gpu/drm/i915/gt/intel_engine.h 		engine->reset.reset(engine, stalled);
engine            430 drivers/gpu/drm/i915/gt/intel_engine.h 	engine->serial++; /* contexts lost */
engine            433 drivers/gpu/drm/i915/gt/intel_engine.h bool intel_engine_is_idle(struct intel_engine_cs *engine);
engine            438 drivers/gpu/drm/i915/gt/intel_engine.h bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
engine            441 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_dump(struct intel_engine_cs *engine,
engine            445 drivers/gpu/drm/i915/gt/intel_engine.h static inline void intel_engine_context_in(struct intel_engine_cs *engine)
engine            449 drivers/gpu/drm/i915/gt/intel_engine.h 	if (READ_ONCE(engine->stats.enabled) == 0)
engine            452 drivers/gpu/drm/i915/gt/intel_engine.h 	write_seqlock_irqsave(&engine->stats.lock, flags);
engine            454 drivers/gpu/drm/i915/gt/intel_engine.h 	if (engine->stats.enabled > 0) {
engine            455 drivers/gpu/drm/i915/gt/intel_engine.h 		if (engine->stats.active++ == 0)
engine            456 drivers/gpu/drm/i915/gt/intel_engine.h 			engine->stats.start = ktime_get();
engine            457 drivers/gpu/drm/i915/gt/intel_engine.h 		GEM_BUG_ON(engine->stats.active == 0);
engine            460 drivers/gpu/drm/i915/gt/intel_engine.h 	write_sequnlock_irqrestore(&engine->stats.lock, flags);
engine            463 drivers/gpu/drm/i915/gt/intel_engine.h static inline void intel_engine_context_out(struct intel_engine_cs *engine)
engine            467 drivers/gpu/drm/i915/gt/intel_engine.h 	if (READ_ONCE(engine->stats.enabled) == 0)
engine            470 drivers/gpu/drm/i915/gt/intel_engine.h 	write_seqlock_irqsave(&engine->stats.lock, flags);
engine            472 drivers/gpu/drm/i915/gt/intel_engine.h 	if (engine->stats.enabled > 0) {
engine            475 drivers/gpu/drm/i915/gt/intel_engine.h 		if (engine->stats.active && --engine->stats.active == 0) {
engine            480 drivers/gpu/drm/i915/gt/intel_engine.h 			last = ktime_sub(ktime_get(), engine->stats.start);
engine            482 drivers/gpu/drm/i915/gt/intel_engine.h 			engine->stats.total = ktime_add(engine->stats.total,
engine            484 drivers/gpu/drm/i915/gt/intel_engine.h 		} else if (engine->stats.active == 0) {
engine            490 drivers/gpu/drm/i915/gt/intel_engine.h 			last = ktime_sub(ktime_get(), engine->stats.enabled_at);
engine            492 drivers/gpu/drm/i915/gt/intel_engine.h 			engine->stats.total = ktime_add(engine->stats.total,
engine            497 drivers/gpu/drm/i915/gt/intel_engine.h 	write_sequnlock_irqrestore(&engine->stats.lock, flags);
engine            500 drivers/gpu/drm/i915/gt/intel_engine.h int intel_enable_engine_stats(struct intel_engine_cs *engine);
engine            501 drivers/gpu/drm/i915/gt/intel_engine.h void intel_disable_engine_stats(struct intel_engine_cs *engine);
engine            503 drivers/gpu/drm/i915/gt/intel_engine.h ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
engine            506 drivers/gpu/drm/i915/gt/intel_engine.h intel_engine_find_active_request(struct intel_engine_cs *engine);
engine            530 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_init_active(struct intel_engine_cs *engine,
engine            239 drivers/gpu/drm/i915/gt/intel_engine_cs.c static void __sprint_engine_name(struct intel_engine_cs *engine)
engine            246 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
engine            247 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			     intel_engine_class_repr(engine->class),
engine            248 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			     engine->instance) >= sizeof(engine->name));
engine            251 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
engine            257 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
engine            260 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (INTEL_GEN(engine->i915) >= 3)
engine            261 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		ENGINE_WRITE(engine, RING_HWSTAM, mask);
engine            263 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		ENGINE_WRITE16(engine, RING_HWSTAM, mask);
engine            266 drivers/gpu/drm/i915/gt/intel_engine_cs.c static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
engine            269 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_set_hwsp_writemask(engine, ~0u);
engine            275 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine            289 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
engine            290 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!engine)
engine            293 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
engine            295 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->id = id;
engine            296 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->mask = BIT(id);
engine            297 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->i915 = gt->i915;
engine            298 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->gt = gt;
engine            299 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->uncore = gt->uncore;
engine            300 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->hw_id = engine->guc_id = info->hw_id;
engine            301 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->mmio_base = __engine_mmio_base(gt->i915, info->mmio_bases);
engine            303 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->class = info->class;
engine            304 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->instance = info->instance;
engine            305 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	__sprint_engine_name(engine);
engine            311 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->destroy = (typeof(engine->destroy))kfree;
engine            313 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->context_size = intel_engine_context_size(gt->i915,
engine            314 drivers/gpu/drm/i915/gt/intel_engine_cs.c 							 engine->class);
engine            315 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (WARN_ON(engine->context_size > BIT(20)))
engine            316 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		engine->context_size = 0;
engine            317 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (engine->context_size)
engine            321 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->schedule = NULL;
engine            323 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	seqlock_init(&engine->stats.lock);
engine            325 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
engine            328 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_sanitize_mmio(engine);
engine            330 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	gt->engine_class[info->class][info->instance] = engine;
engine            332 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_add_user(engine);
engine            333 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	gt->i915->engine[id] = engine;
engine            338 drivers/gpu/drm/i915/gt/intel_engine_cs.c static void __setup_engine_capabilities(struct intel_engine_cs *engine)
engine            340 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct drm_i915_private *i915 = engine->i915;
engine            342 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (engine->class == VIDEO_DECODE_CLASS) {
engine            348 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		    (INTEL_GEN(i915) >= 9 && engine->instance == 0))
engine            349 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			engine->uabi_capabilities |=
engine            357 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		     RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
engine            358 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		    (INTEL_GEN(i915) >= 9 && engine->instance == 0))
engine            359 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			engine->uabi_capabilities |=
engine            361 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
engine            363 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			engine->uabi_capabilities |=
engine            370 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine            373 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	for_each_engine(engine, i915, id)
engine            374 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		__setup_engine_capabilities(engine);
engine            383 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine            386 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	for_each_engine(engine, i915, id) {
engine            387 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		engine->destroy(engine);
engine            388 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		i915->engine[id] = NULL;
engine            453 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	int (*init)(struct intel_engine_cs *engine);
engine            454 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine            463 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	for_each_engine(engine, i915, id) {
engine            464 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		err = init(engine);
engine            476 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_init_execlists(struct intel_engine_cs *engine)
engine            478 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            492 drivers/gpu/drm/i915/gt/intel_engine_cs.c static void cleanup_status_page(struct intel_engine_cs *engine)
engine            497 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_set_hwsp_writemask(engine, ~0u);
engine            499 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	vma = fetch_and_zero(&engine->status_page.vma);
engine            503 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!HWS_NEEDS_PHYSICAL(engine->i915))
engine            510 drivers/gpu/drm/i915/gt/intel_engine_cs.c static int pin_ggtt_status_page(struct intel_engine_cs *engine,
engine            516 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!HAS_LLC(engine->i915))
engine            535 drivers/gpu/drm/i915/gt/intel_engine_cs.c static int init_status_page(struct intel_engine_cs *engine)
engine            549 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
engine            557 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
engine            569 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
engine            570 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->status_page.vma = vma;
engine            572 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
engine            573 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		ret = pin_ggtt_status_page(engine, vma);
engine            587 drivers/gpu/drm/i915/gt/intel_engine_cs.c static int intel_engine_setup_common(struct intel_engine_cs *engine)
engine            591 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	init_llist_head(&engine->barrier_tasks);
engine            593 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	err = init_status_page(engine);
engine            597 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_active(engine, ENGINE_PHYSICAL);
engine            598 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_breadcrumbs(engine);
engine            599 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_execlists(engine);
engine            600 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_hangcheck(engine);
engine            601 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_cmd_parser(engine);
engine            602 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init__pm(engine);
engine            604 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_pool_init(&engine->pool);
engine            607 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->sseu =
engine            608 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
engine            610 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_workarounds(engine);
engine            611 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_whitelist(engine);
engine            612 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_init_ctx_wa(engine);
engine            628 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	int (*setup)(struct intel_engine_cs *engine);
engine            629 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine            638 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	for_each_engine(engine, i915, id) {
engine            639 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		err = intel_engine_setup_common(engine);
engine            643 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		err = setup(engine);
engine            648 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		GEM_BUG_ON(engine->destroy == (typeof(engine->destroy))kfree);
engine            650 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		GEM_BUG_ON(!engine->cops);
engine            667 drivers/gpu/drm/i915/gt/intel_engine_cs.c static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
engine            672 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	GEM_BUG_ON(!engine->gt->scratch);
engine            679 drivers/gpu/drm/i915/gt/intel_engine_cs.c 				engine->gt,
engine            680 drivers/gpu/drm/i915/gt/intel_engine_cs.c 				engine->status_page.vma))
engine            688 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	frame->rq.i915 = engine->i915;
engine            689 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	frame->rq.engine = engine;
engine            697 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
engine            710 drivers/gpu/drm/i915/gt/intel_engine_cs.c intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
engine            712 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	INIT_LIST_HEAD(&engine->active.requests);
engine            714 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	spin_lock_init(&engine->active.lock);
engine            715 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	lockdep_set_subclass(&engine->active.lock, subclass);
engine            724 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	lock_map_acquire(&engine->active.lock.dep_map);
engine            725 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	lock_map_release(&engine->active.lock.dep_map);
engine            731 drivers/gpu/drm/i915/gt/intel_engine_cs.c create_kernel_context(struct intel_engine_cs *engine)
engine            736 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ce = intel_context_create(engine->i915->kernel_context, engine);
engine            762 drivers/gpu/drm/i915/gt/intel_engine_cs.c int intel_engine_init_common(struct intel_engine_cs *engine)
engine            767 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->set_default_submission(engine);
engine            777 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ce = create_kernel_context(engine);
engine            781 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->kernel_context = ce;
engine            783 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ret = measure_breadcrumb_dw(engine);
engine            787 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	engine->emit_fini_breadcrumb_dw = ret;
engine            804 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_cleanup_common(struct intel_engine_cs *engine)
engine            806 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	GEM_BUG_ON(!list_empty(&engine->active.requests));
engine            808 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	cleanup_status_page(engine);
engine            810 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_pool_fini(&engine->pool);
engine            811 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_fini_breadcrumbs(engine);
engine            812 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_cleanup_cmd_parser(engine);
engine            814 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (engine->default_state)
engine            815 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		i915_gem_object_put(engine->default_state);
engine            817 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_context_unpin(engine->kernel_context);
engine            818 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_context_put(engine->kernel_context);
engine            819 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
engine            821 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_wa_list_free(&engine->ctx_wa_list);
engine            822 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_wa_list_free(&engine->wa_list);
engine            823 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_wa_list_free(&engine->whitelist);
engine            826 drivers/gpu/drm/i915/gt/intel_engine_cs.c u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
engine            828 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct drm_i915_private *i915 = engine->i915;
engine            833 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
engine            835 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		acthd = ENGINE_READ(engine, RING_ACTHD);
engine            837 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		acthd = ENGINE_READ(engine, ACTHD);
engine            842 drivers/gpu/drm/i915/gt/intel_engine_cs.c u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
engine            846 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (INTEL_GEN(engine->i915) >= 8)
engine            847 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
engine            849 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		bbaddr = ENGINE_READ(engine, RING_BBADDR);
engine            854 drivers/gpu/drm/i915/gt/intel_engine_cs.c int intel_engine_stop_cs(struct intel_engine_cs *engine)
engine            856 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_uncore *uncore = engine->uncore;
engine            857 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	const u32 base = engine->mmio_base;
engine            861 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (INTEL_GEN(engine->i915) < 3)
engine            864 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	GEM_TRACE("%s\n", engine->name);
engine            873 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
engine            883 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
engine            885 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	GEM_TRACE("%s\n", engine->name);
engine            887 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
engine            902 drivers/gpu/drm/i915/gt/intel_engine_cs.c read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
engine            905 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct drm_i915_private *i915 = engine->i915;
engine            906 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_uncore *uncore = engine->uncore;
engine            947 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_get_instdone(struct intel_engine_cs *engine,
engine            950 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct drm_i915_private *i915 = engine->i915;
engine            951 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_uncore *uncore = engine->uncore;
engine            952 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	u32 mmio_base = engine->mmio_base;
engine            963 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		if (engine->id != RCS0)
engine            970 drivers/gpu/drm/i915/gt/intel_engine_cs.c 				read_subslice_reg(engine, slice, subslice,
engine            973 drivers/gpu/drm/i915/gt/intel_engine_cs.c 				read_subslice_reg(engine, slice, subslice,
engine            981 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		if (engine->id != RCS0)
engine            997 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		if (engine->id == RCS0)
engine           1009 drivers/gpu/drm/i915/gt/intel_engine_cs.c static bool ring_is_idle(struct intel_engine_cs *engine)
engine           1013 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (I915_SELFTEST_ONLY(!engine->mmio_base))
engine           1016 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!intel_engine_pm_get_if_awake(engine))
engine           1020 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
engine           1021 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	    (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
engine           1025 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (INTEL_GEN(engine->i915) > 2 &&
engine           1026 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	    !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
engine           1029 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_pm_put(engine);
engine           1041 drivers/gpu/drm/i915/gt/intel_engine_cs.c bool intel_engine_is_idle(struct intel_engine_cs *engine)
engine           1044 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (intel_gt_is_wedged(engine->gt))
engine           1047 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!intel_engine_pm_is_awake(engine))
engine           1051 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (execlists_active(&engine->execlists)) {
engine           1052 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		struct tasklet_struct *t = &engine->execlists.tasklet;
engine           1054 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		synchronize_hardirq(engine->i915->drm.pdev->irq);
engine           1068 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		if (execlists_active(&engine->execlists))
engine           1073 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
engine           1077 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	return ring_is_idle(engine);
engine           1082 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine           1096 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	for_each_engine(engine, gt->i915, id) {
engine           1097 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		if (!intel_engine_is_idle(engine))
engine           1106 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_cs *engine;
engine           1109 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	for_each_engine(engine, gt->i915, id)
engine           1110 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		engine->set_default_submission(engine);
engine           1113 drivers/gpu/drm/i915/gt/intel_engine_cs.c bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
engine           1115 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	switch (INTEL_GEN(engine->i915)) {
engine           1120 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
engine           1122 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
engine           1196 drivers/gpu/drm/i915/gt/intel_engine_cs.c static void intel_engine_print_registers(struct intel_engine_cs *engine,
engine           1199 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct drm_i915_private *dev_priv = engine->i915;
engine           1200 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           1203 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
engine           1204 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
engine           1206 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   ENGINE_READ(engine, RING_START));
engine           1208 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
engine           1210 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
engine           1212 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   ENGINE_READ(engine, RING_CTL),
engine           1213 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
engine           1214 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (INTEL_GEN(engine->i915) > 2) {
engine           1216 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_MI_MODE),
engine           1217 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
engine           1222 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_IMR));
engine           1225 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	addr = intel_engine_get_active_head(engine);
engine           1228 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	addr = intel_engine_get_last_batch_head(engine);
engine           1232 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
engine           1234 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		addr = ENGINE_READ(engine, RING_DMA_FADD);
engine           1236 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		addr = ENGINE_READ(engine, DMA_FADD_I8XX);
engine           1241 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_IPEIR));
engine           1243 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_IPEHR));
engine           1245 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
engine           1246 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
engine           1252 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
engine           1258 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
engine           1259 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
engine           1268 drivers/gpu/drm/i915/gt/intel_engine_cs.c 					  &engine->execlists.tasklet.state)),
engine           1269 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
engine           1313 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_PP_DIR_BASE));
engine           1315 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
engine           1317 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			   ENGINE_READ(engine, RING_PP_DIR_DCLV));
engine           1354 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_dump(struct intel_engine_cs *engine,
engine           1358 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct i915_gpu_error * const error = &engine->i915->gpu_error;
engine           1371 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (intel_gt_is_wedged(engine->gt))
engine           1374 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
engine           1376 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
engine           1378 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		   i915_reset_engine_count(error, engine),
engine           1383 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine           1384 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	rq = intel_engine_find_active_request(engine);
engine           1403 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine           1405 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
engine           1406 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	wakeref = intel_runtime_pm_get_if_in_use(&engine->i915->runtime_pm);
engine           1408 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		intel_engine_print_registers(engine, m);
engine           1409 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		intel_runtime_pm_put(&engine->i915->runtime_pm, wakeref);
engine           1414 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_execlists_show_requests(engine, m, print_request, 8);
engine           1417 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	hexdump(m, engine->status_page.addr, PAGE_SIZE);
engine           1419 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
engine           1421 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_engine_print_breadcrumbs(engine, m);
engine           1432 drivers/gpu/drm/i915/gt/intel_engine_cs.c int intel_enable_engine_stats(struct intel_engine_cs *engine)
engine           1434 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	struct intel_engine_execlists *execlists = &engine->execlists;
engine           1438 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!intel_engine_supports_stats(engine))
engine           1442 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	write_seqlock_irqsave(&engine->stats.lock, flags);
engine           1444 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (unlikely(engine->stats.enabled == ~0)) {
engine           1449 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (engine->stats.enabled++ == 0) {
engine           1453 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		engine->stats.enabled_at = ktime_get();
engine           1457 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			engine->stats.active++;
engine           1462 drivers/gpu/drm/i915/gt/intel_engine_cs.c 				engine->stats.active++;
engine           1465 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		if (engine->stats.active)
engine           1466 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			engine->stats.start = engine->stats.enabled_at;
engine           1470 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	write_sequnlock_irqrestore(&engine->stats.lock, flags);
engine           1476 drivers/gpu/drm/i915/gt/intel_engine_cs.c static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
engine           1478 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	ktime_t total = engine->stats.total;
engine           1484 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (engine->stats.active)
engine           1486 drivers/gpu/drm/i915/gt/intel_engine_cs.c 				  ktime_sub(ktime_get(), engine->stats.start));
engine           1497 drivers/gpu/drm/i915/gt/intel_engine_cs.c ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
engine           1503 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		seq = read_seqbegin(&engine->stats.lock);
engine           1504 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		total = __intel_engine_get_busy_time(engine);
engine           1505 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	} while (read_seqretry(&engine->stats.lock, seq));
engine           1516 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_disable_engine_stats(struct intel_engine_cs *engine)
engine           1520 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (!intel_engine_supports_stats(engine))
engine           1523 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	write_seqlock_irqsave(&engine->stats.lock, flags);
engine           1524 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	WARN_ON_ONCE(engine->stats.enabled == 0);
engine           1525 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	if (--engine->stats.enabled == 0) {
engine           1526 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		engine->stats.total = __intel_engine_get_busy_time(engine);
engine           1527 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		engine->stats.active = 0;
engine           1529 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	write_sequnlock_irqrestore(&engine->stats.lock, flags);
engine           1534 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	u32 ring = ENGINE_READ(rq->engine, RING_START);
engine           1540 drivers/gpu/drm/i915/gt/intel_engine_cs.c intel_engine_find_active_request(struct intel_engine_cs *engine)
engine           1555 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	lockdep_assert_held(&engine->active.lock);
engine           1556 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	list_for_each_entry(request, &engine->active.requests, sched.link) {
engine             17 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	struct intel_engine_cs *engine =
engine             18 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		container_of(wf, typeof(*engine), wakeref);
engine             21 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	GEM_TRACE("%s\n", engine->name);
engine             23 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	intel_gt_pm_get(engine->gt);
engine             27 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (engine->default_state)
engine             28 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		map = i915_gem_object_pin_map(engine->default_state,
engine             31 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		engine->pinned_default_state = map;
engine             33 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (engine->unpark)
engine             34 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		engine->unpark(engine);
engine             36 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	intel_engine_init_hangcheck(engine);
engine             73 drivers/gpu/drm/i915/gt/intel_engine_pm.c static bool switch_to_kernel_context(struct intel_engine_cs *engine)
engine             80 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (engine->wakeref_serial == engine->serial)
engine             84 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (intel_gt_is_wedged(engine->gt))
engine             99 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	flags = __timeline_mark_lock(engine->kernel_context);
engine            101 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	rq = __i915_request_create(engine->kernel_context, GFP_NOWAIT);
engine            109 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	engine->wakeref_serial = engine->serial + 1;
engine            117 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	__intel_wakeref_defer_park(&engine->wakeref);
engine            122 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	__timeline_mark_unlock(engine->kernel_context, flags);
engine            128 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	struct intel_engine_cs *engine =
engine            129 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		container_of(wf, typeof(*engine), wakeref);
engine            131 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	engine->saturated = 0;
engine            140 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (!switch_to_kernel_context(engine))
engine            143 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	GEM_TRACE("%s\n", engine->name);
engine            145 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	intel_engine_disarm_breadcrumbs(engine);
engine            146 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	intel_engine_pool_park(&engine->pool);
engine            149 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN);
engine            151 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (engine->park)
engine            152 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		engine->park(engine);
engine            154 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	if (engine->pinned_default_state) {
engine            155 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		i915_gem_object_unpin_map(engine->default_state);
engine            156 drivers/gpu/drm/i915/gt/intel_engine_pm.c 		engine->pinned_default_state = NULL;
engine            159 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	engine->execlists.no_priolist = false;
engine            161 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	intel_gt_pm_put(engine->gt);
engine            170 drivers/gpu/drm/i915/gt/intel_engine_pm.c void intel_engine_init__pm(struct intel_engine_cs *engine)
engine            172 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	struct intel_runtime_pm *rpm = &engine->i915->runtime_pm;
engine            174 drivers/gpu/drm/i915/gt/intel_engine_pm.c 	intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
engine             14 drivers/gpu/drm/i915/gt/intel_engine_pm.h intel_engine_pm_is_awake(const struct intel_engine_cs *engine)
engine             16 drivers/gpu/drm/i915/gt/intel_engine_pm.h 	return intel_wakeref_is_active(&engine->wakeref);
engine             19 drivers/gpu/drm/i915/gt/intel_engine_pm.h static inline void intel_engine_pm_get(struct intel_engine_cs *engine)
engine             21 drivers/gpu/drm/i915/gt/intel_engine_pm.h 	intel_wakeref_get(&engine->wakeref);
engine             24 drivers/gpu/drm/i915/gt/intel_engine_pm.h static inline bool intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
engine             26 drivers/gpu/drm/i915/gt/intel_engine_pm.h 	return intel_wakeref_get_if_active(&engine->wakeref);
engine             29 drivers/gpu/drm/i915/gt/intel_engine_pm.h static inline void intel_engine_pm_put(struct intel_engine_cs *engine)
engine             31 drivers/gpu/drm/i915/gt/intel_engine_pm.h 	intel_wakeref_put(&engine->wakeref);
engine             34 drivers/gpu/drm/i915/gt/intel_engine_pm.h void intel_engine_init__pm(struct intel_engine_cs *engine);
engine             87 drivers/gpu/drm/i915/gt/intel_engine_pool.c 	struct intel_engine_cs *engine = to_engine(pool);
engine             97 drivers/gpu/drm/i915/gt/intel_engine_pool.c 	i915_active_init(engine->i915, &node->active, pool_active, pool_retire);
engine             99 drivers/gpu/drm/i915/gt/intel_engine_pool.c 	obj = i915_gem_object_create_internal(engine->i915, sz);
engine            405 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*irq_enable)(struct intel_engine_cs *engine);
engine            406 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*irq_disable)(struct intel_engine_cs *engine);
engine            408 drivers/gpu/drm/i915/gt/intel_engine_types.h 	int		(*resume)(struct intel_engine_cs *engine);
engine            411 drivers/gpu/drm/i915/gt/intel_engine_types.h 		void (*prepare)(struct intel_engine_cs *engine);
engine            412 drivers/gpu/drm/i915/gt/intel_engine_types.h 		void (*reset)(struct intel_engine_cs *engine, bool stalled);
engine            413 drivers/gpu/drm/i915/gt/intel_engine_types.h 		void (*finish)(struct intel_engine_cs *engine);
engine            416 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*park)(struct intel_engine_cs *engine);
engine            417 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*unpark)(struct intel_engine_cs *engine);
engine            419 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*set_default_submission)(struct intel_engine_cs *engine);
engine            468 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*cancel_requests)(struct intel_engine_cs *engine);
engine            470 drivers/gpu/drm/i915/gt/intel_engine_types.h 	void		(*destroy)(struct intel_engine_cs *engine);
engine            546 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_using_cmd_parser(const struct intel_engine_cs *engine)
engine            548 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_USING_CMD_PARSER;
engine            552 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine)
engine            554 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_REQUIRES_CMD_PARSER;
engine            558 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_supports_stats(const struct intel_engine_cs *engine)
engine            560 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_SUPPORTS_STATS;
engine            564 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_has_preemption(const struct intel_engine_cs *engine)
engine            566 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_HAS_PREEMPTION;
engine            570 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_has_semaphores(const struct intel_engine_cs *engine)
engine            572 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
engine            576 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
engine            578 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
engine            582 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_is_virtual(const struct intel_engine_cs *engine)
engine            584 drivers/gpu/drm/i915/gt/intel_engine_types.h 	return engine->flags & I915_ENGINE_IS_VIRTUAL;
engine             38 drivers/gpu/drm/i915/gt/intel_engine_user.c void intel_engine_add_user(struct intel_engine_cs *engine)
engine             40 drivers/gpu/drm/i915/gt/intel_engine_user.c 	llist_add((struct llist_node *)&engine->uabi_node,
engine             41 drivers/gpu/drm/i915/gt/intel_engine_user.c 		  (struct llist_head *)&engine->i915->uabi_engines);
engine             82 drivers/gpu/drm/i915/gt/intel_engine_user.c 		struct intel_engine_cs *engine =
engine             83 drivers/gpu/drm/i915/gt/intel_engine_user.c 			container_of((struct rb_node *)pos, typeof(*engine),
engine             85 drivers/gpu/drm/i915/gt/intel_engine_user.c 		list_add((struct list_head *)&engine->uabi_node, engines);
engine             93 drivers/gpu/drm/i915/gt/intel_engine_user.c 		u8 engine;
engine            102 drivers/gpu/drm/i915/gt/intel_engine_user.c 	struct intel_engine_cs *engine;
engine            107 drivers/gpu/drm/i915/gt/intel_engine_user.c 	for_each_uabi_engine(engine, i915) { /* all engines must agree! */
engine            110 drivers/gpu/drm/i915/gt/intel_engine_user.c 		if (engine->schedule)
engine            118 drivers/gpu/drm/i915/gt/intel_engine_user.c 			if (engine->flags & BIT(map[i].engine))
engine            172 drivers/gpu/drm/i915/gt/intel_engine_user.c 			    struct intel_engine_cs *engine)
engine            176 drivers/gpu/drm/i915/gt/intel_engine_user.c 	if (engine->gt != ring->gt || engine->class != ring->class) {
engine            177 drivers/gpu/drm/i915/gt/intel_engine_user.c 		ring->gt = engine->gt;
engine            178 drivers/gpu/drm/i915/gt/intel_engine_user.c 		ring->class = engine->class;
engine            186 drivers/gpu/drm/i915/gt/intel_engine_user.c 	GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
engine            187 drivers/gpu/drm/i915/gt/intel_engine_user.c 	ring->gt->engine[idx] = engine;
engine            190 drivers/gpu/drm/i915/gt/intel_engine_user.c 	engine->legacy_idx = idx;
engine            206 drivers/gpu/drm/i915/gt/intel_engine_user.c 		struct intel_engine_cs *engine =
engine            207 drivers/gpu/drm/i915/gt/intel_engine_user.c 			container_of((struct rb_node *)it, typeof(*engine),
engine            209 drivers/gpu/drm/i915/gt/intel_engine_user.c 		char old[sizeof(engine->name)];
engine            211 drivers/gpu/drm/i915/gt/intel_engine_user.c 		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
engine            212 drivers/gpu/drm/i915/gt/intel_engine_user.c 		engine->uabi_class = uabi_classes[engine->class];
engine            214 drivers/gpu/drm/i915/gt/intel_engine_user.c 		GEM_BUG_ON(engine->uabi_class >= ARRAY_SIZE(uabi_instances));
engine            215 drivers/gpu/drm/i915/gt/intel_engine_user.c 		engine->uabi_instance = uabi_instances[engine->uabi_class]++;
engine            218 drivers/gpu/drm/i915/gt/intel_engine_user.c 		memcpy(old, engine->name, sizeof(engine->name));
engine            219 drivers/gpu/drm/i915/gt/intel_engine_user.c 		scnprintf(engine->name, sizeof(engine->name), "%s%u",
engine            220 drivers/gpu/drm/i915/gt/intel_engine_user.c 			  intel_engine_class_repr(engine->class),
engine            221 drivers/gpu/drm/i915/gt/intel_engine_user.c 			  engine->uabi_instance);
engine            222 drivers/gpu/drm/i915/gt/intel_engine_user.c 		DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
engine            224 drivers/gpu/drm/i915/gt/intel_engine_user.c 		rb_link_node(&engine->uabi_node, prev, p);
engine            225 drivers/gpu/drm/i915/gt/intel_engine_user.c 		rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
engine            228 drivers/gpu/drm/i915/gt/intel_engine_user.c 						    engine->uabi_class,
engine            229 drivers/gpu/drm/i915/gt/intel_engine_user.c 						    engine->uabi_instance) != engine);
engine            232 drivers/gpu/drm/i915/gt/intel_engine_user.c 		add_legacy_ring(&ring, engine);
engine            234 drivers/gpu/drm/i915/gt/intel_engine_user.c 		prev = &engine->uabi_node;
engine            240 drivers/gpu/drm/i915/gt/intel_engine_user.c 		struct intel_engine_cs *engine;
engine            247 drivers/gpu/drm/i915/gt/intel_engine_user.c 				engine = intel_engine_lookup_user(i915,
engine            249 drivers/gpu/drm/i915/gt/intel_engine_user.c 				if (!engine) {
engine            256 drivers/gpu/drm/i915/gt/intel_engine_user.c 				if (engine->uabi_class != class ||
engine            257 drivers/gpu/drm/i915/gt/intel_engine_user.c 				    engine->uabi_instance != inst) {
engine            259 drivers/gpu/drm/i915/gt/intel_engine_user.c 					       engine->name,
engine            260 drivers/gpu/drm/i915/gt/intel_engine_user.c 					       engine->uabi_class,
engine            261 drivers/gpu/drm/i915/gt/intel_engine_user.c 					       engine->uabi_instance,
engine            274 drivers/gpu/drm/i915/gt/intel_engine_user.c 		for_each_uabi_engine(engine, i915) {
engine            275 drivers/gpu/drm/i915/gt/intel_engine_user.c 			unsigned int bit = BIT(engine->uabi_class);
engine            276 drivers/gpu/drm/i915/gt/intel_engine_user.c 			unsigned int expected = engine->default_state ? bit : 0;
engine            280 drivers/gpu/drm/i915/gt/intel_engine_user.c 				       engine->uabi_class, engine->name);
engine            294 drivers/gpu/drm/i915/gt/intel_engine_user.c 	struct intel_engine_cs *engine;
engine            298 drivers/gpu/drm/i915/gt/intel_engine_user.c 	for_each_uabi_engine(engine, i915)
engine            299 drivers/gpu/drm/i915/gt/intel_engine_user.c 		if (engine->default_state)
engine            300 drivers/gpu/drm/i915/gt/intel_engine_user.c 			which |= BIT(engine->uabi_class);
engine             20 drivers/gpu/drm/i915/gt/intel_engine_user.h void intel_engine_add_user(struct intel_engine_cs *engine);
engine            113 drivers/gpu/drm/i915/gt/intel_gpu_commands.h #define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
engine             47 drivers/gpu/drm/i915/gt/intel_gt.c static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
engine             49 drivers/gpu/drm/i915/gt/intel_gt.c 	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
engine             50 drivers/gpu/drm/i915/gt/intel_gt.c 	GEN6_RING_FAULT_REG_POSTING_READ(engine);
engine             89 drivers/gpu/drm/i915/gt/intel_gt.c 		struct intel_engine_cs *engine;
engine             92 drivers/gpu/drm/i915/gt/intel_gt.c 		for_each_engine_masked(engine, i915, engine_mask, id)
engine             93 drivers/gpu/drm/i915/gt/intel_gt.c 			gen8_clear_engine_error_register(engine);
engine             99 drivers/gpu/drm/i915/gt/intel_gt.c 	struct intel_engine_cs *engine;
engine            103 drivers/gpu/drm/i915/gt/intel_gt.c 	for_each_engine(engine, gt->i915, id) {
engine            104 drivers/gpu/drm/i915/gt/intel_gt.c 		fault = GEN6_RING_FAULT_REG_READ(engine);
engine             22 drivers/gpu/drm/i915/gt/intel_gt_irq.c cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
engine             30 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		intel_engine_breadcrumbs_irq(engine);
engine             31 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
engine             35 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		tasklet_hi_schedule(&engine->execlists.tasklet);
engine             90 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	struct intel_engine_cs *engine;
engine             93 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		engine = gt->engine_class[class][instance];
engine             95 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		engine = NULL;
engine             97 drivers/gpu/drm/i915/gt/intel_gt_irq.c 	if (likely(engine))
engine             98 drivers/gpu/drm/i915/gt/intel_gt_irq.c 		return cs_irq_handler(engine, iir);
engine            120 drivers/gpu/drm/i915/gt/intel_gt_pm.c 	struct intel_engine_cs *engine;
engine            130 drivers/gpu/drm/i915/gt/intel_gt_pm.c 	for_each_engine(engine, gt->i915, id)
engine            131 drivers/gpu/drm/i915/gt/intel_gt_pm.c 		__intel_engine_reset(engine, false);
engine            136 drivers/gpu/drm/i915/gt/intel_gt_pm.c 	struct intel_engine_cs *engine;
engine            147 drivers/gpu/drm/i915/gt/intel_gt_pm.c 	for_each_engine(engine, gt->i915, id) {
engine            150 drivers/gpu/drm/i915/gt/intel_gt_pm.c 		intel_engine_pm_get(engine);
engine            152 drivers/gpu/drm/i915/gt/intel_gt_pm.c 		ce = engine->kernel_context;
engine            156 drivers/gpu/drm/i915/gt/intel_gt_pm.c 		engine->serial++; /* kernel context lost */
engine            157 drivers/gpu/drm/i915/gt/intel_gt_pm.c 		err = engine->resume(engine);
engine            159 drivers/gpu/drm/i915/gt/intel_gt_pm.c 		intel_engine_pm_put(engine);
engine            163 drivers/gpu/drm/i915/gt/intel_gt_pm.c 				engine->name, err);
engine             82 drivers/gpu/drm/i915/gt/intel_gt_types.h 	struct intel_engine_cs *engine[I915_NUM_ENGINES];
engine             53 drivers/gpu/drm/i915/gt/intel_hangcheck.c static bool subunits_stuck(struct intel_engine_cs *engine)
engine             55 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	struct drm_i915_private *dev_priv = engine->i915;
engine             57 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
engine             62 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	intel_engine_get_instdone(engine, &instdone);
engine             85 drivers/gpu/drm/i915/gt/intel_hangcheck.c head_stuck(struct intel_engine_cs *engine, u64 acthd)
engine             87 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	if (acthd != engine->hangcheck.acthd) {
engine             90 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		memset(&engine->hangcheck.instdone, 0,
engine             91 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		       sizeof(engine->hangcheck.instdone));
engine             96 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	if (!subunits_stuck(engine))
engine            103 drivers/gpu/drm/i915/gt/intel_hangcheck.c engine_stuck(struct intel_engine_cs *engine, u64 acthd)
engine            108 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	ha = head_stuck(engine, acthd);
engine            112 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	if (IS_GEN(engine->i915, 2))
engine            120 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	tmp = ENGINE_READ(engine, RING_CTL);
engine            122 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		intel_gt_handle_error(engine->gt, engine->mask, 0,
engine            123 drivers/gpu/drm/i915/gt/intel_hangcheck.c 				      "stuck wait on %s", engine->name);
engine            124 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		ENGINE_WRITE(engine, RING_CTL, tmp);
engine            131 drivers/gpu/drm/i915/gt/intel_hangcheck.c static void hangcheck_load_sample(struct intel_engine_cs *engine,
engine            134 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	hc->acthd = intel_engine_get_active_head(engine);
engine            135 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	hc->ring = ENGINE_READ(engine, RING_START);
engine            136 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	hc->head = ENGINE_READ(engine, RING_HEAD);
engine            139 drivers/gpu/drm/i915/gt/intel_hangcheck.c static void hangcheck_store_sample(struct intel_engine_cs *engine,
engine            142 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	engine->hangcheck.acthd = hc->acthd;
engine            143 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	engine->hangcheck.last_ring = hc->ring;
engine            144 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	engine->hangcheck.last_head = hc->head;
engine            148 drivers/gpu/drm/i915/gt/intel_hangcheck.c hangcheck_get_action(struct intel_engine_cs *engine,
engine            151 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	if (intel_engine_is_idle(engine))
engine            154 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	if (engine->hangcheck.last_ring != hc->ring)
engine            157 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	if (engine->hangcheck.last_head != hc->head)
engine            160 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	return engine_stuck(engine, hc->acthd);
engine            163 drivers/gpu/drm/i915/gt/intel_hangcheck.c static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
engine            168 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	hc->action = hangcheck_get_action(engine, hc);
engine            191 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		memset(&engine->hangcheck.instdone, 0,
engine            192 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		       sizeof(engine->hangcheck.instdone));
engine            197 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		engine->hangcheck.action_timestamp = jiffies;
engine            217 drivers/gpu/drm/i915/gt/intel_hangcheck.c 				 engine->hangcheck.action_timestamp + timeout);
engine            219 drivers/gpu/drm/i915/gt/intel_hangcheck.c 				 engine->hangcheck.action_timestamp +
engine            227 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	struct intel_engine_cs *engine;
engine            239 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	for_each_engine_masked(engine, gt->i915, hung, tmp)
engine            241 drivers/gpu/drm/i915/gt/intel_hangcheck.c 				 "%s, ", engine->name);
engine            260 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	struct intel_engine_cs *engine;
engine            283 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine            286 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		intel_engine_signal_breadcrumbs(engine);
engine            288 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		hangcheck_load_sample(engine, &hc);
engine            289 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		hangcheck_accumulate_sample(engine, &hc);
engine            290 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		hangcheck_store_sample(engine, &hc);
engine            293 drivers/gpu/drm/i915/gt/intel_hangcheck.c 			hung |= engine->mask;
engine            295 drivers/gpu/drm/i915/gt/intel_hangcheck.c 				stuck |= engine->mask;
engine            299 drivers/gpu/drm/i915/gt/intel_hangcheck.c 			wedged |= engine->mask;
engine            305 drivers/gpu/drm/i915/gt/intel_hangcheck.c 		for_each_engine(engine, gt->i915, id) {
engine            306 drivers/gpu/drm/i915/gt/intel_hangcheck.c 			if (intel_engine_is_idle(engine))
engine            309 drivers/gpu/drm/i915/gt/intel_hangcheck.c 			intel_engine_dump(engine, &p, "%s\n", engine->name);
engine            347 drivers/gpu/drm/i915/gt/intel_hangcheck.c void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
engine            349 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
engine            350 drivers/gpu/drm/i915/gt/intel_hangcheck.c 	engine->hangcheck.action_timestamp = jiffies;
engine            223 drivers/gpu/drm/i915/gt/intel_lrc.c static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)
engine            225 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_BUG_ON(!intel_engine_is_virtual(engine));
engine            226 drivers/gpu/drm/i915/gt/intel_lrc.c 	return container_of(engine, struct virtual_engine, base);
engine            230 drivers/gpu/drm/i915/gt/intel_lrc.c 				     struct intel_engine_cs *engine);
engine            234 drivers/gpu/drm/i915/gt/intel_lrc.c 				     struct intel_engine_cs *engine,
engine            244 drivers/gpu/drm/i915/gt/intel_lrc.c static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
engine            246 drivers/gpu/drm/i915/gt/intel_lrc.c 	return (i915_ggtt_offset(engine->status_page.vma) +
engine            251 drivers/gpu/drm/i915/gt/intel_lrc.c ring_set_paused(const struct intel_engine_cs *engine, int state)
engine            259 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
engine            320 drivers/gpu/drm/i915/gt/intel_lrc.c static inline bool need_preempt(const struct intel_engine_cs *engine,
engine            326 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!intel_engine_has_semaphores(engine))
engine            342 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
engine            350 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!list_is_last(&rq->sched.link, &engine->active.requests) &&
engine            356 drivers/gpu/drm/i915/gt/intel_lrc.c 			rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
engine            359 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (engine == ve->siblings[0]) { /* only preempt one sibling */
engine            383 drivers/gpu/drm/i915/gt/intel_lrc.c 	return queue_prio(&engine->execlists) > last_prio;
engine            430 drivers/gpu/drm/i915/gt/intel_lrc.c lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
engine            444 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (IS_GEN(engine->i915, 8))
engine            454 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (INTEL_GEN(engine->i915) >= 11) {
engine            459 drivers/gpu/drm/i915/gt/intel_lrc.c 		desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
engine            464 drivers/gpu/drm/i915/gt/intel_lrc.c 		desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
engine            475 drivers/gpu/drm/i915/gt/intel_lrc.c __unwind_incomplete_requests(struct intel_engine_cs *engine)
engine            481 drivers/gpu/drm/i915/gt/intel_lrc.c 	lockdep_assert_held(&engine->active.lock);
engine            484 drivers/gpu/drm/i915/gt/intel_lrc.c 					 &engine->active.requests,
engine            500 drivers/gpu/drm/i915/gt/intel_lrc.c 		owner = rq->hw_context->engine;
engine            501 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (likely(owner == engine)) {
engine            505 drivers/gpu/drm/i915/gt/intel_lrc.c 				pl = i915_sched_lookup_priolist(engine, prio);
engine            507 drivers/gpu/drm/i915/gt/intel_lrc.c 			GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
engine            526 drivers/gpu/drm/i915/gt/intel_lrc.c 			rq->engine = owner;
engine            538 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs *engine =
engine            539 drivers/gpu/drm/i915/gt/intel_lrc.c 		container_of(execlists, typeof(*engine), execlists);
engine            541 drivers/gpu/drm/i915/gt/intel_lrc.c 	return __unwind_incomplete_requests(engine);
engine            554 drivers/gpu/drm/i915/gt/intel_lrc.c 	atomic_notifier_call_chain(&rq->engine->context_status_notifier,
engine            561 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs * const engine = rq->engine;
engine            566 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_gt_pm_get(engine->gt);
engine            568 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_context_in(engine);
engine            570 drivers/gpu/drm/i915/gt/intel_lrc.c 	return engine;
engine            579 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
engine            590 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
engine            605 drivers/gpu/drm/i915/gt/intel_lrc.c 			 struct intel_engine_cs * const engine)
engine            609 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_context_out(engine);
engine            611 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_gt_pm_put(engine->gt);
engine            622 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (ce->engine != engine)
engine            714 drivers/gpu/drm/i915/gt/intel_lrc.c 	const struct intel_engine_cs *engine =
engine            715 drivers/gpu/drm/i915/gt/intel_lrc.c 		container_of(execlists, typeof(*engine), execlists);
engine            718 drivers/gpu/drm/i915/gt/intel_lrc.c 		  engine->name, msg,
engine            761 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_submit_ports(struct intel_engine_cs *engine)
engine            763 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists *execlists = &engine->execlists;
engine            776 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
engine            839 drivers/gpu/drm/i915/gt/intel_lrc.c 					    struct intel_engine_cs *engine)
engine            841 drivers/gpu/drm/i915/gt/intel_lrc.c 	u32 base = engine->mmio_base;
engine            871 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (engine->class == RENDER_CLASS) {
engine            886 drivers/gpu/drm/i915/gt/intel_lrc.c 			    const struct intel_engine_cs *engine)
engine            890 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */
engine            903 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (inflight && inflight != engine)
engine            910 drivers/gpu/drm/i915/gt/intel_lrc.c 				     struct intel_engine_cs *engine)
engine            919 drivers/gpu/drm/i915/gt/intel_lrc.c 			       &engine->breadcrumbs.signalers);
engine            920 drivers/gpu/drm/i915/gt/intel_lrc.c 		intel_engine_queue_breadcrumbs(engine);
engine            963 drivers/gpu/drm/i915/gt/intel_lrc.c 			if (w->engine != rq->engine)
engine            985 drivers/gpu/drm/i915/gt/intel_lrc.c static void defer_active(struct intel_engine_cs *engine)
engine            989 drivers/gpu/drm/i915/gt/intel_lrc.c 	rq = __unwind_incomplete_requests(engine);
engine            993 drivers/gpu/drm/i915/gt/intel_lrc.c 	defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
engine            997 drivers/gpu/drm/i915/gt/intel_lrc.c need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
engine           1001 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!intel_engine_has_semaphores(engine))
engine           1004 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (list_is_last(&rq->sched.link, &engine->active.requests))
engine           1008 drivers/gpu/drm/i915/gt/intel_lrc.c 		   engine->execlists.queue_priority_hint);
engine           1014 drivers/gpu/drm/i915/gt/intel_lrc.c switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
engine           1016 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (list_is_last(&rq->sched.link, &engine->active.requests))
engine           1038 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_dequeue(struct intel_engine_cs *engine)
engine           1040 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           1071 drivers/gpu/drm/i915/gt/intel_lrc.c 			rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
engine           1081 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (!virtual_matches(ve, rq, engine)) {
engine           1099 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (need_preempt(engine, last, rb)) {
engine           1101 drivers/gpu/drm/i915/gt/intel_lrc.c 				  engine->name,
engine           1113 drivers/gpu/drm/i915/gt/intel_lrc.c 			ring_set_paused(engine, 1);
engine           1122 drivers/gpu/drm/i915/gt/intel_lrc.c 			__unwind_incomplete_requests(engine);
engine           1125 drivers/gpu/drm/i915/gt/intel_lrc.c 		} else if (need_timeslice(engine, last) &&
engine           1126 drivers/gpu/drm/i915/gt/intel_lrc.c 			   !timer_pending(&engine->execlists.timer)) {
engine           1128 drivers/gpu/drm/i915/gt/intel_lrc.c 				  engine->name,
engine           1134 drivers/gpu/drm/i915/gt/intel_lrc.c 			ring_set_paused(engine, 1);
engine           1135 drivers/gpu/drm/i915/gt/intel_lrc.c 			defer_active(engine);
engine           1162 drivers/gpu/drm/i915/gt/intel_lrc.c 					  &engine->active.requests))
engine           1169 drivers/gpu/drm/i915/gt/intel_lrc.c 			rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
engine           1184 drivers/gpu/drm/i915/gt/intel_lrc.c 		GEM_BUG_ON(rq->engine != &ve->base);
engine           1188 drivers/gpu/drm/i915/gt/intel_lrc.c 			if (!virtual_matches(ve, rq, engine)) {
engine           1200 drivers/gpu/drm/i915/gt/intel_lrc.c 				  engine->name,
engine           1206 drivers/gpu/drm/i915/gt/intel_lrc.c 				  yesno(engine != ve->siblings[0]));
engine           1213 drivers/gpu/drm/i915/gt/intel_lrc.c 			GEM_BUG_ON(!(rq->execution_mask & engine->mask));
engine           1214 drivers/gpu/drm/i915/gt/intel_lrc.c 			rq->engine = engine;
engine           1216 drivers/gpu/drm/i915/gt/intel_lrc.c 			if (engine != ve->siblings[0]) {
engine           1221 drivers/gpu/drm/i915/gt/intel_lrc.c 				virtual_update_register_offsets(regs, engine);
engine           1224 drivers/gpu/drm/i915/gt/intel_lrc.c 					virtual_xfer_breadcrumbs(ve, engine);
engine           1234 drivers/gpu/drm/i915/gt/intel_lrc.c 					if (ve->siblings[n] == engine) {
engine           1241 drivers/gpu/drm/i915/gt/intel_lrc.c 				GEM_BUG_ON(ve->siblings[0] != engine);
engine           1357 drivers/gpu/drm/i915/gt/intel_lrc.c 		  engine->name, execlists->queue_priority_hint,
engine           1364 drivers/gpu/drm/i915/gt/intel_lrc.c 			switch_prio(engine, *execlists->pending);
engine           1365 drivers/gpu/drm/i915/gt/intel_lrc.c 		execlists_submit_ports(engine);
engine           1367 drivers/gpu/drm/i915/gt/intel_lrc.c 		ring_set_paused(engine, 0);
engine           1486 drivers/gpu/drm/i915/gt/intel_lrc.c static void process_csb(struct intel_engine_cs *engine)
engine           1488 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           1493 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915));
engine           1507 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
engine           1546 drivers/gpu/drm/i915/gt/intel_lrc.c 			  engine->name, head,
engine           1549 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (INTEL_GEN(engine->i915) >= 12)
engine           1575 drivers/gpu/drm/i915/gt/intel_lrc.c 				ring_set_paused(engine, 0);
engine           1618 drivers/gpu/drm/i915/gt/intel_lrc.c static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
engine           1620 drivers/gpu/drm/i915/gt/intel_lrc.c 	lockdep_assert_held(&engine->active.lock);
engine           1621 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!engine->execlists.pending[0]) {
engine           1623 drivers/gpu/drm/i915/gt/intel_lrc.c 		execlists_dequeue(engine);
engine           1634 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
engine           1637 drivers/gpu/drm/i915/gt/intel_lrc.c 	process_csb(engine);
engine           1638 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!READ_ONCE(engine->execlists.pending[0])) {
engine           1639 drivers/gpu/drm/i915/gt/intel_lrc.c 		spin_lock_irqsave(&engine->active.lock, flags);
engine           1640 drivers/gpu/drm/i915/gt/intel_lrc.c 		__execlists_submission_tasklet(engine);
engine           1641 drivers/gpu/drm/i915/gt/intel_lrc.c 		spin_unlock_irqrestore(&engine->active.lock, flags);
engine           1647 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs *engine =
engine           1648 drivers/gpu/drm/i915/gt/intel_lrc.c 		from_timer(engine, timer, execlists.timer);
engine           1651 drivers/gpu/drm/i915/gt/intel_lrc.c 	tasklet_hi_schedule(&engine->execlists.tasklet);
engine           1654 drivers/gpu/drm/i915/gt/intel_lrc.c static void queue_request(struct intel_engine_cs *engine,
engine           1659 drivers/gpu/drm/i915/gt/intel_lrc.c 	list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
engine           1662 drivers/gpu/drm/i915/gt/intel_lrc.c static void __submit_queue_imm(struct intel_engine_cs *engine)
engine           1664 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           1670 drivers/gpu/drm/i915/gt/intel_lrc.c 		__execlists_submission_tasklet(engine);
engine           1675 drivers/gpu/drm/i915/gt/intel_lrc.c static void submit_queue(struct intel_engine_cs *engine,
engine           1678 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists *execlists = &engine->execlists;
engine           1684 drivers/gpu/drm/i915/gt/intel_lrc.c 	__submit_queue_imm(engine);
engine           1689 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs *engine = request->engine;
engine           1693 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine           1695 drivers/gpu/drm/i915/gt/intel_lrc.c 	queue_request(engine, &request->sched, rq_prio(request));
engine           1697 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
engine           1700 drivers/gpu/drm/i915/gt/intel_lrc.c 	submit_queue(engine, request);
engine           1702 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine           1726 drivers/gpu/drm/i915/gt/intel_lrc.c set_redzone(void *vaddr, const struct intel_engine_cs *engine)
engine           1732 drivers/gpu/drm/i915/gt/intel_lrc.c 	vaddr += engine->context_size;
engine           1738 drivers/gpu/drm/i915/gt/intel_lrc.c check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
engine           1744 drivers/gpu/drm/i915/gt/intel_lrc.c 	vaddr += engine->context_size;
engine           1747 drivers/gpu/drm/i915/gt/intel_lrc.c 		dev_err_once(engine->i915->drm.dev,
engine           1749 drivers/gpu/drm/i915/gt/intel_lrc.c 			     engine->name);
engine           1755 drivers/gpu/drm/i915/gt/intel_lrc.c 		      ce->engine);
engine           1764 drivers/gpu/drm/i915/gt/intel_lrc.c 			     struct intel_engine_cs *engine)
engine           1777 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (engine->class == RENDER_CLASS) {
engine           1779 drivers/gpu/drm/i915/gt/intel_lrc.c 			intel_sseu_make_rpcs(engine->i915, &ce->sseu);
engine           1781 drivers/gpu/drm/i915/gt/intel_lrc.c 		i915_oa_init_reg_state(engine, ce, regs);
engine           1787 drivers/gpu/drm/i915/gt/intel_lrc.c 			struct intel_engine_cs *engine)
engine           1800 drivers/gpu/drm/i915/gt/intel_lrc.c 					i915_coherent_map_type(engine->i915) |
engine           1811 drivers/gpu/drm/i915/gt/intel_lrc.c 	ce->lrc_desc = lrc_descriptor(ce, engine);
engine           1813 drivers/gpu/drm/i915/gt/intel_lrc.c 	__execlists_update_reg_state(ce, engine);
engine           1827 drivers/gpu/drm/i915/gt/intel_lrc.c 	return __execlists_context_pin(ce, ce->engine);
engine           1832 drivers/gpu/drm/i915/gt/intel_lrc.c 	return __execlists_context_alloc(ce, ce->engine);
engine           1854 drivers/gpu/drm/i915/gt/intel_lrc.c 	__execlists_update_reg_state(ce, ce->engine);
engine           1904 drivers/gpu/drm/i915/gt/intel_lrc.c 	const struct intel_engine_cs * const engine = rq->engine;
engine           1919 drivers/gpu/drm/i915/gt/intel_lrc.c 	err = engine->emit_flush(rq, EMIT_FLUSH);
engine           1924 drivers/gpu/drm/i915/gt/intel_lrc.c 	err = engine->emit_flush(rq, EMIT_INVALIDATE);
engine           1936 drivers/gpu/drm/i915/gt/intel_lrc.c 		u32 base = engine->mmio_base;
engine           1948 drivers/gpu/drm/i915/gt/intel_lrc.c 	err = engine->emit_flush(rq, EMIT_FLUSH);
engine           1953 drivers/gpu/drm/i915/gt/intel_lrc.c 	return engine->emit_flush(rq, EMIT_INVALIDATE);
engine           1979 drivers/gpu/drm/i915/gt/intel_lrc.c 		ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
engine           2006 drivers/gpu/drm/i915/gt/intel_lrc.c gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
engine           2011 drivers/gpu/drm/i915/gt/intel_lrc.c 	*batch++ = intel_gt_scratch_offset(engine->gt,
engine           2026 drivers/gpu/drm/i915/gt/intel_lrc.c 	*batch++ = intel_gt_scratch_offset(engine->gt,
engine           2033 drivers/gpu/drm/i915/gt/intel_lrc.c static u32 slm_offset(struct intel_engine_cs *engine)
engine           2035 drivers/gpu/drm/i915/gt/intel_lrc.c 	return intel_gt_scratch_offset(engine->gt,
engine           2054 drivers/gpu/drm/i915/gt/intel_lrc.c static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
engine           2060 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (IS_BROADWELL(engine->i915))
engine           2061 drivers/gpu/drm/i915/gt/intel_lrc.c 		batch = gen8_emit_flush_coherentl3_wa(engine, batch);
engine           2070 drivers/gpu/drm/i915/gt/intel_lrc.c 				       slm_offset(engine));
engine           2106 drivers/gpu/drm/i915/gt/intel_lrc.c static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
engine           2134 drivers/gpu/drm/i915/gt/intel_lrc.c 	batch = gen8_emit_flush_coherentl3_wa(engine, batch);
engine           2142 drivers/gpu/drm/i915/gt/intel_lrc.c 				       slm_offset(engine));
engine           2147 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (HAS_POOLED_EU(engine->i915)) {
engine           2179 drivers/gpu/drm/i915/gt/intel_lrc.c gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
engine           2214 drivers/gpu/drm/i915/gt/intel_lrc.c static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
engine           2220 drivers/gpu/drm/i915/gt/intel_lrc.c 	obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_OBJ_SIZE);
engine           2224 drivers/gpu/drm/i915/gt/intel_lrc.c 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
engine           2234 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->wa_ctx.vma = vma;
engine           2242 drivers/gpu/drm/i915/gt/intel_lrc.c static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
engine           2244 drivers/gpu/drm/i915/gt/intel_lrc.c 	i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
engine           2247 drivers/gpu/drm/i915/gt/intel_lrc.c typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
engine           2249 drivers/gpu/drm/i915/gt/intel_lrc.c static int intel_init_workaround_bb(struct intel_engine_cs *engine)
engine           2251 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
engine           2260 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (engine->class != RENDER_CLASS)
engine           2263 drivers/gpu/drm/i915/gt/intel_lrc.c 	switch (INTEL_GEN(engine->i915)) {
engine           2280 drivers/gpu/drm/i915/gt/intel_lrc.c 		MISSING_CASE(INTEL_GEN(engine->i915));
engine           2284 drivers/gpu/drm/i915/gt/intel_lrc.c 	ret = lrc_setup_wa_ctx(engine);
engine           2306 drivers/gpu/drm/i915/gt/intel_lrc.c 			batch_ptr = wa_bb_fn[i](engine, batch_ptr);
engine           2314 drivers/gpu/drm/i915/gt/intel_lrc.c 		lrc_destroy_wa_ctx(engine);
engine           2319 drivers/gpu/drm/i915/gt/intel_lrc.c static void enable_execlists(struct intel_engine_cs *engine)
engine           2323 drivers/gpu/drm/i915/gt/intel_lrc.c 	assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
engine           2325 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
engine           2327 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (INTEL_GEN(engine->i915) >= 11)
engine           2331 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
engine           2333 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
engine           2335 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_WRITE_FW(engine,
engine           2337 drivers/gpu/drm/i915/gt/intel_lrc.c 			i915_ggtt_offset(engine->status_page.vma));
engine           2338 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_POSTING_READ(engine, RING_HWS_PGA);
engine           2341 drivers/gpu/drm/i915/gt/intel_lrc.c static bool unexpected_starting_state(struct intel_engine_cs *engine)
engine           2345 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
engine           2353 drivers/gpu/drm/i915/gt/intel_lrc.c static int execlists_resume(struct intel_engine_cs *engine)
engine           2355 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_apply_workarounds(engine);
engine           2356 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_apply_whitelist(engine);
engine           2358 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_mocs_init_engine(engine);
engine           2360 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_reset_breadcrumbs(engine);
engine           2362 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
engine           2365 drivers/gpu/drm/i915/gt/intel_lrc.c 		intel_engine_dump(engine, &p, NULL);
engine           2368 drivers/gpu/drm/i915/gt/intel_lrc.c 	enable_execlists(engine);
engine           2373 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_reset_prepare(struct intel_engine_cs *engine)
engine           2375 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           2378 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_TRACE("%s: depth<-%d\n", engine->name,
engine           2394 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine           2395 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine           2409 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_stop_cs(engine);
engine           2412 drivers/gpu/drm/i915/gt/intel_lrc.c static void reset_csb_pointers(struct intel_engine_cs *engine)
engine           2414 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           2417 drivers/gpu/drm/i915/gt/intel_lrc.c 	ring_set_paused(engine, 0);
engine           2459 drivers/gpu/drm/i915/gt/intel_lrc.c static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
engine           2461 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           2466 drivers/gpu/drm/i915/gt/intel_lrc.c 	process_csb(engine); /* drain preemption events */
engine           2469 drivers/gpu/drm/i915/gt/intel_lrc.c 	reset_csb_pointers(engine);
engine           2530 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (engine->pinned_default_state) {
engine           2532 drivers/gpu/drm/i915/gt/intel_lrc.c 		       engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
engine           2533 drivers/gpu/drm/i915/gt/intel_lrc.c 		       engine->context_size - PAGE_SIZE);
engine           2535 drivers/gpu/drm/i915/gt/intel_lrc.c 	execlists_init_reg_state(regs, ce, engine, ce->ring);
engine           2539 drivers/gpu/drm/i915/gt/intel_lrc.c 		  engine->name, ce->ring->head, ce->ring->tail);
engine           2541 drivers/gpu/drm/i915/gt/intel_lrc.c 	__execlists_update_reg_state(ce, engine);
engine           2546 drivers/gpu/drm/i915/gt/intel_lrc.c 	__unwind_incomplete_requests(engine);
engine           2549 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
engine           2553 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_TRACE("%s\n", engine->name);
engine           2555 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine           2557 drivers/gpu/drm/i915/gt/intel_lrc.c 	__execlists_reset(engine, stalled);
engine           2559 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine           2567 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_cancel_requests(struct intel_engine_cs *engine)
engine           2569 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           2574 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_TRACE("%s\n", engine->name);
engine           2590 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine           2592 drivers/gpu/drm/i915/gt/intel_lrc.c 	__execlists_reset(engine, true);
engine           2595 drivers/gpu/drm/i915/gt/intel_lrc.c 	list_for_each_entry(rq, &engine->active.requests, sched.link)
engine           2615 drivers/gpu/drm/i915/gt/intel_lrc.c 			rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
engine           2625 drivers/gpu/drm/i915/gt/intel_lrc.c 			rq->engine = engine;
engine           2642 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine           2645 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_reset_finish(struct intel_engine_cs *engine)
engine           2647 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           2661 drivers/gpu/drm/i915/gt/intel_lrc.c 	GEM_TRACE("%s: depth->%d\n", engine->name,
engine           2726 drivers/gpu/drm/i915/gt/intel_lrc.c static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
engine           2728 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_WRITE(engine, RING_IMR,
engine           2729 drivers/gpu/drm/i915/gt/intel_lrc.c 		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
engine           2730 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_POSTING_READ(engine, RING_IMR);
engine           2733 drivers/gpu/drm/i915/gt/intel_lrc.c static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
engine           2735 drivers/gpu/drm/i915/gt/intel_lrc.c 	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
engine           2757 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (request->engine->class == VIDEO_DECODE_CLASS)
engine           2773 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs *engine = request->engine;
engine           2775 drivers/gpu/drm/i915/gt/intel_lrc.c 		intel_gt_scratch_offset(engine->gt,
engine           2844 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_cs *engine = request->engine;
engine           2846 drivers/gpu/drm/i915/gt/intel_lrc.c 		intel_gt_scratch_offset(engine->gt,
engine           2920 drivers/gpu/drm/i915/gt/intel_lrc.c 	*cs++ = intel_hws_preempt_address(request->engine);
engine           2933 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (intel_engine_has_semaphores(request->engine))
engine           2986 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_park(struct intel_engine_cs *engine)
engine           2988 drivers/gpu/drm/i915/gt/intel_lrc.c 	del_timer(&engine->execlists.timer);
engine           2991 drivers/gpu/drm/i915/gt/intel_lrc.c void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
engine           2993 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->submit_request = execlists_submit_request;
engine           2994 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->cancel_requests = execlists_cancel_requests;
engine           2995 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->schedule = i915_schedule;
engine           2996 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->execlists.tasklet.func = execlists_submission_tasklet;
engine           2998 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->reset.prepare = execlists_reset_prepare;
engine           2999 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->reset.reset = execlists_reset;
engine           3000 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->reset.finish = execlists_reset_finish;
engine           3002 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->park = execlists_park;
engine           3003 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->unpark = NULL;
engine           3005 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->flags |= I915_ENGINE_SUPPORTS_STATS;
engine           3006 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!intel_vgpu_active(engine->i915)) {
engine           3007 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
engine           3008 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine           3009 drivers/gpu/drm/i915/gt/intel_lrc.c 			engine->flags |= I915_ENGINE_HAS_PREEMPTION;
engine           3013 drivers/gpu/drm/i915/gt/intel_lrc.c static void execlists_destroy(struct intel_engine_cs *engine)
engine           3015 drivers/gpu/drm/i915/gt/intel_lrc.c 	intel_engine_cleanup_common(engine);
engine           3016 drivers/gpu/drm/i915/gt/intel_lrc.c 	lrc_destroy_wa_ctx(engine);
engine           3017 drivers/gpu/drm/i915/gt/intel_lrc.c 	kfree(engine);
engine           3021 drivers/gpu/drm/i915/gt/intel_lrc.c logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine           3025 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->destroy = execlists_destroy;
engine           3026 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->resume = execlists_resume;
engine           3028 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->reset.prepare = execlists_reset_prepare;
engine           3029 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->reset.reset = execlists_reset;
engine           3030 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->reset.finish = execlists_reset_finish;
engine           3032 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->cops = &execlists_context_ops;
engine           3033 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->request_alloc = execlists_request_alloc;
engine           3035 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->emit_flush = gen8_emit_flush;
engine           3036 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine           3037 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
engine           3039 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->set_default_submission = intel_execlists_set_default_submission;
engine           3041 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (INTEL_GEN(engine->i915) < 11) {
engine           3042 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->irq_enable = gen8_logical_ring_enable_irq;
engine           3043 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->irq_disable = gen8_logical_ring_disable_irq;
engine           3052 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (IS_GEN(engine->i915, 8))
engine           3053 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->emit_bb_start = gen8_emit_bb_start;
engine           3055 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->emit_bb_start = gen9_emit_bb_start;
engine           3059 drivers/gpu/drm/i915/gt/intel_lrc.c logical_ring_default_irqs(struct intel_engine_cs *engine)
engine           3063 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (INTEL_GEN(engine->i915) < 11) {
engine           3072 drivers/gpu/drm/i915/gt/intel_lrc.c 		shift = irq_shifts[engine->id];
engine           3075 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
engine           3076 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
engine           3079 drivers/gpu/drm/i915/gt/intel_lrc.c static void rcs_submission_override(struct intel_engine_cs *engine)
engine           3081 drivers/gpu/drm/i915/gt/intel_lrc.c 	switch (INTEL_GEN(engine->i915)) {
engine           3084 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->emit_flush = gen11_emit_flush_render;
engine           3085 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->emit_fini_breadcrumb = gen11_emit_fini_breadcrumb_rcs;
engine           3088 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->emit_flush = gen8_emit_flush_render;
engine           3089 drivers/gpu/drm/i915/gt/intel_lrc.c 		engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
engine           3094 drivers/gpu/drm/i915/gt/intel_lrc.c int intel_execlists_submission_setup(struct intel_engine_cs *engine)
engine           3096 drivers/gpu/drm/i915/gt/intel_lrc.c 	tasklet_init(&engine->execlists.tasklet,
engine           3097 drivers/gpu/drm/i915/gt/intel_lrc.c 		     execlists_submission_tasklet, (unsigned long)engine);
engine           3098 drivers/gpu/drm/i915/gt/intel_lrc.c 	timer_setup(&engine->execlists.timer, execlists_submission_timer, 0);
engine           3100 drivers/gpu/drm/i915/gt/intel_lrc.c 	logical_ring_default_vfuncs(engine);
engine           3101 drivers/gpu/drm/i915/gt/intel_lrc.c 	logical_ring_default_irqs(engine);
engine           3103 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (engine->class == RENDER_CLASS)
engine           3104 drivers/gpu/drm/i915/gt/intel_lrc.c 		rcs_submission_override(engine);
engine           3109 drivers/gpu/drm/i915/gt/intel_lrc.c int intel_execlists_submission_init(struct intel_engine_cs *engine)
engine           3111 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine           3112 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct drm_i915_private *i915 = engine->i915;
engine           3113 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct intel_uncore *uncore = engine->uncore;
engine           3114 drivers/gpu/drm/i915/gt/intel_lrc.c 	u32 base = engine->mmio_base;
engine           3117 drivers/gpu/drm/i915/gt/intel_lrc.c 	ret = intel_engine_init_common(engine);
engine           3121 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (intel_init_workaround_bb(engine))
engine           3140 drivers/gpu/drm/i915/gt/intel_lrc.c 		&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
engine           3143 drivers/gpu/drm/i915/gt/intel_lrc.c 		&engine->status_page.addr[intel_hws_csb_write_index(i915)];
engine           3150 drivers/gpu/drm/i915/gt/intel_lrc.c 	reset_csb_pointers(engine);
engine           3155 drivers/gpu/drm/i915/gt/intel_lrc.c static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
engine           3159 drivers/gpu/drm/i915/gt/intel_lrc.c 	switch (INTEL_GEN(engine->i915)) {
engine           3161 drivers/gpu/drm/i915/gt/intel_lrc.c 		MISSING_CASE(INTEL_GEN(engine->i915));
engine           3190 drivers/gpu/drm/i915/gt/intel_lrc.c 				     struct intel_engine_cs *engine,
engine           3194 drivers/gpu/drm/i915/gt/intel_lrc.c 	bool rcs = engine->class == RENDER_CLASS;
engine           3195 drivers/gpu/drm/i915/gt/intel_lrc.c 	u32 base = engine->mmio_base;
engine           3213 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (INTEL_GEN(engine->i915) < 11) {
engine           3230 drivers/gpu/drm/i915/gt/intel_lrc.c 		struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
engine           3243 drivers/gpu/drm/i915/gt/intel_lrc.c 				intel_lr_indirect_ctx_offset(engine) << 6;
engine           3287 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (INTEL_GEN(engine->i915) >= 10)
engine           3294 drivers/gpu/drm/i915/gt/intel_lrc.c 		    struct intel_engine_cs *engine,
engine           3308 drivers/gpu/drm/i915/gt/intel_lrc.c 	set_redzone(vaddr, engine);
engine           3310 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (engine->default_state) {
engine           3319 drivers/gpu/drm/i915/gt/intel_lrc.c 		defaults = i915_gem_object_pin_map(engine->default_state,
engine           3326 drivers/gpu/drm/i915/gt/intel_lrc.c 		memcpy(vaddr + start, defaults + start, engine->context_size);
engine           3327 drivers/gpu/drm/i915/gt/intel_lrc.c 		i915_gem_object_unpin_map(engine->default_state);
engine           3333 drivers/gpu/drm/i915/gt/intel_lrc.c 	execlists_init_reg_state(regs, ce, engine, ring);
engine           3334 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (!engine->default_state)
engine           3342 drivers/gpu/drm/i915/gt/intel_lrc.c 				    engine->context_size);
engine           3348 drivers/gpu/drm/i915/gt/intel_lrc.c 				     struct intel_engine_cs *engine)
engine           3357 drivers/gpu/drm/i915/gt/intel_lrc.c 	context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
engine           3367 drivers/gpu/drm/i915/gt/intel_lrc.c 	ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
engine           3371 drivers/gpu/drm/i915/gt/intel_lrc.c 	vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
engine           3380 drivers/gpu/drm/i915/gt/intel_lrc.c 		tl = intel_timeline_create(engine->gt, NULL);
engine           3389 drivers/gpu/drm/i915/gt/intel_lrc.c 	ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
engine           3395 drivers/gpu/drm/i915/gt/intel_lrc.c 	ret = populate_lr_context(ce, ctx_obj, engine, ring);
engine           3632 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct virtual_engine *ve = to_virtual_engine(rq->engine);
engine           3687 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct virtual_engine *ve = to_virtual_engine(rq->engine);
engine           3691 drivers/gpu/drm/i915/gt/intel_lrc.c 	allowed = ~to_request(signal)->engine->mask;
engine           3693 drivers/gpu/drm/i915/gt/intel_lrc.c 	bond = virtual_find_bond(ve, to_request(signal)->engine);
engine           3862 drivers/gpu/drm/i915/gt/intel_lrc.c 		struct virtual_engine *de = to_virtual_engine(dst->engine);
engine           3878 drivers/gpu/drm/i915/gt/intel_lrc.c int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
engine           3882 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct virtual_engine *ve = to_virtual_engine(engine);
engine           3914 drivers/gpu/drm/i915/gt/intel_lrc.c void intel_execlists_show_requests(struct intel_engine_cs *engine,
engine           3921 drivers/gpu/drm/i915/gt/intel_lrc.c 	const struct intel_engine_execlists *execlists = &engine->execlists;
engine           3927 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine           3931 drivers/gpu/drm/i915/gt/intel_lrc.c 	list_for_each_entry(rq, &engine->active.requests, sched.link) {
engine           3975 drivers/gpu/drm/i915/gt/intel_lrc.c 			rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
engine           3994 drivers/gpu/drm/i915/gt/intel_lrc.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine           3997 drivers/gpu/drm/i915/gt/intel_lrc.c void intel_lr_context_reset(struct intel_engine_cs *engine,
engine           4013 drivers/gpu/drm/i915/gt/intel_lrc.c 		if (engine->pinned_default_state) {
engine           4015 drivers/gpu/drm/i915/gt/intel_lrc.c 			       engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
engine           4016 drivers/gpu/drm/i915/gt/intel_lrc.c 			       engine->context_size - PAGE_SIZE);
engine           4018 drivers/gpu/drm/i915/gt/intel_lrc.c 		execlists_init_reg_state(regs, ce, engine, ce->ring);
engine           4025 drivers/gpu/drm/i915/gt/intel_lrc.c 	__execlists_update_reg_state(ce, engine);
engine             76 drivers/gpu/drm/i915/gt/intel_lrc.h void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
engine             78 drivers/gpu/drm/i915/gt/intel_lrc.h int intel_execlists_submission_setup(struct intel_engine_cs *engine);
engine             79 drivers/gpu/drm/i915/gt/intel_lrc.h int intel_execlists_submission_init(struct intel_engine_cs *engine);
engine            107 drivers/gpu/drm/i915/gt/intel_lrc.h void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
engine            109 drivers/gpu/drm/i915/gt/intel_lrc.h void intel_lr_context_reset(struct intel_engine_cs *engine,
engine            114 drivers/gpu/drm/i915/gt/intel_lrc.h void intel_execlists_show_requests(struct intel_engine_cs *engine,
engine            130 drivers/gpu/drm/i915/gt/intel_lrc.h int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine,
engine            367 drivers/gpu/drm/i915/gt/intel_mocs.c void intel_mocs_init_engine(struct intel_engine_cs *engine)
engine            369 drivers/gpu/drm/i915/gt/intel_mocs.c 	struct intel_gt *gt = engine->gt;
engine            392 drivers/gpu/drm/i915/gt/intel_mocs.c 				      mocs_register(engine->id, index),
engine            399 drivers/gpu/drm/i915/gt/intel_mocs.c 				      mocs_register(engine->id, index),
engine            436 drivers/gpu/drm/i915/gt/intel_mocs.c 	enum intel_engine_id engine = rq->engine->id;
engine            456 drivers/gpu/drm/i915/gt/intel_mocs.c 		*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
engine            462 drivers/gpu/drm/i915/gt/intel_mocs.c 		*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
engine            602 drivers/gpu/drm/i915/gt/intel_mocs.c 	    rq->engine->class != RENDER_CLASS)
engine            605 drivers/gpu/drm/i915/gt/intel_mocs.c 	if (get_mocs_settings(rq->engine->gt, &t)) {
engine             57 drivers/gpu/drm/i915/gt/intel_mocs.h void intel_mocs_init_engine(struct intel_engine_cs *engine);
engine             42 drivers/gpu/drm/i915/gt/intel_renderstate.c render_state_get_rodata(const struct intel_engine_cs *engine)
engine             44 drivers/gpu/drm/i915/gt/intel_renderstate.c 	if (engine->class != RENDER_CLASS)
engine             47 drivers/gpu/drm/i915/gt/intel_renderstate.c 	switch (INTEL_GEN(engine->i915)) {
engine            181 drivers/gpu/drm/i915/gt/intel_renderstate.c 	struct intel_engine_cs *engine = rq->engine;
engine            185 drivers/gpu/drm/i915/gt/intel_renderstate.c 	so.rodata = render_state_get_rodata(engine);
engine            192 drivers/gpu/drm/i915/gt/intel_renderstate.c 	so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
engine            196 drivers/gpu/drm/i915/gt/intel_renderstate.c 	so.vma = i915_vma_instance(so.obj, &engine->gt->ggtt->vm, NULL);
engine            210 drivers/gpu/drm/i915/gt/intel_renderstate.c 	err = engine->emit_bb_start(rq,
engine            217 drivers/gpu/drm/i915/gt/intel_renderstate.c 		err = engine->emit_bb_start(rq,
engine             42 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine = rq->engine;
engine             48 drivers/gpu/drm/i915/gt/intel_reset.c 	lockdep_assert_held(&engine->active.lock);
engine             49 drivers/gpu/drm/i915/gt/intel_reset.c 	list_for_each_entry_continue(rq, &engine->active.requests, sched.link)
engine            120 drivers/gpu/drm/i915/gt/intel_reset.c 		  rq->engine->name,
engine            285 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            301 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine            302 drivers/gpu/drm/i915/gt/intel_reset.c 			GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
engine            303 drivers/gpu/drm/i915/gt/intel_reset.c 			hw_mask |= hw_engine_mask[engine->id];
engine            310 drivers/gpu/drm/i915/gt/intel_reset.c static u32 gen11_lock_sfc(struct intel_engine_cs *engine)
engine            312 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_uncore *uncore = engine->uncore;
engine            313 drivers/gpu/drm/i915/gt/intel_reset.c 	u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
engine            320 drivers/gpu/drm/i915/gt/intel_reset.c 	switch (engine->class) {
engine            322 drivers/gpu/drm/i915/gt/intel_reset.c 		if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
engine            325 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
engine            328 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
engine            331 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
engine            333 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
engine            337 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
engine            340 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
engine            343 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_usage = GEN11_VECS_SFC_USAGE(engine);
engine            345 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
engine            377 drivers/gpu/drm/i915/gt/intel_reset.c static void gen11_unlock_sfc(struct intel_engine_cs *engine)
engine            379 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_uncore *uncore = engine->uncore;
engine            380 drivers/gpu/drm/i915/gt/intel_reset.c 	u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access;
engine            384 drivers/gpu/drm/i915/gt/intel_reset.c 	switch (engine->class) {
engine            386 drivers/gpu/drm/i915/gt/intel_reset.c 		if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
engine            389 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
engine            394 drivers/gpu/drm/i915/gt/intel_reset.c 		sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
engine            419 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            428 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine            429 drivers/gpu/drm/i915/gt/intel_reset.c 			GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
engine            430 drivers/gpu/drm/i915/gt/intel_reset.c 			hw_mask |= hw_engine_mask[engine->id];
engine            431 drivers/gpu/drm/i915/gt/intel_reset.c 			hw_mask |= gen11_lock_sfc(engine);
engine            438 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
engine            439 drivers/gpu/drm/i915/gt/intel_reset.c 			gen11_unlock_sfc(engine);
engine            444 drivers/gpu/drm/i915/gt/intel_reset.c static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
engine            446 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_uncore *uncore = engine->uncore;
engine            447 drivers/gpu/drm/i915/gt/intel_reset.c 	const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
engine            475 drivers/gpu/drm/i915/gt/intel_reset.c 			  engine->name, request,
engine            481 drivers/gpu/drm/i915/gt/intel_reset.c static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
engine            483 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_uncore_write_fw(engine->uncore,
engine            484 drivers/gpu/drm/i915/gt/intel_reset.c 			      RING_RESET_CTL(engine->mmio_base),
engine            492 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            497 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine            498 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = gen8_engine_reset_prepare(engine);
engine            523 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
engine            524 drivers/gpu/drm/i915/gt/intel_reset.c 		gen8_engine_reset_cancel(engine);
engine            610 drivers/gpu/drm/i915/gt/intel_reset.c static void reset_prepare_engine(struct intel_engine_cs *engine)
engine            619 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
engine            620 drivers/gpu/drm/i915/gt/intel_reset.c 	engine->reset.prepare(engine);
engine            651 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            655 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, id) {
engine            656 drivers/gpu/drm/i915/gt/intel_reset.c 		if (intel_engine_pm_get_if_awake(engine))
engine            657 drivers/gpu/drm/i915/gt/intel_reset.c 			awake |= engine->mask;
engine            658 drivers/gpu/drm/i915/gt/intel_reset.c 		reset_prepare_engine(engine);
engine            673 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            685 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, id)
engine            686 drivers/gpu/drm/i915/gt/intel_reset.c 		__intel_engine_reset(engine, stalled_mask & engine->mask);
engine            693 drivers/gpu/drm/i915/gt/intel_reset.c static void reset_finish_engine(struct intel_engine_cs *engine)
engine            695 drivers/gpu/drm/i915/gt/intel_reset.c 	engine->reset.finish(engine);
engine            696 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
engine            698 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_engine_signal_breadcrumbs(engine);
engine            703 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            706 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, id) {
engine            707 drivers/gpu/drm/i915/gt/intel_reset.c 		reset_finish_engine(engine);
engine            708 drivers/gpu/drm/i915/gt/intel_reset.c 		if (awake & engine->mask)
engine            709 drivers/gpu/drm/i915/gt/intel_reset.c 			intel_engine_pm_put(engine);
engine            715 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine = request->engine;
engine            719 drivers/gpu/drm/i915/gt/intel_reset.c 		  engine->name, request->fence.context, request->fence.seqno);
engine            722 drivers/gpu/drm/i915/gt/intel_reset.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            725 drivers/gpu/drm/i915/gt/intel_reset.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            727 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_engine_queue_breadcrumbs(engine);
engine            732 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            742 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine(engine, gt->i915, id)
engine            743 drivers/gpu/drm/i915/gt/intel_reset.c 			intel_engine_dump(engine, &p, "%s\n", engine->name);
engine            759 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, id)
engine            760 drivers/gpu/drm/i915/gt/intel_reset.c 		engine->submit_request = nop_submit_request;
engine            771 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, id)
engine            772 drivers/gpu/drm/i915/gt/intel_reset.c 		engine->cancel_requests(engine);
engine            890 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine            894 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, id) {
engine            895 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = engine->resume(engine);
engine           1011 drivers/gpu/drm/i915/gt/intel_reset.c static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
engine           1013 drivers/gpu/drm/i915/gt/intel_reset.c 	return __intel_gt_reset(engine->gt, engine->mask);
engine           1029 drivers/gpu/drm/i915/gt/intel_reset.c int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
engine           1031 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_gt *gt = engine->gt;
engine           1034 drivers/gpu/drm/i915/gt/intel_reset.c 	GEM_TRACE("%s flags=%lx\n", engine->name, gt->reset.flags);
engine           1035 drivers/gpu/drm/i915/gt/intel_reset.c 	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
engine           1037 drivers/gpu/drm/i915/gt/intel_reset.c 	if (!intel_engine_pm_get_if_awake(engine))
engine           1040 drivers/gpu/drm/i915/gt/intel_reset.c 	reset_prepare_engine(engine);
engine           1043 drivers/gpu/drm/i915/gt/intel_reset.c 		dev_notice(engine->i915->drm.dev,
engine           1044 drivers/gpu/drm/i915/gt/intel_reset.c 			   "Resetting %s for %s\n", engine->name, msg);
engine           1045 drivers/gpu/drm/i915/gt/intel_reset.c 	atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
engine           1047 drivers/gpu/drm/i915/gt/intel_reset.c 	if (!engine->gt->uc.guc.execbuf_client)
engine           1048 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = intel_gt_reset_engine(engine);
engine           1050 drivers/gpu/drm/i915/gt/intel_reset.c 		ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
engine           1054 drivers/gpu/drm/i915/gt/intel_reset.c 				 engine->gt->uc.guc.execbuf_client ? "GuC " : "",
engine           1055 drivers/gpu/drm/i915/gt/intel_reset.c 				 engine->name, ret);
engine           1064 drivers/gpu/drm/i915/gt/intel_reset.c 	__intel_engine_reset(engine, true);
engine           1071 drivers/gpu/drm/i915/gt/intel_reset.c 	ret = engine->resume(engine);
engine           1074 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_engine_cancel_stop_cs(engine);
engine           1075 drivers/gpu/drm/i915/gt/intel_reset.c 	reset_finish_engine(engine);
engine           1076 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_engine_pm_put(engine);
engine           1129 drivers/gpu/drm/i915/gt/intel_reset.c 	struct intel_engine_cs *engine;
engine           1166 drivers/gpu/drm/i915/gt/intel_reset.c 		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
engine           1168 drivers/gpu/drm/i915/gt/intel_reset.c 			if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
engine           1172 drivers/gpu/drm/i915/gt/intel_reset.c 			if (intel_engine_reset(engine, msg) == 0)
engine           1173 drivers/gpu/drm/i915/gt/intel_reset.c 				engine_mask &= ~engine->mask;
engine           1175 drivers/gpu/drm/i915/gt/intel_reset.c 			clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
engine           1194 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, tmp) {
engine           1195 drivers/gpu/drm/i915/gt/intel_reset.c 		while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
engine           1198 drivers/gpu/drm/i915/gt/intel_reset.c 				    I915_RESET_ENGINE + engine->id,
engine           1204 drivers/gpu/drm/i915/gt/intel_reset.c 	for_each_engine(engine, gt->i915, tmp)
engine           1205 drivers/gpu/drm/i915/gt/intel_reset.c 		clear_bit_unlock(I915_RESET_ENGINE + engine->id,
engine             36 drivers/gpu/drm/i915/gt/intel_reset.h int intel_engine_reset(struct intel_engine_cs *engine,
engine             80 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
engine            154 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
engine            164 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
engine            219 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		intel_gt_scratch_offset(rq->engine->gt,
engine            254 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		intel_gt_scratch_offset(rq->engine->gt,
engine            313 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	*cs++ = intel_gt_scratch_offset(rq->engine->gt,
engine            359 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		intel_gt_scratch_offset(rq->engine->gt,
engine            442 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
engine            462 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
engine            489 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
engine            495 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (engine->class == RENDER_CLASS) {
engine            496 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		if (INTEL_GEN(engine->i915) >= 6)
engine            502 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_engine_set_hwsp_writemask(engine, mask);
engine            505 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
engine            507 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine            517 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static struct page *status_page(struct intel_engine_cs *engine)
engine            519 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
engine            525 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
engine            527 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
engine            528 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	set_hwstam(engine, ~0u);
engine            531 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
engine            533 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine            541 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		switch (engine->id) {
engine            547 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			GEM_BUG_ON(engine->id);
engine            563 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
engine            565 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		hwsp = RING_HWS_PGA(engine->mmio_base);
engine            572 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void flush_cs_tlb(struct intel_engine_cs *engine)
engine            574 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine            580 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
engine            582 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_INSTPM,
engine            585 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (intel_wait_for_register(engine->uncore,
engine            586 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				    RING_INSTPM(engine->mmio_base),
engine            590 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  engine->name);
engine            593 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void ring_setup_status_page(struct intel_engine_cs *engine)
engine            595 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
engine            596 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	set_hwstam(engine, ~0u);
engine            598 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	flush_cs_tlb(engine);
engine            601 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static bool stop_ring(struct intel_engine_cs *engine)
engine            603 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine            606 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ENGINE_WRITE(engine,
engine            608 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		if (intel_wait_for_register(engine->uncore,
engine            609 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 					    RING_MI_MODE(engine->mmio_base),
engine            614 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				  engine->name);
engine            621 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			if (ENGINE_READ(engine, RING_HEAD) !=
engine            622 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			    ENGINE_READ(engine, RING_TAIL))
engine            627 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
engine            629 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_HEAD, 0);
engine            630 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_TAIL, 0);
engine            633 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_CTL, 0);
engine            635 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
engine            638 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static int xcs_resume(struct intel_engine_cs *engine)
engine            640 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine            641 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct intel_ring *ring = engine->legacy.ring;
engine            645 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		  engine->name, ring->head, ring->tail);
engine            647 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
engine            650 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (!stop_ring(engine)) {
engine            654 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				engine->name,
engine            655 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				ENGINE_READ(engine, RING_CTL),
engine            656 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				ENGINE_READ(engine, RING_HEAD),
engine            657 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				ENGINE_READ(engine, RING_TAIL),
engine            658 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				ENGINE_READ(engine, RING_START));
engine            660 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		if (!stop_ring(engine)) {
engine            663 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				  engine->name,
engine            664 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				  ENGINE_READ(engine, RING_CTL),
engine            665 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				  ENGINE_READ(engine, RING_HEAD),
engine            666 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				  ENGINE_READ(engine, RING_TAIL),
engine            667 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				  ENGINE_READ(engine, RING_START));
engine            674 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ring_setup_phys_status_page(engine);
engine            676 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ring_setup_status_page(engine);
engine            678 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_engine_reset_breadcrumbs(engine);
engine            681 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_POSTING_READ(engine, RING_HEAD);
engine            689 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
engine            697 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_HEAD, ring->head);
engine            698 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_TAIL, ring->head);
engine            699 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_POSTING_READ(engine, RING_TAIL);
engine            701 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID);
engine            704 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (intel_wait_for_register(engine->uncore,
engine            705 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				    RING_CTL(engine->mmio_base),
engine            710 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  engine->name,
engine            711 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  ENGINE_READ(engine, RING_CTL),
engine            712 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  ENGINE_READ(engine, RING_CTL) & RING_VALID,
engine            713 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  ENGINE_READ(engine, RING_HEAD), ring->head,
engine            714 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  ENGINE_READ(engine, RING_TAIL), ring->tail,
engine            715 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  ENGINE_READ(engine, RING_START),
engine            722 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ENGINE_WRITE(engine,
engine            727 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ENGINE_WRITE(engine, RING_TAIL, ring->tail);
engine            728 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ENGINE_POSTING_READ(engine, RING_TAIL);
engine            732 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_engine_queue_breadcrumbs(engine);
engine            734 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
engine            739 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void reset_prepare(struct intel_engine_cs *engine)
engine            741 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct intel_uncore *uncore = engine->uncore;
engine            742 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	const u32 base = engine->mmio_base;
engine            758 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_TRACE("%s\n", engine->name);
engine            760 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (intel_engine_stop_cs(engine))
engine            761 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
engine            778 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			  engine->name,
engine            782 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void reset_ring(struct intel_engine_cs *engine, bool stalled)
engine            789 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            790 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	list_for_each_entry(pos, &engine->active.requests, sched.link) {
engine            837 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		GEM_BUG_ON(rq->ring != engine->legacy.ring);
engine            840 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		head = engine->legacy.ring->tail;
engine            842 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);
engine            844 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            847 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void reset_finish(struct intel_engine_cs *engine)
engine            851 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static int rcs_resume(struct intel_engine_cs *engine)
engine            853 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine            907 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	return xcs_resume(engine);
engine            910 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void cancel_requests(struct intel_engine_cs *engine)
engine            915 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            918 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	list_for_each_entry(request, &engine->active.requests, sched.link) {
engine            927 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            934 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(request->engine, RING_TAIL,
engine            940 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
engine            963 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
engine            985 drivers/gpu/drm/i915/gt/intel_ringbuffer.c gen5_irq_enable(struct intel_engine_cs *engine)
engine            987 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
engine            991 drivers/gpu/drm/i915/gt/intel_ringbuffer.c gen5_irq_disable(struct intel_engine_cs *engine)
engine            993 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
engine            997 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i9xx_irq_enable(struct intel_engine_cs *engine)
engine            999 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->i915->irq_mask &= ~engine->irq_enable_mask;
engine           1000 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
engine           1001 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
engine           1005 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i9xx_irq_disable(struct intel_engine_cs *engine)
engine           1007 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->i915->irq_mask |= engine->irq_enable_mask;
engine           1008 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
engine           1012 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i8xx_irq_enable(struct intel_engine_cs *engine)
engine           1014 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           1016 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	i915->irq_mask &= ~engine->irq_enable_mask;
engine           1018 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_POSTING_READ16(engine, RING_IMR);
engine           1022 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i8xx_irq_disable(struct intel_engine_cs *engine)
engine           1024 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           1026 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	i915->irq_mask |= engine->irq_enable_mask;
engine           1046 drivers/gpu/drm/i915/gt/intel_ringbuffer.c gen6_irq_enable(struct intel_engine_cs *engine)
engine           1048 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_IMR,
engine           1049 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
engine           1052 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_POSTING_READ(engine, RING_IMR);
engine           1054 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
engine           1058 drivers/gpu/drm/i915/gt/intel_ringbuffer.c gen6_irq_disable(struct intel_engine_cs *engine)
engine           1060 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
engine           1061 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
engine           1065 drivers/gpu/drm/i915/gt/intel_ringbuffer.c hsw_vebox_irq_enable(struct intel_engine_cs *engine)
engine           1067 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
engine           1070 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_POSTING_READ(engine, RING_IMR);
engine           1072 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask);
engine           1076 drivers/gpu/drm/i915/gt/intel_ringbuffer.c hsw_vebox_irq_disable(struct intel_engine_cs *engine)
engine           1078 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_IMR, ~0);
engine           1079 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask);
engine           1111 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		intel_gt_scratch_offset(rq->engine->gt,
engine           1114 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
engine           1299 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_engine_create_ring(struct intel_engine_cs *engine, int size)
engine           1301 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           1327 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	vma = create_ring_vma(engine->gt->ggtt, size);
engine           1403 drivers/gpu/drm/i915/gt/intel_ringbuffer.c alloc_context_vma(struct intel_engine_cs *engine)
engine           1405 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           1410 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	obj = i915_gem_object_create_shmem(i915, engine->context_size);
engine           1432 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (engine->default_state) {
engine           1441 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		defaults = i915_gem_object_pin_map(engine->default_state,
engine           1448 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		memcpy(vaddr, defaults, engine->context_size);
engine           1449 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		i915_gem_object_unpin_map(engine->default_state);
engine           1455 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
engine           1472 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct intel_engine_cs *engine = ce->engine;
engine           1475 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(!engine->legacy.ring);
engine           1476 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ce->ring = engine->legacy.ring;
engine           1477 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ce->timeline = intel_timeline_get(engine->legacy.timeline);
engine           1480 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	if (engine->context_size) {
engine           1483 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		vma = alloc_context_vma(engine);
engine           1532 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	const struct intel_engine_cs * const engine = rq->engine;
engine           1540 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
engine           1544 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
engine           1554 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	const struct intel_engine_cs * const engine = rq->engine;
engine           1563 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
engine           1564 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	*cs++ = intel_gt_scratch_offset(rq->engine->gt,
engine           1575 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct intel_engine_cs *engine = rq->engine;
engine           1615 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				if (signaller == engine)
engine           1648 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		*cs++ = i915_ggtt_offset(engine->kernel_context->state) |
engine           1669 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				if (signaller == engine)
engine           1681 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			*cs++ = intel_gt_scratch_offset(rq->engine->gt,
engine           1746 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct intel_engine_cs *engine = rq->engine;
engine           1768 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915))
engine           1777 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		if (ppgtt->pd_dirty_engines & engine->mask) {
engine           1778 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			unwind_mm = engine->mask;
engine           1785 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		GEM_BUG_ON(engine->id != RCS0);
engine           1803 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ret = engine->emit_flush(rq, EMIT_INVALIDATE);
engine           1819 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ret = engine->emit_flush(rq, EMIT_INVALIDATE);
engine           1823 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		ret = engine->emit_flush(rq, EMIT_FLUSH);
engine           1856 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
engine           2010 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct intel_uncore *uncore = request->engine->uncore;
engine           2138 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void i9xx_set_default_submission(struct intel_engine_cs *engine)
engine           2140 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->submit_request = i9xx_submit_request;
engine           2141 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->cancel_requests = cancel_requests;
engine           2143 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->park = NULL;
engine           2144 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->unpark = NULL;
engine           2147 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
engine           2149 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	i9xx_set_default_submission(engine);
engine           2150 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->submit_request = gen6_bsd_submit_request;
engine           2153 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void ring_destroy(struct intel_engine_cs *engine)
engine           2155 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *dev_priv = engine->i915;
engine           2158 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
engine           2160 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_engine_cleanup_common(engine);
engine           2162 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_ring_unpin(engine->legacy.ring);
engine           2163 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_ring_put(engine->legacy.ring);
engine           2165 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_timeline_unpin(engine->legacy.timeline);
engine           2166 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_timeline_put(engine->legacy.timeline);
engine           2168 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	kfree(engine);
engine           2171 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void setup_irq(struct intel_engine_cs *engine)
engine           2173 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           2176 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable = gen6_irq_enable;
engine           2177 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_disable = gen6_irq_disable;
engine           2179 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable = gen5_irq_enable;
engine           2180 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_disable = gen5_irq_disable;
engine           2182 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable = i9xx_irq_enable;
engine           2183 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_disable = i9xx_irq_disable;
engine           2185 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable = i8xx_irq_enable;
engine           2186 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_disable = i8xx_irq_disable;
engine           2190 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void setup_common(struct intel_engine_cs *engine)
engine           2192 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           2197 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	setup_irq(engine);
engine           2199 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->destroy = ring_destroy;
engine           2201 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->resume = xcs_resume;
engine           2202 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->reset.prepare = reset_prepare;
engine           2203 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->reset.reset = reset_ring;
engine           2204 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->reset.finish = reset_finish;
engine           2206 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->cops = &ring_context_ops;
engine           2207 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->request_alloc = ring_request_alloc;
engine           2214 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb;
engine           2216 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
engine           2218 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->set_default_submission = i9xx_set_default_submission;
engine           2221 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_bb_start = gen6_emit_bb_start;
engine           2223 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_bb_start = i965_emit_bb_start;
engine           2225 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_bb_start = i830_emit_bb_start;
engine           2227 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_bb_start = i915_emit_bb_start;
engine           2230 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void setup_rcs(struct intel_engine_cs *engine)
engine           2232 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           2235 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
engine           2237 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine           2240 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_flush = gen7_render_ring_flush;
engine           2241 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb;
engine           2243 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_flush = gen6_render_ring_flush;
engine           2244 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb;
engine           2246 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_flush = gen4_render_ring_flush;
engine           2249 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->emit_flush = gen2_render_ring_flush;
engine           2251 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->emit_flush = gen4_render_ring_flush;
engine           2252 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable_mask = I915_USER_INTERRUPT;
engine           2256 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_bb_start = hsw_emit_bb_start;
engine           2258 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->resume = rcs_resume;
engine           2261 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void setup_vcs(struct intel_engine_cs *engine)
engine           2263 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           2268 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->set_default_submission = gen6_bsd_set_default_submission;
engine           2269 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_flush = gen6_bsd_ring_flush;
engine           2270 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
engine           2273 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb;
engine           2275 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
engine           2277 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_flush = bsd_ring_flush;
engine           2279 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
engine           2281 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
engine           2285 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void setup_bcs(struct intel_engine_cs *engine)
engine           2287 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           2289 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->emit_flush = gen6_ring_flush;
engine           2290 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
engine           2293 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb;
engine           2295 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
engine           2298 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void setup_vecs(struct intel_engine_cs *engine)
engine           2300 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	struct drm_i915_private *i915 = engine->i915;
engine           2304 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->emit_flush = gen6_ring_flush;
engine           2305 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
engine           2306 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable = hsw_vebox_irq_enable;
engine           2307 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_disable = hsw_vebox_irq_disable;
engine           2309 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
engine           2312 drivers/gpu/drm/i915/gt/intel_ringbuffer.c int intel_ring_submission_setup(struct intel_engine_cs *engine)
engine           2314 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	setup_common(engine);
engine           2316 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	switch (engine->class) {
engine           2318 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		setup_rcs(engine);
engine           2321 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		setup_vcs(engine);
engine           2324 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		setup_bcs(engine);
engine           2327 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		setup_vecs(engine);
engine           2330 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		MISSING_CASE(engine->class);
engine           2337 drivers/gpu/drm/i915/gt/intel_ringbuffer.c int intel_ring_submission_init(struct intel_engine_cs *engine)
engine           2343 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	timeline = intel_timeline_create(engine->gt, engine->status_page.vma);
engine           2354 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ring = intel_engine_create_ring(engine, SZ_16K);
engine           2364 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(engine->legacy.ring);
engine           2365 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->legacy.ring = ring;
engine           2366 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->legacy.timeline = timeline;
engine           2368 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	err = intel_engine_init_common(engine);
engine           2372 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
engine           2385 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	intel_engine_cleanup_common(engine);
engine            189 drivers/gpu/drm/i915/gt/intel_workarounds.c static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            237 drivers/gpu/drm/i915/gt/intel_workarounds.c static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            240 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            242 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen8_ctx_workarounds_init(engine, wal);
engine            265 drivers/gpu/drm/i915/gt/intel_workarounds.c static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            268 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen8_ctx_workarounds_init(engine, wal);
engine            277 drivers/gpu/drm/i915/gt/intel_workarounds.c static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            280 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            370 drivers/gpu/drm/i915/gt/intel_workarounds.c static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
engine            373 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            410 drivers/gpu/drm/i915/gt/intel_workarounds.c static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            413 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen9_ctx_workarounds_init(engine, wal);
engine            414 drivers/gpu/drm/i915/gt/intel_workarounds.c 	skl_tune_iz_hashing(engine, wal);
engine            417 drivers/gpu/drm/i915/gt/intel_workarounds.c static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            420 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen9_ctx_workarounds_init(engine, wal);
engine            431 drivers/gpu/drm/i915/gt/intel_workarounds.c static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            434 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            436 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen9_ctx_workarounds_init(engine, wal);
engine            448 drivers/gpu/drm/i915/gt/intel_workarounds.c static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            451 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen9_ctx_workarounds_init(engine, wal);
engine            458 drivers/gpu/drm/i915/gt/intel_workarounds.c static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            461 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen9_ctx_workarounds_init(engine, wal);
engine            472 drivers/gpu/drm/i915/gt/intel_workarounds.c static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            475 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            512 drivers/gpu/drm/i915/gt/intel_workarounds.c static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            515 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            520 drivers/gpu/drm/i915/gt/intel_workarounds.c 		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
engine            567 drivers/gpu/drm/i915/gt/intel_workarounds.c static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
engine            573 drivers/gpu/drm/i915/gt/intel_workarounds.c __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
engine            577 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            579 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine            582 drivers/gpu/drm/i915/gt/intel_workarounds.c 	wa_init_start(wal, name, engine->name);
engine            585 drivers/gpu/drm/i915/gt/intel_workarounds.c 		tgl_ctx_workarounds_init(engine, wal);
engine            587 drivers/gpu/drm/i915/gt/intel_workarounds.c 		icl_ctx_workarounds_init(engine, wal);
engine            589 drivers/gpu/drm/i915/gt/intel_workarounds.c 		cnl_ctx_workarounds_init(engine, wal);
engine            591 drivers/gpu/drm/i915/gt/intel_workarounds.c 		cfl_ctx_workarounds_init(engine, wal);
engine            593 drivers/gpu/drm/i915/gt/intel_workarounds.c 		glk_ctx_workarounds_init(engine, wal);
engine            595 drivers/gpu/drm/i915/gt/intel_workarounds.c 		kbl_ctx_workarounds_init(engine, wal);
engine            597 drivers/gpu/drm/i915/gt/intel_workarounds.c 		bxt_ctx_workarounds_init(engine, wal);
engine            599 drivers/gpu/drm/i915/gt/intel_workarounds.c 		skl_ctx_workarounds_init(engine, wal);
engine            601 drivers/gpu/drm/i915/gt/intel_workarounds.c 		chv_ctx_workarounds_init(engine, wal);
engine            603 drivers/gpu/drm/i915/gt/intel_workarounds.c 		bdw_ctx_workarounds_init(engine, wal);
engine            612 drivers/gpu/drm/i915/gt/intel_workarounds.c void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
engine            614 drivers/gpu/drm/i915/gt/intel_workarounds.c 	__intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
engine            619 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
engine            628 drivers/gpu/drm/i915/gt/intel_workarounds.c 	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
engine            645 drivers/gpu/drm/i915/gt/intel_workarounds.c 	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
engine           1071 drivers/gpu/drm/i915/gt/intel_workarounds.c static void skl_whitelist_build(struct intel_engine_cs *engine)
engine           1073 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1075 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine           1084 drivers/gpu/drm/i915/gt/intel_workarounds.c static void bxt_whitelist_build(struct intel_engine_cs *engine)
engine           1086 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine           1089 drivers/gpu/drm/i915/gt/intel_workarounds.c 	gen9_whitelist_build(&engine->whitelist);
engine           1092 drivers/gpu/drm/i915/gt/intel_workarounds.c static void kbl_whitelist_build(struct intel_engine_cs *engine)
engine           1094 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1096 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine           1105 drivers/gpu/drm/i915/gt/intel_workarounds.c static void glk_whitelist_build(struct intel_engine_cs *engine)
engine           1107 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1109 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine           1118 drivers/gpu/drm/i915/gt/intel_workarounds.c static void cfl_whitelist_build(struct intel_engine_cs *engine)
engine           1120 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1122 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine           1141 drivers/gpu/drm/i915/gt/intel_workarounds.c static void cnl_whitelist_build(struct intel_engine_cs *engine)
engine           1143 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1145 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class != RENDER_CLASS)
engine           1152 drivers/gpu/drm/i915/gt/intel_workarounds.c static void icl_whitelist_build(struct intel_engine_cs *engine)
engine           1154 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1156 drivers/gpu/drm/i915/gt/intel_workarounds.c 	switch (engine->class) {
engine           1183 drivers/gpu/drm/i915/gt/intel_workarounds.c 		whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
engine           1186 drivers/gpu/drm/i915/gt/intel_workarounds.c 		whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
engine           1189 drivers/gpu/drm/i915/gt/intel_workarounds.c 		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
engine           1198 drivers/gpu/drm/i915/gt/intel_workarounds.c static void tgl_whitelist_build(struct intel_engine_cs *engine)
engine           1202 drivers/gpu/drm/i915/gt/intel_workarounds.c void intel_engine_init_whitelist(struct intel_engine_cs *engine)
engine           1204 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine           1205 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *w = &engine->whitelist;
engine           1207 drivers/gpu/drm/i915/gt/intel_workarounds.c 	wa_init_start(w, "whitelist", engine->name);
engine           1210 drivers/gpu/drm/i915/gt/intel_workarounds.c 		tgl_whitelist_build(engine);
engine           1212 drivers/gpu/drm/i915/gt/intel_workarounds.c 		icl_whitelist_build(engine);
engine           1214 drivers/gpu/drm/i915/gt/intel_workarounds.c 		cnl_whitelist_build(engine);
engine           1216 drivers/gpu/drm/i915/gt/intel_workarounds.c 		cfl_whitelist_build(engine);
engine           1218 drivers/gpu/drm/i915/gt/intel_workarounds.c 		glk_whitelist_build(engine);
engine           1220 drivers/gpu/drm/i915/gt/intel_workarounds.c 		kbl_whitelist_build(engine);
engine           1222 drivers/gpu/drm/i915/gt/intel_workarounds.c 		bxt_whitelist_build(engine);
engine           1224 drivers/gpu/drm/i915/gt/intel_workarounds.c 		skl_whitelist_build(engine);
engine           1233 drivers/gpu/drm/i915/gt/intel_workarounds.c void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
engine           1235 drivers/gpu/drm/i915/gt/intel_workarounds.c 	const struct i915_wa_list *wal = &engine->whitelist;
engine           1236 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct intel_uncore *uncore = engine->uncore;
engine           1237 drivers/gpu/drm/i915/gt/intel_workarounds.c 	const u32 base = engine->mmio_base;
engine           1257 drivers/gpu/drm/i915/gt/intel_workarounds.c rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
engine           1259 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine           1374 drivers/gpu/drm/i915/gt/intel_workarounds.c xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
engine           1376 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine           1381 drivers/gpu/drm/i915/gt/intel_workarounds.c 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
engine           1387 drivers/gpu/drm/i915/gt/intel_workarounds.c engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
engine           1389 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
engine           1392 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (engine->class == RENDER_CLASS)
engine           1393 drivers/gpu/drm/i915/gt/intel_workarounds.c 		rcs_engine_wa_init(engine, wal);
engine           1395 drivers/gpu/drm/i915/gt/intel_workarounds.c 		xcs_engine_wa_init(engine, wal);
engine           1398 drivers/gpu/drm/i915/gt/intel_workarounds.c void intel_engine_init_workarounds(struct intel_engine_cs *engine)
engine           1400 drivers/gpu/drm/i915/gt/intel_workarounds.c 	struct i915_wa_list *wal = &engine->wa_list;
engine           1402 drivers/gpu/drm/i915/gt/intel_workarounds.c 	if (INTEL_GEN(engine->i915) < 8)
engine           1405 drivers/gpu/drm/i915/gt/intel_workarounds.c 	wa_init_start(wal, "engine", engine->name);
engine           1406 drivers/gpu/drm/i915/gt/intel_workarounds.c 	engine_init_workarounds(engine, wal);
engine           1410 drivers/gpu/drm/i915/gt/intel_workarounds.c void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
engine           1412 drivers/gpu/drm/i915/gt/intel_workarounds.c 	wa_list_apply(engine->uncore, &engine->wa_list);
engine           1514 drivers/gpu/drm/i915/gt/intel_workarounds.c 	vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
engine           1557 drivers/gpu/drm/i915/gt/intel_workarounds.c int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
engine           1560 drivers/gpu/drm/i915/gt/intel_workarounds.c 	return engine_wa_list_verify(engine->kernel_context,
engine           1561 drivers/gpu/drm/i915/gt/intel_workarounds.c 				     &engine->wa_list,
engine             25 drivers/gpu/drm/i915/gt/intel_workarounds.h void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
engine             32 drivers/gpu/drm/i915/gt/intel_workarounds.h void intel_engine_init_whitelist(struct intel_engine_cs *engine);
engine             33 drivers/gpu/drm/i915/gt/intel_workarounds.h void intel_engine_apply_whitelist(struct intel_engine_cs *engine);
engine             35 drivers/gpu/drm/i915/gt/intel_workarounds.h void intel_engine_init_workarounds(struct intel_engine_cs *engine);
engine             36 drivers/gpu/drm/i915/gt/intel_workarounds.h void intel_engine_apply_workarounds(struct intel_engine_cs *engine);
engine             37 drivers/gpu/drm/i915/gt/intel_workarounds.h int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
engine             46 drivers/gpu/drm/i915/gt/mock_engine.c static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
engine             66 drivers/gpu/drm/i915/gt/mock_engine.c static struct i915_request *first_request(struct mock_engine *engine)
engine             68 drivers/gpu/drm/i915/gt/mock_engine.c 	return list_first_entry_or_null(&engine->hw_queue,
engine             79 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_queue_breadcrumbs(request->engine);
engine             84 drivers/gpu/drm/i915/gt/mock_engine.c 	struct mock_engine *engine = from_timer(engine, t, hw_delay);
engine             88 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_lock_irqsave(&engine->hw_lock, flags);
engine             91 drivers/gpu/drm/i915/gt/mock_engine.c 	request = first_request(engine);
engine             99 drivers/gpu/drm/i915/gt/mock_engine.c 	while ((request = first_request(engine))) {
engine            101 drivers/gpu/drm/i915/gt/mock_engine.c 			mod_timer(&engine->hw_delay,
engine            109 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_unlock_irqrestore(&engine->hw_lock, flags);
engine            133 drivers/gpu/drm/i915/gt/mock_engine.c 	ce->ring = mock_ring(ce->engine);
engine            138 drivers/gpu/drm/i915/gt/mock_engine.c 	ce->timeline = intel_timeline_create(ce->engine->gt, NULL);
engine            140 drivers/gpu/drm/i915/gt/mock_engine.c 		kfree(ce->engine);
engine            187 drivers/gpu/drm/i915/gt/mock_engine.c 	struct mock_engine *engine =
engine            188 drivers/gpu/drm/i915/gt/mock_engine.c 		container_of(request->engine, typeof(*engine), base);
engine            193 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_lock_irqsave(&engine->hw_lock, flags);
engine            194 drivers/gpu/drm/i915/gt/mock_engine.c 	list_add_tail(&request->mock.link, &engine->hw_queue);
engine            195 drivers/gpu/drm/i915/gt/mock_engine.c 	if (list_is_first(&request->mock.link, &engine->hw_queue)) {
engine            197 drivers/gpu/drm/i915/gt/mock_engine.c 			mod_timer(&engine->hw_delay,
engine            202 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_unlock_irqrestore(&engine->hw_lock, flags);
engine            205 drivers/gpu/drm/i915/gt/mock_engine.c static void mock_reset_prepare(struct intel_engine_cs *engine)
engine            209 drivers/gpu/drm/i915/gt/mock_engine.c static void mock_reset(struct intel_engine_cs *engine, bool stalled)
engine            214 drivers/gpu/drm/i915/gt/mock_engine.c static void mock_reset_finish(struct intel_engine_cs *engine)
engine            218 drivers/gpu/drm/i915/gt/mock_engine.c static void mock_cancel_requests(struct intel_engine_cs *engine)
engine            223 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            226 drivers/gpu/drm/i915/gt/mock_engine.c 	list_for_each_entry(request, &engine->active.requests, sched.link) {
engine            233 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            240 drivers/gpu/drm/i915/gt/mock_engine.c 	struct mock_engine *engine;
engine            244 drivers/gpu/drm/i915/gt/mock_engine.c 	engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL);
engine            245 drivers/gpu/drm/i915/gt/mock_engine.c 	if (!engine)
engine            249 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.i915 = i915;
engine            250 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.gt = &i915->gt;
engine            251 drivers/gpu/drm/i915/gt/mock_engine.c 	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
engine            252 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.id = id;
engine            253 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.mask = BIT(id);
engine            254 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.instance = id;
engine            255 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.status_page.addr = (void *)(engine + 1);
engine            257 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.cops = &mock_context_ops;
engine            258 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.request_alloc = mock_request_alloc;
engine            259 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.emit_flush = mock_emit_flush;
engine            260 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
engine            261 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.submit_request = mock_submit_request;
engine            263 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.reset.prepare = mock_reset_prepare;
engine            264 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.reset.reset = mock_reset;
engine            265 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.reset.finish = mock_reset_finish;
engine            266 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->base.cancel_requests = mock_cancel_requests;
engine            269 drivers/gpu/drm/i915/gt/mock_engine.c 	spin_lock_init(&engine->hw_lock);
engine            270 drivers/gpu/drm/i915/gt/mock_engine.c 	timer_setup(&engine->hw_delay, hw_delay_complete, 0);
engine            271 drivers/gpu/drm/i915/gt/mock_engine.c 	INIT_LIST_HEAD(&engine->hw_queue);
engine            273 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_add_user(&engine->base);
engine            275 drivers/gpu/drm/i915/gt/mock_engine.c 	return &engine->base;
engine            278 drivers/gpu/drm/i915/gt/mock_engine.c int mock_engine_init(struct intel_engine_cs *engine)
engine            282 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_init_active(engine, ENGINE_MOCK);
engine            283 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_init_breadcrumbs(engine);
engine            284 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_init_execlists(engine);
engine            285 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_init__pm(engine);
engine            286 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_pool_init(&engine->pool);
engine            288 drivers/gpu/drm/i915/gt/mock_engine.c 	ce = create_kernel_context(engine);
engine            292 drivers/gpu/drm/i915/gt/mock_engine.c 	engine->kernel_context = ce;
engine            296 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_fini_breadcrumbs(engine);
engine            300 drivers/gpu/drm/i915/gt/mock_engine.c void mock_engine_flush(struct intel_engine_cs *engine)
engine            303 drivers/gpu/drm/i915/gt/mock_engine.c 		container_of(engine, typeof(*mock), base);
engine            314 drivers/gpu/drm/i915/gt/mock_engine.c void mock_engine_reset(struct intel_engine_cs *engine)
engine            318 drivers/gpu/drm/i915/gt/mock_engine.c void mock_engine_free(struct intel_engine_cs *engine)
engine            321 drivers/gpu/drm/i915/gt/mock_engine.c 		container_of(engine, typeof(*mock), base);
engine            325 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_context_unpin(engine->kernel_context);
engine            326 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_context_put(engine->kernel_context);
engine            328 drivers/gpu/drm/i915/gt/mock_engine.c 	intel_engine_fini_breadcrumbs(engine);
engine            330 drivers/gpu/drm/i915/gt/mock_engine.c 	kfree(engine);
engine             45 drivers/gpu/drm/i915/gt/mock_engine.h int mock_engine_init(struct intel_engine_cs *engine);
engine             47 drivers/gpu/drm/i915/gt/mock_engine.h void mock_engine_flush(struct intel_engine_cs *engine);
engine             48 drivers/gpu/drm/i915/gt/mock_engine.h void mock_engine_reset(struct intel_engine_cs *engine);
engine             49 drivers/gpu/drm/i915/gt/mock_engine.h void mock_engine_free(struct intel_engine_cs *engine);
engine             68 drivers/gpu/drm/i915/gt/selftest_context.c static int __live_context_size(struct intel_engine_cs *engine,
engine             76 drivers/gpu/drm/i915/gt/selftest_context.c 	ce = intel_context_create(fixme, engine);
engine             85 drivers/gpu/drm/i915/gt/selftest_context.c 					i915_coherent_map_type(engine->i915));
engine            104 drivers/gpu/drm/i915/gt/selftest_context.c 	if (HAS_EXECLISTS(engine->i915))
engine            107 drivers/gpu/drm/i915/gt/selftest_context.c 	vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
engine            122 drivers/gpu/drm/i915/gt/selftest_context.c 	rq = i915_request_create(engine->kernel_context);
engine            132 drivers/gpu/drm/i915/gt/selftest_context.c 		pr_err("%s context overwrote trailing red-zone!", engine->name);
engine            146 drivers/gpu/drm/i915/gt/selftest_context.c 	struct intel_engine_cs *engine;
engine            164 drivers/gpu/drm/i915/gt/selftest_context.c 	for_each_engine(engine, gt->i915, id) {
engine            170 drivers/gpu/drm/i915/gt/selftest_context.c 		if (!engine->context_size)
engine            173 drivers/gpu/drm/i915/gt/selftest_context.c 		intel_engine_pm_get(engine);
engine            182 drivers/gpu/drm/i915/gt/selftest_context.c 		saved.state = fetch_and_zero(&engine->default_state);
engine            183 drivers/gpu/drm/i915/gt/selftest_context.c 		saved.pinned = fetch_and_zero(&engine->pinned_default_state);
engine            186 drivers/gpu/drm/i915/gt/selftest_context.c 		engine->context_size += I915_GTT_PAGE_SIZE;
engine            188 drivers/gpu/drm/i915/gt/selftest_context.c 		err = __live_context_size(engine, fixme);
engine            190 drivers/gpu/drm/i915/gt/selftest_context.c 		engine->context_size -= I915_GTT_PAGE_SIZE;
engine            192 drivers/gpu/drm/i915/gt/selftest_context.c 		engine->pinned_default_state = saved.pinned;
engine            193 drivers/gpu/drm/i915/gt/selftest_context.c 		engine->default_state = saved.state;
engine            195 drivers/gpu/drm/i915/gt/selftest_context.c 		intel_engine_pm_put(engine);
engine            207 drivers/gpu/drm/i915/gt/selftest_context.c static int __live_active_context(struct intel_engine_cs *engine,
engine            227 drivers/gpu/drm/i915/gt/selftest_context.c 	if (intel_engine_pm_is_awake(engine)) {
engine            229 drivers/gpu/drm/i915/gt/selftest_context.c 		       engine->name, __func__);
engine            233 drivers/gpu/drm/i915/gt/selftest_context.c 	ce = intel_context_create(fixme, engine);
engine            253 drivers/gpu/drm/i915/gt/selftest_context.c 			       engine->name, pass);
engine            258 drivers/gpu/drm/i915/gt/selftest_context.c 		if (!intel_engine_pm_is_awake(engine)) {
engine            260 drivers/gpu/drm/i915/gt/selftest_context.c 			       engine->name);
engine            267 drivers/gpu/drm/i915/gt/selftest_context.c 	err = context_sync(engine->kernel_context);
engine            276 drivers/gpu/drm/i915/gt/selftest_context.c 	if (intel_engine_pm_is_awake(engine)) {
engine            279 drivers/gpu/drm/i915/gt/selftest_context.c 		intel_engine_dump(engine, &p,
engine            281 drivers/gpu/drm/i915/gt/selftest_context.c 				  engine->name);
engine            296 drivers/gpu/drm/i915/gt/selftest_context.c 	struct intel_engine_cs *engine;
engine            314 drivers/gpu/drm/i915/gt/selftest_context.c 	for_each_engine(engine, gt->i915, id) {
engine            315 drivers/gpu/drm/i915/gt/selftest_context.c 		err = __live_active_context(engine, fixme);
engine            358 drivers/gpu/drm/i915/gt/selftest_context.c static int __live_remote_context(struct intel_engine_cs *engine,
engine            373 drivers/gpu/drm/i915/gt/selftest_context.c 	remote = intel_context_create(fixme, engine);
engine            377 drivers/gpu/drm/i915/gt/selftest_context.c 	local = intel_context_create(fixme, engine);
engine            388 drivers/gpu/drm/i915/gt/selftest_context.c 		err = __remote_sync(engine->kernel_context, remote);
engine            394 drivers/gpu/drm/i915/gt/selftest_context.c 			       engine->name, pass);
engine            409 drivers/gpu/drm/i915/gt/selftest_context.c 	struct intel_engine_cs *engine;
engine            427 drivers/gpu/drm/i915/gt/selftest_context.c 	for_each_engine(engine, gt->i915, id) {
engine            428 drivers/gpu/drm/i915/gt/selftest_context.c 		err = __live_remote_context(engine, fixme);
engine             14 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 	struct intel_engine_cs *engine;
engine             28 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 	for_each_engine(engine, gt->i915, id) {
engine             46 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 			GEM_BUG_ON(intel_engine_pm_is_awake(engine));
engine             47 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 			intel_engine_pm_get(engine);
engine             50 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 			if (!intel_engine_pm_get_if_awake(engine))
engine             52 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 				       engine->name, p->name);
engine             54 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 				intel_engine_pm_put(engine);
engine             55 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 			intel_engine_pm_put(engine);
engine             59 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 			if (intel_engine_pm_is_awake(engine)) {
engine             61 drivers/gpu/drm/i915/gt/selftest_engine_pm.c 				       engine->name);
engine            131 drivers/gpu/drm/i915/gt/selftest_hangcheck.c hang_create_request(struct hang *h, struct intel_engine_cs *engine)
engine            134 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct i915_address_space *vm = h->ctx->vm ?: &engine->gt->ggtt->vm;
engine            175 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	rq = igt_request_alloc(h->ctx, engine);
engine            244 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	intel_gt_chipset_flush(engine->gt);
engine            246 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	if (rq->engine->emit_init_breadcrumb) {
engine            247 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		err = rq->engine->emit_init_breadcrumb(rq);
engine            256 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
engine            305 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine            317 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine            321 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (!intel_engine_can_store_dword(engine))
engine            324 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		rq = hang_create_request(&h, engine);
engine            328 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			       engine->name, err);
engine            335 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_gt_chipset_flush(engine->gt);
engine            351 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			       engine->name, err);
engine            363 drivers/gpu/drm/i915/gt/selftest_hangcheck.c static bool wait_for_idle(struct intel_engine_cs *engine)
engine            365 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0;
engine            372 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine            400 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		for_each_engine(engine, gt->i915, id) {
engine            406 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				rq = igt_request_alloc(ctx, engine);
engine            453 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine            477 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine            483 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		reset_engine_count = i915_reset_engine_count(global, engine);
engine            490 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			if (!wait_for_idle(engine)) {
engine            492 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       engine->name);
engine            501 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				rq = igt_request_alloc(ctx, engine);
engine            509 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			err = intel_engine_reset(engine, NULL);
engine            522 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			if (i915_reset_engine_count(global, engine) !=
engine            525 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       engine->name);
engine            531 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
engine            555 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine            573 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine            577 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (active && !intel_engine_can_store_dword(engine))
engine            580 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (!wait_for_idle(engine)) {
engine            582 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			       engine->name);
engine            588 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		reset_engine_count = i915_reset_engine_count(global, engine);
engine            590 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_pm_get(engine);
engine            597 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				rq = hang_create_request(&h, engine);
engine            613 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 					intel_engine_dump(engine, &p,
engine            614 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 							  "%s\n", engine->name);
engine            624 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			err = intel_engine_reset(engine, NULL);
engine            636 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			if (i915_reset_engine_count(global, engine) !=
engine            639 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       engine->name);
engine            645 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_pm_put(engine);
engine            679 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine            698 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			  rq->engine->name,
engine            703 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_gt_set_wedged(rq->engine->gt);
engine            716 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine = arg->engine;
engine            723 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	file = mock_file(engine->i915);
engine            728 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		mutex_lock(&engine->i915->drm.struct_mutex);
engine            729 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		ctx[count] = live_context(engine->i915, file);
engine            730 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		mutex_unlock(&engine->i915->drm.struct_mutex);
engine            744 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		mutex_lock(&engine->i915->drm.struct_mutex);
engine            745 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		new = igt_request_alloc(ctx[idx], engine);
engine            747 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			mutex_unlock(&engine->i915->drm.struct_mutex);
engine            758 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		mutex_unlock(&engine->i915->drm.struct_mutex);
engine            776 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	mock_file_free(engine->i915, file);
engine            785 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine, *other;
engine            808 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine            815 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		    !intel_engine_can_store_dword(engine))
engine            818 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (!wait_for_idle(engine)) {
engine            820 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			       engine->name, test_name);
engine            835 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			if (other == engine && !(flags & TEST_SELF))
engine            838 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			threads[tmp].engine = other;
engine            852 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_pm_get(engine);
engine            859 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				rq = hang_create_request(&h, engine);
engine            875 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 					intel_engine_dump(engine, &p,
engine            876 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 							  "%s\n", engine->name);
engine            884 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			err = intel_engine_reset(engine, NULL);
engine            887 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       engine->name, test_name, err);
engine            900 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 					       engine->name, test_name);
engine            901 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 					intel_engine_dump(engine, &p,
engine            902 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 							  "%s\n", engine->name);
engine            914 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {
engine            920 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       engine->name, test_name);
engine            921 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				intel_engine_dump(engine, &p,
engine            922 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 						  "%s\n", engine->name);
engine            929 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_pm_put(engine);
engine            931 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			engine->name, test_name, count);
engine            933 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		reported = i915_reset_engine_count(global, engine);
engine            934 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		reported -= threads[engine->id].resets;
engine            937 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			       engine->name, test_name, count, reported);
engine            958 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			if (other->uabi_class != engine->uabi_class &&
engine           1050 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
engine           1057 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	if (!engine || !intel_engine_can_store_dword(engine))
engine           1069 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	rq = hang_create_request(&h, engine);
engine           1083 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
engine           1186 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
engine           1194 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	if (!engine || !intel_engine_can_store_dword(engine))
engine           1224 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	rq = hang_create_request(&h, engine);
engine           1272 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
engine           1294 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
engine           1302 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	fake_hangcheck(gt, rq->engine->mask);
engine           1379 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine           1382 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine           1383 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (engine == exclude)
engine           1386 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (!wait_for_idle(engine))
engine           1397 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine;
engine           1411 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for_each_engine(engine, gt->i915, id) {
engine           1416 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (!intel_engine_can_store_dword(engine))
engine           1419 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		prev = hang_create_request(&h, engine);
engine           1433 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			rq = hang_create_request(&h, engine);
engine           1452 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			err = wait_for_others(gt, engine);
engine           1455 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       __func__, engine->name);
engine           1468 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				       __func__, engine->name,
engine           1470 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 				intel_engine_dump(engine, &p,
engine           1471 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 						  "%s\n", engine->name);
engine           1514 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		pr_info("%s: Completed %d resets\n", engine->name, count);
engine           1517 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_gt_chipset_flush(engine->gt);
engine           1542 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
engine           1553 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	if (!engine || !intel_engine_can_store_dword(engine))
engine           1562 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	rq = hang_create_request(&h, engine);
engine           1576 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
engine           1589 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	intel_gt_handle_error(gt, engine->mask, 0, NULL);
engine           1610 drivers/gpu/drm/i915/gt/selftest_hangcheck.c static int __igt_atomic_reset_engine(struct intel_engine_cs *engine,
engine           1614 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	struct tasklet_struct * const t = &engine->execlists.tasklet;
engine           1618 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		  engine->name, mode, p->name);
engine           1623 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	err = intel_engine_reset(engine, NULL);
engine           1630 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		       engine->name, mode, p->name);
engine           1635 drivers/gpu/drm/i915/gt/selftest_hangcheck.c static int igt_atomic_reset_engine(struct intel_engine_cs *engine,
engine           1642 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	err = __igt_atomic_reset_engine(engine, p, "idle");
engine           1646 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	err = hang_init(&h, engine->gt);
engine           1650 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	rq = hang_create_request(&h, engine);
engine           1660 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		err = __igt_atomic_reset_engine(engine, p, "active");
engine           1663 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		       __func__, engine->name,
engine           1665 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_gt_set_wedged(engine->gt);
engine           1672 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		intel_wedge_on_timeout(&w, engine->gt, HZ / 20 /* 50ms */)
engine           1674 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		if (intel_gt_is_wedged(engine->gt))
engine           1706 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		struct intel_engine_cs *engine;
engine           1709 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		for_each_engine(engine, gt->i915, id) {
engine           1710 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 			err = igt_atomic_reset_engine(engine, p);
engine            120 drivers/gpu/drm/i915/gt/selftest_lrc.c semaphore_queue(struct intel_engine_cs *engine, struct i915_vma *vma, int idx)
engine            126 drivers/gpu/drm/i915/gt/selftest_lrc.c 	ctx = kernel_context(engine->i915);
engine            130 drivers/gpu/drm/i915/gt/selftest_lrc.c 	rq = igt_request_alloc(ctx, engine);
engine            145 drivers/gpu/drm/i915/gt/selftest_lrc.c release_queue(struct intel_engine_cs *engine,
engine            155 drivers/gpu/drm/i915/gt/selftest_lrc.c 	rq = i915_request_create(engine->kernel_context);
engine            173 drivers/gpu/drm/i915/gt/selftest_lrc.c 	engine->schedule(rq, &attr);
engine            183 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine            193 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, outer->i915, id) {
engine            197 drivers/gpu/drm/i915/gt/selftest_lrc.c 			rq = semaphore_queue(engine, vma, n++);
engine            269 drivers/gpu/drm/i915/gt/selftest_lrc.c 		struct intel_engine_cs *engine;
engine            272 drivers/gpu/drm/i915/gt/selftest_lrc.c 		for_each_engine(engine, i915, id) {
engine            273 drivers/gpu/drm/i915/gt/selftest_lrc.c 			if (!intel_engine_has_preemption(engine))
engine            278 drivers/gpu/drm/i915/gt/selftest_lrc.c 			err = slice_semaphore_queue(engine, vma, count);
engine            306 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine            356 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine            361 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine            364 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_can_store_dword(engine))
engine            367 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
engine            381 drivers/gpu/drm/i915/gt/selftest_lrc.c 		lo = igt_request_alloc(ctx_lo, engine);
engine            420 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       engine->name);
engine            425 drivers/gpu/drm/i915/gt/selftest_lrc.c 		hi = igt_request_alloc(ctx_hi, engine);
engine            450 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       engine->name);
engine            452 drivers/gpu/drm/i915/gt/selftest_lrc.c 			intel_engine_dump(engine, &p, "%s\n", engine->name);
engine            487 drivers/gpu/drm/i915/gt/selftest_lrc.c 		       struct intel_engine_cs *engine,
engine            493 drivers/gpu/drm/i915/gt/selftest_lrc.c 	ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
engine            507 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine            539 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine            543 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine            546 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
engine            551 drivers/gpu/drm/i915/gt/selftest_lrc.c 		rq = spinner_create_request(&spin_lo, ctx_lo, engine,
engine            567 drivers/gpu/drm/i915/gt/selftest_lrc.c 		rq = spinner_create_request(&spin_hi, ctx_hi, engine,
engine            613 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine            642 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine            646 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine            649 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
engine            654 drivers/gpu/drm/i915/gt/selftest_lrc.c 		rq = spinner_create_request(&spin_lo, ctx_lo, engine,
engine            667 drivers/gpu/drm/i915/gt/selftest_lrc.c 		rq = spinner_create_request(&spin_hi, ctx_hi, engine,
engine            682 drivers/gpu/drm/i915/gt/selftest_lrc.c 		engine->schedule(rq, &attr);
engine            752 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine            775 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine            778 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine            781 drivers/gpu/drm/i915/gt/selftest_lrc.c 		engine->execlists.preempt_hang.count = 0;
engine            784 drivers/gpu/drm/i915/gt/selftest_lrc.c 					      a.ctx, engine,
engine            801 drivers/gpu/drm/i915/gt/selftest_lrc.c 					      b.ctx, engine,
engine            828 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (engine->execlists.preempt_hang.count) {
engine            830 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       engine->execlists.preempt_hang.count);
engine            860 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine            893 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine            897 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine            900 drivers/gpu/drm/i915/gt/selftest_lrc.c 		engine->execlists.preempt_hang.count = 0;
engine            903 drivers/gpu/drm/i915/gt/selftest_lrc.c 					      a.ctx, engine,
engine            917 drivers/gpu/drm/i915/gt/selftest_lrc.c 		mod_timer(&engine->execlists.timer, jiffies + HZ);
engine            920 drivers/gpu/drm/i915/gt/selftest_lrc.c 						      b.ctx, engine,
engine            929 drivers/gpu/drm/i915/gt/selftest_lrc.c 			engine->schedule(rq_a, &attr);
engine            942 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (engine->execlists.preempt_hang.count) {
engine            944 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       engine->name,
engine            945 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       engine->execlists.preempt_hang.count,
engine            979 drivers/gpu/drm/i915/gt/selftest_lrc.c static struct i915_request *dummy_request(struct intel_engine_cs *engine)
engine            988 drivers/gpu/drm/i915/gt/selftest_lrc.c 	rq->engine = engine;
engine           1026 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine           1053 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine           1056 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine           1059 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!engine->emit_init_breadcrumb)
engine           1066 drivers/gpu/drm/i915/gt/selftest_lrc.c 			engine->execlists.preempt_hang.count = 0;
engine           1068 drivers/gpu/drm/i915/gt/selftest_lrc.c 			dummy = dummy_request(engine);
engine           1074 drivers/gpu/drm/i915/gt/selftest_lrc.c 							       client[i].ctx, engine,
engine           1092 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       engine->name);
engine           1101 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       engine->name, depth);
engine           1111 drivers/gpu/drm/i915/gt/selftest_lrc.c 			if (engine->execlists.preempt_hang.count) {
engine           1113 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       engine->name,
engine           1114 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       engine->execlists.preempt_hang.count,
engine           1147 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine           1171 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine           1179 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine           1183 drivers/gpu/drm/i915/gt/selftest_lrc.c 					    lo.ctx, engine,
engine           1194 drivers/gpu/drm/i915/gt/selftest_lrc.c 			 __func__, engine->name, ring_size);
engine           1198 drivers/gpu/drm/i915/gt/selftest_lrc.c 			pr_err("Timed out waiting to flush %s\n", engine->name);
engine           1202 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
engine           1209 drivers/gpu/drm/i915/gt/selftest_lrc.c 						    hi.ctx, engine,
engine           1218 drivers/gpu/drm/i915/gt/selftest_lrc.c 						    lo.ctx, engine,
engine           1225 drivers/gpu/drm/i915/gt/selftest_lrc.c 				rq = igt_request_alloc(lo.ctx, engine);
engine           1231 drivers/gpu/drm/i915/gt/selftest_lrc.c 			rq = igt_request_alloc(hi.ctx, engine);
engine           1235 drivers/gpu/drm/i915/gt/selftest_lrc.c 			engine->schedule(rq, &attr);
engine           1244 drivers/gpu/drm/i915/gt/selftest_lrc.c 				intel_engine_dump(engine, &p,
engine           1245 drivers/gpu/drm/i915/gt/selftest_lrc.c 						  "%s\n", engine->name);
engine           1250 drivers/gpu/drm/i915/gt/selftest_lrc.c 			rq = igt_request_alloc(lo.ctx, engine);
engine           1260 drivers/gpu/drm/i915/gt/selftest_lrc.c 				intel_engine_dump(engine, &p,
engine           1261 drivers/gpu/drm/i915/gt/selftest_lrc.c 						  "%s\n", engine->name);
engine           1295 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine           1327 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine           1330 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!intel_engine_has_preemption(engine))
engine           1333 drivers/gpu/drm/i915/gt/selftest_lrc.c 		rq = spinner_create_request(&spin_lo, ctx_lo, engine,
engine           1349 drivers/gpu/drm/i915/gt/selftest_lrc.c 		rq = spinner_create_request(&spin_hi, ctx_hi, engine,
engine           1357 drivers/gpu/drm/i915/gt/selftest_lrc.c 		init_completion(&engine->execlists.preempt_hang.completion);
engine           1358 drivers/gpu/drm/i915/gt/selftest_lrc.c 		engine->execlists.preempt_hang.inject_hang = true;
engine           1362 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (!wait_for_completion_timeout(&engine->execlists.preempt_hang.completion,
engine           1372 drivers/gpu/drm/i915/gt/selftest_lrc.c 		intel_engine_reset(engine, NULL);
engine           1375 drivers/gpu/drm/i915/gt/selftest_lrc.c 		engine->execlists.preempt_hang.inject_hang = false;
engine           1421 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine           1454 drivers/gpu/drm/i915/gt/selftest_lrc.c 	rq = igt_request_alloc(ctx, smoke->engine);
engine           1466 drivers/gpu/drm/i915/gt/selftest_lrc.c 			err = rq->engine->emit_bb_start(rq,
engine           1512 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine           1519 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, smoke->i915, id) {
engine           1521 drivers/gpu/drm/i915/gt/selftest_lrc.c 		arg[id].engine = engine;
engine           1536 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, smoke->i915, id) {
engine           1567 drivers/gpu/drm/i915/gt/selftest_lrc.c 		for_each_engine(smoke->engine, smoke->i915, id) {
engine           1715 drivers/gpu/drm/i915/gt/selftest_lrc.c 	err = igt_live_test_begin(&t, i915, __func__, ve[0]->engine->name);
engine           1753 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       __func__, ve[0]->engine->name,
engine           1758 drivers/gpu/drm/i915/gt/selftest_lrc.c 					  __func__, ve[0]->engine->name,
engine           1780 drivers/gpu/drm/i915/gt/selftest_lrc.c 		nctx, ve[0]->engine->name, ktime_to_ns(times[0]),
engine           1799 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct intel_engine_cs *engine;
engine           1810 drivers/gpu/drm/i915/gt/selftest_lrc.c 	for_each_engine(engine, i915, id) {
engine           1811 drivers/gpu/drm/i915/gt/selftest_lrc.c 		err = nop_virtual_engine(i915, &engine, 1, 1, 0);
engine           1814 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       engine->name, err);
engine           1879 drivers/gpu/drm/i915/gt/selftest_lrc.c 	err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
engine           1901 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       __func__, ve->engine->name,
engine           1906 drivers/gpu/drm/i915/gt/selftest_lrc.c 				  __func__, ve->engine->name,
engine           1915 drivers/gpu/drm/i915/gt/selftest_lrc.c 		if (request[n]->engine != siblings[nsibling - n - 1]) {
engine           1917 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       request[n]->engine->name,
engine           2039 drivers/gpu/drm/i915/gt/selftest_lrc.c 			err = intel_virtual_engine_attach_bond(ve->engine,
engine           2066 drivers/gpu/drm/i915/gt/selftest_lrc.c 							   ve->engine->bond_execute);
engine           2077 drivers/gpu/drm/i915/gt/selftest_lrc.c 			       rq[0]->engine->name);
engine           2089 drivers/gpu/drm/i915/gt/selftest_lrc.c 			if (rq[n + 1]->engine != siblings[n]) {
engine           2092 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       rq[n + 1]->engine->name,
engine           2093 drivers/gpu/drm/i915/gt/selftest_lrc.c 				       rq[0]->engine->name);
engine            109 drivers/gpu/drm/i915/gt/selftest_reset.c 	struct intel_engine_cs *engine;
engine            128 drivers/gpu/drm/i915/gt/selftest_reset.c 	for_each_engine(engine, gt->i915, id) {
engine            129 drivers/gpu/drm/i915/gt/selftest_reset.c 		tasklet_disable_nosync(&engine->execlists.tasklet);
engine            130 drivers/gpu/drm/i915/gt/selftest_reset.c 		intel_engine_pm_get(engine);
engine            134 drivers/gpu/drm/i915/gt/selftest_reset.c 				  engine->name, p->name);
engine            137 drivers/gpu/drm/i915/gt/selftest_reset.c 			err = intel_engine_reset(engine, NULL);
engine            142 drivers/gpu/drm/i915/gt/selftest_reset.c 				       engine->name, p->name);
engine            147 drivers/gpu/drm/i915/gt/selftest_reset.c 		intel_engine_pm_put(engine);
engine            148 drivers/gpu/drm/i915/gt/selftest_reset.c 		tasklet_enable(&engine->execlists.tasklet);
engine            447 drivers/gpu/drm/i915/gt/selftest_timeline.c tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
engine            460 drivers/gpu/drm/i915/gt/selftest_timeline.c 	rq = i915_request_create(engine->kernel_context);
engine            501 drivers/gpu/drm/i915/gt/selftest_timeline.c 	struct intel_engine_cs *engine;
engine            522 drivers/gpu/drm/i915/gt/selftest_timeline.c 	for_each_engine(engine, i915, id) {
engine            523 drivers/gpu/drm/i915/gt/selftest_timeline.c 		if (!intel_engine_can_store_dword(engine))
engine            536 drivers/gpu/drm/i915/gt/selftest_timeline.c 			rq = tl_write(tl, engine, count);
engine            576 drivers/gpu/drm/i915/gt/selftest_timeline.c 	struct intel_engine_cs *engine;
engine            599 drivers/gpu/drm/i915/gt/selftest_timeline.c 		for_each_engine(engine, i915, id) {
engine            603 drivers/gpu/drm/i915/gt/selftest_timeline.c 			if (!intel_engine_can_store_dword(engine))
engine            612 drivers/gpu/drm/i915/gt/selftest_timeline.c 			rq = tl_write(tl, engine, count);
engine            650 drivers/gpu/drm/i915/gt/selftest_timeline.c 	struct intel_engine_cs *engine;
engine            676 drivers/gpu/drm/i915/gt/selftest_timeline.c 	for_each_engine(engine, i915, id) {
engine            681 drivers/gpu/drm/i915/gt/selftest_timeline.c 		if (!intel_engine_can_store_dword(engine))
engine            684 drivers/gpu/drm/i915/gt/selftest_timeline.c 		rq = i915_request_create(engine->kernel_context);
engine            766 drivers/gpu/drm/i915/gt/selftest_timeline.c 	struct intel_engine_cs *engine;
engine            782 drivers/gpu/drm/i915/gt/selftest_timeline.c 	for_each_engine(engine, i915, id) {
engine            785 drivers/gpu/drm/i915/gt/selftest_timeline.c 		if (!intel_engine_can_store_dword(engine))
engine            798 drivers/gpu/drm/i915/gt/selftest_timeline.c 			rq = tl_write(tl, engine, count);
engine             33 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	} engine[I915_NUM_ENGINES];
engine             39 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	struct intel_engine_cs *engine;
engine             48 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for_each_engine(engine, i915, id) {
engine             49 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		struct i915_wa_list *wal = &lists->engine[id].wa_list;
engine             51 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		wa_init_start(wal, "REF", engine->name);
engine             52 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		engine_init_workarounds(engine, wal);
engine             55 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		__intel_engine_init_ctx_wa(engine,
engine             56 drivers/gpu/drm/i915/gt/selftest_workarounds.c 					   &lists->engine[id].ctx_wa_list,
engine             64 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	struct intel_engine_cs *engine;
engine             67 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for_each_engine(engine, i915, id)
engine             68 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		intel_wa_list_free(&lists->engine[id].wa_list);
engine             74 drivers/gpu/drm/i915/gt/selftest_workarounds.c read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
engine             76 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	const u32 base = engine->mmio_base;
engine             84 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
engine             99 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);
engine            109 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	rq = igt_request_alloc(ctx, engine);
engine            156 drivers/gpu/drm/i915/gt/selftest_workarounds.c get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
engine            158 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	i915_reg_t reg = i < engine->whitelist.count ?
engine            159 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			 engine->whitelist.list[i].reg :
engine            160 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			 RING_NOPID(engine->mmio_base);
engine            166 drivers/gpu/drm/i915/gt/selftest_workarounds.c print_results(const struct intel_engine_cs *engine, const u32 *results)
engine            171 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		u32 expected = get_whitelist_reg(engine, i);
engine            180 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			   struct intel_engine_cs *engine)
engine            188 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	results = read_nonprivs(ctx, engine);
engine            209 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		u32 expected = get_whitelist_reg(engine, i);
engine            213 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			print_results(engine, vaddr);
engine            228 drivers/gpu/drm/i915/gt/selftest_workarounds.c static int do_device_reset(struct intel_engine_cs *engine)
engine            230 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	intel_gt_reset(engine->gt, engine->mask, "live_workarounds");
engine            234 drivers/gpu/drm/i915/gt/selftest_workarounds.c static int do_engine_reset(struct intel_engine_cs *engine)
engine            236 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	return intel_engine_reset(engine, "live_workarounds");
engine            240 drivers/gpu/drm/i915/gt/selftest_workarounds.c switch_to_scratch_context(struct intel_engine_cs *engine,
engine            249 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	ctx = kernel_context(engine->i915);
engine            255 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);
engine            259 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	with_intel_runtime_pm(&engine->i915->runtime_pm, wakeref)
engine            285 drivers/gpu/drm/i915/gt/selftest_workarounds.c static int check_whitelist_across_reset(struct intel_engine_cs *engine,
engine            289 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	struct drm_i915_private *i915 = engine->i915;
engine            296 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		engine->whitelist.count, engine->name, name);
engine            302 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	err = igt_spinner_init(&spin, engine->gt);
engine            306 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	err = check_whitelist(ctx, engine);
engine            312 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	err = switch_to_scratch_context(engine, &spin);
engine            317 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = reset(engine);
engine            326 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	err = check_whitelist(ctx, engine);
engine            341 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	err = check_whitelist(ctx, engine);
engine            395 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool wo_register(struct intel_engine_cs *engine, u32 reg)
engine            397 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
engine            422 drivers/gpu/drm/i915/gt/selftest_workarounds.c static int whitelist_writable_count(struct intel_engine_cs *engine)
engine            424 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	int count = engine->whitelist.count;
engine            427 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for (i = 0; i < engine->whitelist.count; i++) {
engine            428 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
engine            438 drivers/gpu/drm/i915/gt/selftest_workarounds.c 				 struct intel_engine_cs *engine)
engine            481 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for (i = 0; i < engine->whitelist.count; i++) {
engine            482 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
engine            490 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		if (wo_register(engine, reg))
engine            501 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			 engine->name, reg);
engine            554 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		intel_gt_chipset_flush(engine->gt);
engine            556 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		rq = igt_request_alloc(ctx, engine);
engine            562 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
engine            563 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			err = engine->emit_init_breadcrumb(rq);
engine            568 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = engine->emit_bb_start(rq,
engine            581 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			       engine->name, reg);
engine            599 drivers/gpu/drm/i915/gt/selftest_workarounds.c 				       engine->name, reg);
engine            629 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			       engine->name, err, reg);
engine            633 drivers/gpu/drm/i915/gt/selftest_workarounds.c 					engine->name, reg, results[0]);
engine            636 drivers/gpu/drm/i915/gt/selftest_workarounds.c 					engine->name, reg, results[0], rsvd);
engine            683 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	struct intel_engine_cs *engine;
engine            711 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for_each_engine(engine, i915, id) {
engine            712 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		if (engine->whitelist.count == 0)
engine            715 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = check_dirty_whitelist(ctx, engine);
engine            732 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	struct intel_engine_cs *engine = i915->engine[RCS0];
engine            737 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	if (!engine || engine->whitelist.count == 0)
engine            743 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = check_whitelist_across_reset(engine,
engine            751 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = check_whitelist_across_reset(engine,
engine            764 drivers/gpu/drm/i915/gt/selftest_workarounds.c 				      struct intel_engine_cs *engine,
engine            771 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	rq = igt_request_alloc(ctx, engine);
engine            779 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
engine            785 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for (i = 0; i < engine->whitelist.count; i++) {
engine            787 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
engine            809 drivers/gpu/drm/i915/gt/selftest_workarounds.c 				       struct intel_engine_cs *engine)
engine            826 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	*cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));
engine            827 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for (i = 0; i < engine->whitelist.count; i++) {
engine            828 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
engine            839 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	intel_gt_chipset_flush(engine->gt);
engine            841 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	rq = igt_request_alloc(ctx, engine);
engine            847 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
engine            848 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = engine->emit_init_breadcrumb(rq);
engine            854 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	err = engine->emit_bb_start(rq, batch->node.start, 0, 0);
engine            901 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool result_eq(struct intel_engine_cs *engine,
engine            904 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	if (a != b && !pardon_reg(engine->i915, reg)) {
engine            923 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool result_neq(struct intel_engine_cs *engine,
engine            926 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	if (a == b && !writeonly_reg(engine->i915, reg)) {
engine            936 drivers/gpu/drm/i915/gt/selftest_workarounds.c check_whitelisted_registers(struct intel_engine_cs *engine,
engine            939 drivers/gpu/drm/i915/gt/selftest_workarounds.c 			    bool (*fn)(struct intel_engine_cs *engine,
engine            957 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for (i = 0; i < engine->whitelist.count; i++) {
engine            958 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		const struct i915_wa *wa = &engine->whitelist.list[i];
engine            964 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		if (!fn(engine, a[i], b[i], wa->reg))
engine            981 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	struct intel_engine_cs *engine;
engine           1023 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	for_each_engine(engine, i915, id) {
engine           1024 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		if (!whitelist_writable_count(engine))
engine           1028 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = read_whitelisted_registers(client[0].ctx, engine,
engine           1034 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = scrub_whitelisted_registers(client[0].ctx, engine);
engine           1039 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = read_whitelisted_registers(client[1].ctx, engine,
engine           1045 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = check_whitelisted_registers(engine,
engine           1053 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = read_whitelisted_registers(client[0].ctx, engine,
engine           1059 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		err = check_whitelisted_registers(engine,
engine           1095 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		enum intel_engine_id id = ce->engine->id;
engine           1098 drivers/gpu/drm/i915/gt/selftest_workarounds.c 					    &lists->engine[id].wa_list,
engine           1102 drivers/gpu/drm/i915/gt/selftest_workarounds.c 					    &lists->engine[id].ctx_wa_list,
engine           1178 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		struct intel_engine_cs *engine = ce->engine;
engine           1181 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		pr_info("Verifying after %s reset...\n", engine->name);
engine           1189 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		intel_engine_reset(engine, "live_workarounds");
engine           1197 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		ret = igt_spinner_init(&spin, engine->gt);
engine           1217 drivers/gpu/drm/i915/gt/selftest_workarounds.c 		intel_engine_reset(engine, "live_workarounds");
engine            519 drivers/gpu/drm/i915/gt/uc/intel_guc.c 			   struct intel_engine_cs *engine)
engine            526 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	data[1] = engine->guc_id;
engine            198 drivers/gpu/drm/i915/gt/uc/intel_guc.h 			   struct intel_engine_cs *engine);
engine            466 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_cs *engine = rq->engine;
engine            470 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	guc_wq_item_append(client, engine->guc_id, ctx_desc,
engine            490 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_submit(struct intel_engine_cs *engine,
engine            494 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_guc *guc = &engine->gt->uc.guc;
engine            525 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	intel_gt_pm_get(rq->engine->gt);
engine            533 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	intel_gt_pm_put(rq->engine->gt);
engine            537 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void __guc_dequeue(struct intel_engine_cs *engine)
engine            539 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            547 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	lockdep_assert_held(&engine->active.lock);
engine            592 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 		guc_submit(engine, first, port);
engine            599 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
engine            600 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            604 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            618 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	__guc_dequeue(engine);
engine            620 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            623 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_reset_prepare(struct intel_engine_cs *engine)
engine            625 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            627 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	GEM_TRACE("%s\n", engine->name);
engine            654 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_reset(struct intel_engine_cs *engine, bool stalled)
engine            656 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            660 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            673 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	intel_lr_context_reset(engine, rq->hw_context, rq->head, stalled);
engine            676 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            679 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_cancel_requests(struct intel_engine_cs *engine)
engine            681 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            686 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	GEM_TRACE("%s\n", engine->name);
engine            702 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            708 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	list_for_each_entry(rq, &engine->active.requests, sched.link) {
engine            736 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            739 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_reset_finish(struct intel_engine_cs *engine)
engine            741 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine            747 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	GEM_TRACE("%s: depth->%d\n", engine->name,
engine           1009 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_cs *engine;
engine           1017 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	for_each_engine(engine, gt->i915, id)
engine           1018 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
engine           1055 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_cs *engine;
engine           1065 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	for_each_engine(engine, gt->i915, id)
engine           1066 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
engine           1077 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_set_default_submission(struct intel_engine_cs *engine)
engine           1090 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	intel_execlists_set_default_submission(engine);
engine           1092 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->execlists.tasklet.func = guc_submission_tasklet;
engine           1095 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->park = engine->unpark = NULL;
engine           1097 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->reset.prepare = guc_reset_prepare;
engine           1098 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->reset.reset = guc_reset;
engine           1099 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->reset.finish = guc_reset_finish;
engine           1101 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->cancel_requests = guc_cancel_requests;
engine           1103 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
engine           1104 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
engine           1112 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	GEM_BUG_ON(engine->irq_enable || engine->irq_disable);
engine           1118 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	struct intel_engine_cs *engine;
engine           1135 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.inflight) *
engine           1148 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	for_each_engine(engine, gt->i915, id) {
engine           1149 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 		engine->set_default_submission = guc_set_default_submission;
engine           1150 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 		engine->set_default_submission(engine);
engine            851 drivers/gpu/drm/i915/gvt/cmd_parser.c 	ring_base = dev_priv->engine[s->ring_id]->mmio_base;
engine            165 drivers/gpu/drm/i915/gvt/debugfs.c 		struct intel_engine_cs *engine;
engine            167 drivers/gpu/drm/i915/gvt/debugfs.c 		engine = dev_priv->engine[id];
engine            168 drivers/gpu/drm/i915/gvt/debugfs.c 		if (engine && (val & (1 << id))) {
engine            169 drivers/gpu/drm/i915/gvt/debugfs.c 			len = snprintf(s, 4, "%d, ", engine->id);
engine             43 drivers/gpu/drm/i915/gvt/execlist.c 	(gvt->dev_priv->engine[ring_id]->mmio_base + (offset))
engine            533 drivers/gpu/drm/i915/gvt/execlist.c 	struct intel_engine_cs *engine;
engine            537 drivers/gpu/drm/i915/gvt/execlist.c 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
engine            538 drivers/gpu/drm/i915/gvt/execlist.c 		kfree(s->ring_scan_buffer[engine->id]);
engine            539 drivers/gpu/drm/i915/gvt/execlist.c 		s->ring_scan_buffer[engine->id] = NULL;
engine            540 drivers/gpu/drm/i915/gvt/execlist.c 		s->ring_scan_buffer_size[engine->id] = 0;
engine            548 drivers/gpu/drm/i915/gvt/execlist.c 	struct intel_engine_cs *engine;
engine            551 drivers/gpu/drm/i915/gvt/execlist.c 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
engine            552 drivers/gpu/drm/i915/gvt/execlist.c 		init_vgpu_execlist(vgpu, engine->id);
engine            156 drivers/gpu/drm/i915/gvt/handlers.c 	struct intel_engine_cs *engine;
engine            159 drivers/gpu/drm/i915/gvt/handlers.c 	for_each_engine(engine, gvt->dev_priv, id) {
engine            160 drivers/gpu/drm/i915/gvt/handlers.c 		if (engine->mmio_base == offset)
engine            523 drivers/gpu/drm/i915/gvt/handlers.c 	ring_base = dev_priv->engine[ring_id]->mmio_base;
engine           1651 drivers/gpu/drm/i915/gvt/handlers.c 		ring_base = dev_priv->engine[ring_id]->mmio_base;
engine            199 drivers/gpu/drm/i915/gvt/mmio_context.c 	int ring_id = req->engine->id;
engine            205 drivers/gpu/drm/i915/gvt/mmio_context.c 	ret = req->engine->emit_flush(req, EMIT_BARRIER);
engine            230 drivers/gpu/drm/i915/gvt/mmio_context.c 	ret = req->engine->emit_flush(req, EMIT_BARRIER);
engine            254 drivers/gpu/drm/i915/gvt/mmio_context.c 			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);
engine            281 drivers/gpu/drm/i915/gvt/mmio_context.c 			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);
engine            315 drivers/gpu/drm/i915/gvt/mmio_context.c 	if (req->engine->id != RCS0)
engine             40 drivers/gpu/drm/i915/gvt/sched_policy.c 	struct intel_engine_cs *engine;
engine             42 drivers/gpu/drm/i915/gvt/sched_policy.c 	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
engine            136 drivers/gpu/drm/i915/gvt/sched_policy.c 	struct intel_engine_cs *engine;
engine            155 drivers/gpu/drm/i915/gvt/sched_policy.c 	for_each_engine(engine, gvt->dev_priv, i) {
engine            172 drivers/gpu/drm/i915/gvt/sched_policy.c 	for_each_engine(engine, gvt->dev_priv, i)
engine            180 drivers/gpu/drm/i915/gvt/scheduler.c 	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
engine            215 drivers/gpu/drm/i915/gvt/scheduler.c 	u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
engine            231 drivers/gpu/drm/i915/gvt/scheduler.c 				shadow_ctx_notifier_block[req->engine->id]);
engine            233 drivers/gpu/drm/i915/gvt/scheduler.c 	enum intel_engine_id ring_id = req->engine->id;
engine            322 drivers/gpu/drm/i915/gvt/scheduler.c 	if (req->engine->emit_init_breadcrumb) {
engine            323 drivers/gpu/drm/i915/gvt/scheduler.c 		err = req->engine->emit_init_breadcrumb(req);
engine            581 drivers/gpu/drm/i915/gvt/scheduler.c 	ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
engine            814 drivers/gpu/drm/i915/gvt/scheduler.c 	gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
engine            830 drivers/gpu/drm/i915/gvt/scheduler.c 	ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
engine            834 drivers/gpu/drm/i915/gvt/scheduler.c 	context_page_num = rq->engine->context_size;
engine            837 drivers/gpu/drm/i915/gvt/scheduler.c 	if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
engine            889 drivers/gpu/drm/i915/gvt/scheduler.c 	struct intel_engine_cs *engine;
engine            894 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
engine            896 drivers/gpu/drm/i915/gvt/scheduler.c 			&s->workload_q_head[engine->id], list) {
engine            900 drivers/gpu/drm/i915/gvt/scheduler.c 		clear_bit(engine->id, s->shadow_ctx_desc_updated);
engine           1087 drivers/gpu/drm/i915/gvt/scheduler.c 	struct intel_engine_cs *engine;
engine           1092 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine(engine, gvt->dev_priv, i) {
engine           1094 drivers/gpu/drm/i915/gvt/scheduler.c 					&engine->context_status_notifier,
engine           1104 drivers/gpu/drm/i915/gvt/scheduler.c 	struct intel_engine_cs *engine;
engine           1112 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine(engine, gvt->dev_priv, i) {
engine           1134 drivers/gpu/drm/i915/gvt/scheduler.c 		atomic_notifier_chain_register(&engine->context_status_notifier,
engine           1173 drivers/gpu/drm/i915/gvt/scheduler.c 	struct intel_engine_cs *engine;
engine           1179 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine(engine, vgpu->gvt->dev_priv, id)
engine           1238 drivers/gpu/drm/i915/gvt/scheduler.c 	struct intel_engine_cs *engine;
engine           1255 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine(engine, i915, i) {
engine           1261 drivers/gpu/drm/i915/gvt/scheduler.c 		ce = intel_context_create(ctx, engine);
engine           1304 drivers/gpu/drm/i915/gvt/scheduler.c 	for_each_engine(engine, i915, i) {
engine            261 drivers/gpu/drm/i915/i915_active.c 				   struct intel_engine_cs *engine)
engine            267 drivers/gpu/drm/i915/i915_active.c 	GEM_BUG_ON(node->timeline != engine->kernel_context->timeline->fence_context);
engine            284 drivers/gpu/drm/i915/i915_active.c 	llist_for_each_safe(pos, next, llist_del_all(&engine->barrier_tasks)) {
engine            296 drivers/gpu/drm/i915/i915_active.c 		llist_add_batch(head, tail, &engine->barrier_tasks);
engine            547 drivers/gpu/drm/i915/i915_active.c 		struct intel_engine_cs *engine;
engine            565 drivers/gpu/drm/i915/i915_active.c 		engine = __barrier_to_engine(node);
engine            568 drivers/gpu/drm/i915/i915_active.c 		    ____active_del_barrier(ref, node, engine))
engine            586 drivers/gpu/drm/i915/i915_active.c 					    struct intel_engine_cs *engine)
engine            588 drivers/gpu/drm/i915/i915_active.c 	struct drm_i915_private *i915 = engine->i915;
engine            589 drivers/gpu/drm/i915/i915_active.c 	intel_engine_mask_t tmp, mask = engine->mask;
engine            601 drivers/gpu/drm/i915/i915_active.c 	for_each_engine_masked(engine, i915, mask, tmp) {
engine            602 drivers/gpu/drm/i915/i915_active.c 		u64 idx = engine->kernel_context->timeline->fence_context;
engine            615 drivers/gpu/drm/i915/i915_active.c 				&engine->kernel_context->timeline->mutex;
engine            634 drivers/gpu/drm/i915/i915_active.c 			node->base.link.prev = (void *)engine;
engine            638 drivers/gpu/drm/i915/i915_active.c 		GEM_BUG_ON(barrier_to_engine(node) != engine);
engine            640 drivers/gpu/drm/i915/i915_active.c 		intel_engine_pm_get(engine);
engine            672 drivers/gpu/drm/i915/i915_active.c 		struct intel_engine_cs *engine = barrier_to_engine(node);
engine            691 drivers/gpu/drm/i915/i915_active.c 		llist_add(barrier_to_ll(node), &engine->barrier_tasks);
engine            692 drivers/gpu/drm/i915/i915_active.c 		intel_engine_pm_put(engine);
engine            699 drivers/gpu/drm/i915/i915_active.c 	struct intel_engine_cs *engine = rq->engine;
engine            702 drivers/gpu/drm/i915/i915_active.c 	GEM_BUG_ON(intel_engine_is_virtual(engine));
engine            703 drivers/gpu/drm/i915/i915_active.c 	GEM_BUG_ON(rq->timeline != engine->kernel_context->timeline);
engine            710 drivers/gpu/drm/i915/i915_active.c 	llist_for_each_safe(node, next, llist_del_all(&engine->barrier_tasks)) {
engine            403 drivers/gpu/drm/i915/i915_active.h 					    struct intel_engine_cs *engine);
engine            785 drivers/gpu/drm/i915/i915_cmd_parser.c static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
engine            808 drivers/gpu/drm/i915/i915_cmd_parser.c 					  engine->name, engine->id,
engine            820 drivers/gpu/drm/i915/i915_cmd_parser.c static bool check_sorted(const struct intel_engine_cs *engine,
engine            834 drivers/gpu/drm/i915/i915_cmd_parser.c 				  engine->name, engine->id,
engine            845 drivers/gpu/drm/i915/i915_cmd_parser.c static bool validate_regs_sorted(struct intel_engine_cs *engine)
engine            850 drivers/gpu/drm/i915/i915_cmd_parser.c 	for (i = 0; i < engine->reg_table_count; i++) {
engine            851 drivers/gpu/drm/i915/i915_cmd_parser.c 		table = &engine->reg_tables[i];
engine            852 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (!check_sorted(engine, table->regs, table->num_regs))
engine            887 drivers/gpu/drm/i915/i915_cmd_parser.c static int init_hash_table(struct intel_engine_cs *engine,
engine            893 drivers/gpu/drm/i915/i915_cmd_parser.c 	hash_init(engine->cmd_hash);
engine            908 drivers/gpu/drm/i915/i915_cmd_parser.c 			hash_add(engine->cmd_hash, &desc_node->node,
engine            916 drivers/gpu/drm/i915/i915_cmd_parser.c static void fini_hash_table(struct intel_engine_cs *engine)
engine            922 drivers/gpu/drm/i915/i915_cmd_parser.c 	hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
engine            936 drivers/gpu/drm/i915/i915_cmd_parser.c void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
engine            942 drivers/gpu/drm/i915/i915_cmd_parser.c 	if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) &&
engine            943 drivers/gpu/drm/i915/i915_cmd_parser.c 					  engine->class == COPY_ENGINE_CLASS))
engine            946 drivers/gpu/drm/i915/i915_cmd_parser.c 	switch (engine->class) {
engine            948 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (IS_HASWELL(engine->i915)) {
engine            957 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (IS_HASWELL(engine->i915)) {
engine            958 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_tables = hsw_render_reg_tables;
engine            959 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
engine            961 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_tables = ivb_render_reg_tables;
engine            962 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
engine            964 drivers/gpu/drm/i915/i915_cmd_parser.c 		engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
engine            969 drivers/gpu/drm/i915/i915_cmd_parser.c 		engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
engine            972 drivers/gpu/drm/i915/i915_cmd_parser.c 		engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
engine            973 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (IS_GEN(engine->i915, 9)) {
engine            976 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->get_cmd_length_mask =
engine            980 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;
engine            981 drivers/gpu/drm/i915/i915_cmd_parser.c 		} else if (IS_HASWELL(engine->i915)) {
engine            989 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (IS_GEN(engine->i915, 9)) {
engine            990 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_tables = gen9_blt_reg_tables;
engine            991 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_table_count =
engine            993 drivers/gpu/drm/i915/i915_cmd_parser.c 		} else if (IS_HASWELL(engine->i915)) {
engine            994 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_tables = hsw_blt_reg_tables;
engine            995 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
engine            997 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_tables = ivb_blt_reg_tables;
engine            998 drivers/gpu/drm/i915/i915_cmd_parser.c 			engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
engine           1005 drivers/gpu/drm/i915/i915_cmd_parser.c 		engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
engine           1008 drivers/gpu/drm/i915/i915_cmd_parser.c 		MISSING_CASE(engine->class);
engine           1012 drivers/gpu/drm/i915/i915_cmd_parser.c 	if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
engine           1014 drivers/gpu/drm/i915/i915_cmd_parser.c 			  engine->name);
engine           1017 drivers/gpu/drm/i915/i915_cmd_parser.c 	if (!validate_regs_sorted(engine)) {
engine           1018 drivers/gpu/drm/i915/i915_cmd_parser.c 		DRM_ERROR("%s: registers are not sorted\n", engine->name);
engine           1022 drivers/gpu/drm/i915/i915_cmd_parser.c 	ret = init_hash_table(engine, cmd_tables, cmd_table_count);
engine           1024 drivers/gpu/drm/i915/i915_cmd_parser.c 		DRM_ERROR("%s: initialised failed!\n", engine->name);
engine           1025 drivers/gpu/drm/i915/i915_cmd_parser.c 		fini_hash_table(engine);
engine           1029 drivers/gpu/drm/i915/i915_cmd_parser.c 	engine->flags |= I915_ENGINE_USING_CMD_PARSER;
engine           1039 drivers/gpu/drm/i915/i915_cmd_parser.c void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
engine           1041 drivers/gpu/drm/i915/i915_cmd_parser.c 	if (!intel_engine_using_cmd_parser(engine))
engine           1044 drivers/gpu/drm/i915/i915_cmd_parser.c 	fini_hash_table(engine);
engine           1048 drivers/gpu/drm/i915/i915_cmd_parser.c find_cmd_in_table(struct intel_engine_cs *engine,
engine           1053 drivers/gpu/drm/i915/i915_cmd_parser.c 	hash_for_each_possible(engine->cmd_hash, desc_node, node,
engine           1072 drivers/gpu/drm/i915/i915_cmd_parser.c find_cmd(struct intel_engine_cs *engine,
engine           1082 drivers/gpu/drm/i915/i915_cmd_parser.c 	desc = find_cmd_in_table(engine, cmd_header);
engine           1086 drivers/gpu/drm/i915/i915_cmd_parser.c 	mask = engine->get_cmd_length_mask(cmd_header);
engine           1115 drivers/gpu/drm/i915/i915_cmd_parser.c find_reg(const struct intel_engine_cs *engine, u32 addr)
engine           1117 drivers/gpu/drm/i915/i915_cmd_parser.c 	const struct drm_i915_reg_table *table = engine->reg_tables;
engine           1119 drivers/gpu/drm/i915/i915_cmd_parser.c 	int count = engine->reg_table_count;
engine           1206 drivers/gpu/drm/i915/i915_cmd_parser.c static bool check_cmd(const struct intel_engine_cs *engine,
engine           1231 drivers/gpu/drm/i915/i915_cmd_parser.c 				find_reg(engine, reg_addr);
engine           1235 drivers/gpu/drm/i915/i915_cmd_parser.c 						 reg_addr, *cmd, engine->name);
engine           1288 drivers/gpu/drm/i915/i915_cmd_parser.c 						 *cmd, engine->name);
engine           1300 drivers/gpu/drm/i915/i915_cmd_parser.c 						 dword, engine->name);
engine           1424 drivers/gpu/drm/i915/i915_cmd_parser.c 			    struct intel_engine_cs *engine,
engine           1460 drivers/gpu/drm/i915/i915_cmd_parser.c 		desc = find_cmd(engine, *cmd, desc, &default_desc);
engine           1482 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (!check_cmd(engine, desc, cmd, length)) {
engine           1531 drivers/gpu/drm/i915/i915_cmd_parser.c 	struct intel_engine_cs *engine;
engine           1535 drivers/gpu/drm/i915/i915_cmd_parser.c 	for_each_uabi_engine(engine, dev_priv) {
engine           1536 drivers/gpu/drm/i915/i915_cmd_parser.c 		if (intel_engine_using_cmd_parser(engine)) {
engine            139 drivers/gpu/drm/i915/i915_debugfs.c 	struct intel_engine_cs *engine;
engine            227 drivers/gpu/drm/i915/i915_debugfs.c 	engine = i915_gem_object_last_write_engine(obj);
engine            228 drivers/gpu/drm/i915/i915_debugfs.c 	if (engine)
engine            229 drivers/gpu/drm/i915/i915_debugfs.c 		seq_printf(m, " (%s)", engine->name);
engine            431 drivers/gpu/drm/i915/i915_debugfs.c 	struct intel_engine_cs *engine;
engine            634 drivers/gpu/drm/i915/i915_debugfs.c 		for_each_uabi_engine(engine, dev_priv) {
engine            637 drivers/gpu/drm/i915/i915_debugfs.c 				   engine->name, ENGINE_READ(engine, RING_IMR));
engine           1027 drivers/gpu/drm/i915/i915_debugfs.c 	struct intel_engine_cs *engine;
engine           1054 drivers/gpu/drm/i915/i915_debugfs.c 		for_each_engine(engine, i915, id) {
engine           1058 drivers/gpu/drm/i915/i915_debugfs.c 				   engine->name,
engine           1060 drivers/gpu/drm/i915/i915_debugfs.c 						    engine->hangcheck.action_timestamp));
engine           1063 drivers/gpu/drm/i915/i915_debugfs.c 				   (long long)engine->hangcheck.acthd,
engine           1064 drivers/gpu/drm/i915/i915_debugfs.c 				   intel_engine_get_active_head(engine));
engine           1066 drivers/gpu/drm/i915/i915_debugfs.c 			intel_engine_get_instdone(engine, &instdone);
engine           1073 drivers/gpu/drm/i915/i915_debugfs.c 					   &engine->hangcheck.instdone);
engine           1606 drivers/gpu/drm/i915/i915_debugfs.c 				seq_printf(m, "%s: ", ce->engine->name);
engine           1924 drivers/gpu/drm/i915/i915_debugfs.c 		struct intel_engine_cs *engine;
engine           1946 drivers/gpu/drm/i915/i915_debugfs.c 		for_each_uabi_engine(engine, dev_priv) {
engine           1947 drivers/gpu/drm/i915/i915_debugfs.c 			u32 guc_engine_id = engine->guc_id;
engine           1951 drivers/gpu/drm/i915/i915_debugfs.c 			seq_printf(m, "\t%s LRC:\n", engine->name);
engine           2783 drivers/gpu/drm/i915/i915_debugfs.c 	struct intel_engine_cs *engine;
engine           2796 drivers/gpu/drm/i915/i915_debugfs.c 	for_each_uabi_engine(engine, dev_priv)
engine           2797 drivers/gpu/drm/i915/i915_debugfs.c 		intel_engine_dump(engine, &p, "%s\n", engine->name);
engine           2876 drivers/gpu/drm/i915/i915_debugfs.c 	struct intel_engine_cs *engine;
engine           2878 drivers/gpu/drm/i915/i915_debugfs.c 	for_each_uabi_engine(engine, i915) {
engine           2879 drivers/gpu/drm/i915/i915_debugfs.c 		const struct i915_wa_list *wal = &engine->ctx_wa_list;
engine           2888 drivers/gpu/drm/i915/i915_debugfs.c 			   engine->name, count);
engine           1350 drivers/gpu/drm/i915/i915_drv.h 	struct intel_engine_cs *engine[I915_NUM_ENGINES];
engine           1796 drivers/gpu/drm/i915/i915_drv.h 		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
engine           1802 drivers/gpu/drm/i915/i915_drv.h 	     ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
engine           2225 drivers/gpu/drm/i915/i915_drv.h void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
engine           2329 drivers/gpu/drm/i915/i915_drv.h 					  struct intel_engine_cs *engine)
engine           2331 drivers/gpu/drm/i915/i915_drv.h 	return atomic_read(&error->reset_engine_count[engine->uabi_class]);
engine           2413 drivers/gpu/drm/i915/i915_drv.h void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
engine           2414 drivers/gpu/drm/i915/i915_drv.h void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
engine           2416 drivers/gpu/drm/i915/i915_drv.h 			    struct intel_engine_cs *engine,
engine           1260 drivers/gpu/drm/i915/i915_gem.c 	struct intel_engine_cs *engine;
engine           1273 drivers/gpu/drm/i915/i915_gem.c 	for_each_engine(engine, i915, id) {
engine           1278 drivers/gpu/drm/i915/i915_gem.c 		GEM_BUG_ON(!engine->kernel_context);
engine           1279 drivers/gpu/drm/i915/i915_gem.c 		engine->serial++; /* force the kernel context switch */
engine           1281 drivers/gpu/drm/i915/i915_gem.c 		ce = intel_context_create(i915->kernel_context, engine);
engine           1367 drivers/gpu/drm/i915/i915_gem.c 		rq->engine->default_state = i915_gem_object_get(state->obj);
engine           1408 drivers/gpu/drm/i915/i915_gem.c 	struct intel_engine_cs *engine;
engine           1415 drivers/gpu/drm/i915/i915_gem.c 	for_each_engine(engine, i915, id) {
engine           1416 drivers/gpu/drm/i915/i915_gem.c 		if (intel_engine_verify_workarounds(engine, "load"))
engine           1555 drivers/gpu/drm/i915/i915_gem_gtt.c 	struct intel_engine_cs *engine;
engine           1570 drivers/gpu/drm/i915/i915_gem_gtt.c 	for_each_engine(engine, i915, id) {
engine           1572 drivers/gpu/drm/i915/i915_gem_gtt.c 		ENGINE_WRITE(engine,
engine            430 drivers/gpu/drm/i915/i915_gpu_error.c 	if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
engine            484 drivers/gpu/drm/i915/i915_gpu_error.c 	err_printf(m, "%s command stream:\n", ee->engine->name);
engine            560 drivers/gpu/drm/i915/i915_gpu_error.c 			    const struct intel_engine_cs *engine,
engine            572 drivers/gpu/drm/i915/i915_gpu_error.c 			   engine ? engine->name : "global", name,
engine            684 drivers/gpu/drm/i915/i915_gpu_error.c 	for (ee = error->engine; ee; ee = ee->next)
engine            686 drivers/gpu/drm/i915/i915_gpu_error.c 			   ee->engine->name,
engine            737 drivers/gpu/drm/i915/i915_gpu_error.c 	for (ee = error->engine; ee; ee = ee->next)
engine            740 drivers/gpu/drm/i915/i915_gpu_error.c 	for (ee = error->engine; ee; ee = ee->next) {
engine            745 drivers/gpu/drm/i915/i915_gpu_error.c 			err_puts(m, ee->engine->name);
engine            753 drivers/gpu/drm/i915/i915_gpu_error.c 			print_error_obj(m, ee->engine, NULL, obj);
engine            757 drivers/gpu/drm/i915/i915_gpu_error.c 			print_error_obj(m, ee->engine, "user", ee->user_bo[j]);
engine            761 drivers/gpu/drm/i915/i915_gpu_error.c 				   ee->engine->name,
engine            769 drivers/gpu/drm/i915/i915_gpu_error.c 		print_error_obj(m, ee->engine, "ringbuffer", ee->ringbuffer);
engine            770 drivers/gpu/drm/i915/i915_gpu_error.c 		print_error_obj(m, ee->engine, "HW Status", ee->hws_page);
engine            771 drivers/gpu/drm/i915/i915_gpu_error.c 		print_error_obj(m, ee->engine, "HW context", ee->ctx);
engine            772 drivers/gpu/drm/i915/i915_gpu_error.c 		print_error_obj(m, ee->engine, "WA context", ee->wa_ctx);
engine            773 drivers/gpu/drm/i915/i915_gpu_error.c 		print_error_obj(m, ee->engine,
engine            775 drivers/gpu/drm/i915/i915_gpu_error.c 		print_error_obj(m, ee->engine,
engine            926 drivers/gpu/drm/i915/i915_gpu_error.c 	while (error->engine) {
engine            927 drivers/gpu/drm/i915/i915_gpu_error.c 		struct drm_i915_error_engine *ee = error->engine;
engine            929 drivers/gpu/drm/i915/i915_gpu_error.c 		error->engine = ee->next;
engine           1027 drivers/gpu/drm/i915/i915_gpu_error.c 	const struct drm_i915_error_engine *ee = error->engine;
engine           1063 drivers/gpu/drm/i915/i915_gpu_error.c 					  struct intel_engine_cs *engine,
engine           1066 drivers/gpu/drm/i915/i915_gpu_error.c 	struct drm_i915_private *dev_priv = engine->i915;
engine           1069 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
engine           1076 drivers/gpu/drm/i915/i915_gpu_error.c 			ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
engine           1080 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
engine           1081 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
engine           1082 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
engine           1083 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->instps = ENGINE_READ(engine, RING_INSTPS);
engine           1084 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
engine           1086 drivers/gpu/drm/i915/i915_gpu_error.c 			ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
engine           1087 drivers/gpu/drm/i915/i915_gpu_error.c 			ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
engine           1089 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
engine           1091 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
engine           1092 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->ipeir = ENGINE_READ(engine, IPEIR);
engine           1093 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->ipehr = ENGINE_READ(engine, IPEHR);
engine           1096 drivers/gpu/drm/i915/i915_gpu_error.c 	intel_engine_get_instdone(engine, &ee->instdone);
engine           1098 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->instpm = ENGINE_READ(engine, RING_INSTPM);
engine           1099 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->acthd = intel_engine_get_active_head(engine);
engine           1100 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->start = ENGINE_READ(engine, RING_START);
engine           1101 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->head = ENGINE_READ(engine, RING_HEAD);
engine           1102 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->tail = ENGINE_READ(engine, RING_TAIL);
engine           1103 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->ctl = ENGINE_READ(engine, RING_CTL);
engine           1105 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->mode = ENGINE_READ(engine, RING_MI_MODE);
engine           1111 drivers/gpu/drm/i915/i915_gpu_error.c 			switch (engine->id) {
engine           1113 drivers/gpu/drm/i915/i915_gpu_error.c 				MISSING_CASE(engine->id);
engine           1128 drivers/gpu/drm/i915/i915_gpu_error.c 		} else if (IS_GEN(engine->i915, 6)) {
engine           1129 drivers/gpu/drm/i915/i915_gpu_error.c 			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
engine           1132 drivers/gpu/drm/i915/i915_gpu_error.c 			mmio = RING_HWS_PGA(engine->mmio_base);
engine           1138 drivers/gpu/drm/i915/i915_gpu_error.c 	ee->idle = intel_engine_is_idle(engine);
engine           1140 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
engine           1142 drivers/gpu/drm/i915/i915_gpu_error.c 						  engine);
engine           1147 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
engine           1151 drivers/gpu/drm/i915/i915_gpu_error.c 				ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
engine           1154 drivers/gpu/drm/i915/i915_gpu_error.c 				ENGINE_READ(engine, RING_PP_DIR_BASE);
engine           1156 drivers/gpu/drm/i915/i915_gpu_error.c 			u32 base = engine->mmio_base;
engine           1188 drivers/gpu/drm/i915/i915_gpu_error.c static void engine_record_requests(struct intel_engine_cs *engine,
engine           1197 drivers/gpu/drm/i915/i915_gpu_error.c 	list_for_each_entry_from(request, &engine->active.requests, sched.link)
engine           1211 drivers/gpu/drm/i915/i915_gpu_error.c 				 &engine->active.requests, sched.link) {
engine           1236 drivers/gpu/drm/i915/i915_gpu_error.c static void error_record_engine_execlists(const struct intel_engine_cs *engine,
engine           1239 drivers/gpu/drm/i915/i915_gpu_error.c 	const struct intel_engine_execlists * const execlists = &engine->execlists;
engine           1366 drivers/gpu/drm/i915/i915_gpu_error.c 	struct intel_engine_cs *engine;
engine           1373 drivers/gpu/drm/i915/i915_gpu_error.c 	for_each_uabi_engine(engine, i915) {
engine           1381 drivers/gpu/drm/i915/i915_gpu_error.c 		spin_lock_irqsave(&engine->active.lock, flags);
engine           1382 drivers/gpu/drm/i915/i915_gpu_error.c 		request = intel_engine_find_active_request(engine);
engine           1384 drivers/gpu/drm/i915/i915_gpu_error.c 			spin_unlock_irqrestore(&engine->active.lock, flags);
engine           1401 drivers/gpu/drm/i915/i915_gpu_error.c 					      engine->gt->scratch,
engine           1421 drivers/gpu/drm/i915/i915_gpu_error.c 		engine_record_requests(engine, request, ee);
engine           1422 drivers/gpu/drm/i915/i915_gpu_error.c 		spin_unlock_irqrestore(&engine->active.lock, flags);
engine           1424 drivers/gpu/drm/i915/i915_gpu_error.c 		error_record_engine_registers(error, engine, ee);
engine           1425 drivers/gpu/drm/i915/i915_gpu_error.c 		error_record_engine_execlists(engine, ee);
engine           1443 drivers/gpu/drm/i915/i915_gpu_error.c 						 engine->status_page.vma,
engine           1448 drivers/gpu/drm/i915/i915_gpu_error.c 						 engine->wa_ctx.vma,
engine           1452 drivers/gpu/drm/i915/i915_gpu_error.c 			capture_object(i915, engine->default_state, compress);
engine           1454 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->engine = engine;
engine           1456 drivers/gpu/drm/i915/i915_gpu_error.c 		ee->next = error->engine;
engine           1457 drivers/gpu/drm/i915/i915_gpu_error.c 		error->engine = ee;
engine           1605 drivers/gpu/drm/i915/i915_gpu_error.c 	if (error->engine) {
engine           1610 drivers/gpu/drm/i915/i915_gpu_error.c 				 error->engine->context.comm,
engine           1611 drivers/gpu/drm/i915/i915_gpu_error.c 				 error->engine->context.pid);
engine           1655 drivers/gpu/drm/i915/i915_gpu_error.c 	for (ee = error->engine; ee; ee = ee->next) {
engine             84 drivers/gpu/drm/i915/i915_gpu_error.h 		const struct intel_engine_cs *engine;
engine            164 drivers/gpu/drm/i915/i915_gpu_error.h 	} *engine;
engine           1697 drivers/gpu/drm/i915/i915_irq.c 		intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]);
engine           4044 drivers/gpu/drm/i915/i915_irq.c 			intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
engine           4149 drivers/gpu/drm/i915/i915_irq.c 			intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
engine           4291 drivers/gpu/drm/i915/i915_irq.c 			intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
engine           4294 drivers/gpu/drm/i915/i915_irq.c 			intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
engine           1217 drivers/gpu/drm/i915/i915_perf.c 		if (ce->engine->class != RENDER_CLASS)
engine           1680 drivers/gpu/drm/i915/i915_perf.c 	struct drm_i915_private *i915 = ce->engine->i915;
engine           1774 drivers/gpu/drm/i915/i915_perf.c 	rq = i915_request_create(ce->engine->kernel_context);
engine           1811 drivers/gpu/drm/i915/i915_perf.c 		GEM_BUG_ON(ce == ce->engine->kernel_context);
engine           1813 drivers/gpu/drm/i915/i915_perf.c 		if (ce->engine->class != RENDER_CLASS)
engine           1887 drivers/gpu/drm/i915/i915_perf.c 	struct intel_engine_cs *engine;
engine           1928 drivers/gpu/drm/i915/i915_perf.c 	for_each_uabi_engine(engine, i915) {
engine           1929 drivers/gpu/drm/i915/i915_perf.c 		struct intel_context *ce = engine->kernel_context;
engine           1932 drivers/gpu/drm/i915/i915_perf.c 		if (engine->class != RENDER_CLASS)
engine           2301 drivers/gpu/drm/i915/i915_perf.c void i915_oa_init_reg_state(struct intel_engine_cs *engine,
engine           2307 drivers/gpu/drm/i915/i915_perf.c 	if (engine->class != RENDER_CLASS)
engine           2310 drivers/gpu/drm/i915/i915_perf.c 	stream = engine->i915->perf.exclusive_stream;
engine             28 drivers/gpu/drm/i915/i915_perf.h void i915_oa_init_reg_state(struct intel_engine_cs *engine,
engine            171 drivers/gpu/drm/i915/i915_pmu.c 	struct intel_engine_cs *engine;
engine            177 drivers/gpu/drm/i915/i915_pmu.c 	for_each_engine(engine, i915, id) {
engine            178 drivers/gpu/drm/i915/i915_pmu.c 		struct intel_engine_pmu *pmu = &engine->pmu;
engine            183 drivers/gpu/drm/i915/i915_pmu.c 		if (!intel_engine_pm_get_if_awake(engine))
engine            186 drivers/gpu/drm/i915/i915_pmu.c 		spin_lock_irqsave(&engine->uncore->lock, flags);
engine            188 drivers/gpu/drm/i915/i915_pmu.c 		val = ENGINE_READ_FW(engine, RING_CTL);
engine            206 drivers/gpu/drm/i915/i915_pmu.c 			val = ENGINE_READ_FW(engine, RING_MI_MODE);
engine            213 drivers/gpu/drm/i915/i915_pmu.c 		spin_unlock_irqrestore(&engine->uncore->lock, flags);
engine            214 drivers/gpu/drm/i915/i915_pmu.c 		intel_engine_pm_put(engine);
engine            303 drivers/gpu/drm/i915/i915_pmu.c 	struct intel_engine_cs *engine;
engine            305 drivers/gpu/drm/i915/i915_pmu.c 	engine = intel_engine_lookup_user(i915,
engine            308 drivers/gpu/drm/i915/i915_pmu.c 	if (WARN_ON_ONCE(!engine))
engine            312 drivers/gpu/drm/i915/i915_pmu.c 	    intel_engine_supports_stats(engine))
engine            313 drivers/gpu/drm/i915/i915_pmu.c 		intel_disable_engine_stats(engine);
engine            325 drivers/gpu/drm/i915/i915_pmu.c engine_event_status(struct intel_engine_cs *engine,
engine            333 drivers/gpu/drm/i915/i915_pmu.c 		if (INTEL_GEN(engine->i915) < 6)
engine            373 drivers/gpu/drm/i915/i915_pmu.c 	struct intel_engine_cs *engine;
engine            377 drivers/gpu/drm/i915/i915_pmu.c 	engine = intel_engine_lookup_user(i915, engine_event_class(event),
engine            379 drivers/gpu/drm/i915/i915_pmu.c 	if (!engine)
engine            383 drivers/gpu/drm/i915/i915_pmu.c 	ret = engine_event_status(engine, sample);
engine            387 drivers/gpu/drm/i915/i915_pmu.c 	if (sample == I915_SAMPLE_BUSY && intel_engine_supports_stats(engine))
engine            388 drivers/gpu/drm/i915/i915_pmu.c 		ret = intel_enable_engine_stats(engine);
engine            536 drivers/gpu/drm/i915/i915_pmu.c 		struct intel_engine_cs *engine;
engine            538 drivers/gpu/drm/i915/i915_pmu.c 		engine = intel_engine_lookup_user(i915,
engine            542 drivers/gpu/drm/i915/i915_pmu.c 		if (WARN_ON_ONCE(!engine)) {
engine            545 drivers/gpu/drm/i915/i915_pmu.c 			   intel_engine_supports_stats(engine)) {
engine            546 drivers/gpu/drm/i915/i915_pmu.c 			val = ktime_to_ns(intel_engine_get_busy_time(engine));
engine            548 drivers/gpu/drm/i915/i915_pmu.c 			val = engine->pmu.sample[sample].cur;
engine            620 drivers/gpu/drm/i915/i915_pmu.c 		struct intel_engine_cs *engine;
engine            622 drivers/gpu/drm/i915/i915_pmu.c 		engine = intel_engine_lookup_user(i915,
engine            626 drivers/gpu/drm/i915/i915_pmu.c 		BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
engine            628 drivers/gpu/drm/i915/i915_pmu.c 		BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
engine            630 drivers/gpu/drm/i915/i915_pmu.c 		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
engine            631 drivers/gpu/drm/i915/i915_pmu.c 		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
engine            632 drivers/gpu/drm/i915/i915_pmu.c 		GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
engine            634 drivers/gpu/drm/i915/i915_pmu.c 		engine->pmu.enable |= BIT(sample);
engine            635 drivers/gpu/drm/i915/i915_pmu.c 		engine->pmu.enable_count[sample]++;
engine            660 drivers/gpu/drm/i915/i915_pmu.c 		struct intel_engine_cs *engine;
engine            662 drivers/gpu/drm/i915/i915_pmu.c 		engine = intel_engine_lookup_user(i915,
engine            666 drivers/gpu/drm/i915/i915_pmu.c 		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
engine            667 drivers/gpu/drm/i915/i915_pmu.c 		GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
engine            668 drivers/gpu/drm/i915/i915_pmu.c 		GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
engine            674 drivers/gpu/drm/i915/i915_pmu.c 		if (--engine->pmu.enable_count[sample] == 0)
engine            675 drivers/gpu/drm/i915/i915_pmu.c 			engine->pmu.enable &= ~BIT(sample);
engine            863 drivers/gpu/drm/i915/i915_pmu.c 	struct intel_engine_cs *engine;
engine            872 drivers/gpu/drm/i915/i915_pmu.c 	for_each_uabi_engine(engine, i915) {
engine            874 drivers/gpu/drm/i915/i915_pmu.c 			if (!engine_event_status(engine,
engine            923 drivers/gpu/drm/i915/i915_pmu.c 	for_each_uabi_engine(engine, i915) {
engine            927 drivers/gpu/drm/i915/i915_pmu.c 			if (engine_event_status(engine,
engine            932 drivers/gpu/drm/i915/i915_pmu.c 					engine->name, engine_events[i].name);
engine            939 drivers/gpu/drm/i915/i915_pmu.c 					      __I915_PMU_ENGINE(engine->uabi_class,
engine            940 drivers/gpu/drm/i915/i915_pmu.c 								engine->uabi_instance,
engine            944 drivers/gpu/drm/i915/i915_pmu.c 					engine->name, engine_events[i].name);
engine            107 drivers/gpu/drm/i915/i915_query.c 	struct intel_engine_cs *engine;
engine            127 drivers/gpu/drm/i915/i915_query.c 	for_each_uabi_engine(engine, i915) {
engine            128 drivers/gpu/drm/i915/i915_query.c 		info.engine.engine_class = engine->uabi_class;
engine            129 drivers/gpu/drm/i915/i915_query.c 		info.engine.engine_instance = engine->uabi_instance;
engine            130 drivers/gpu/drm/i915/i915_query.c 		info.capabilities = engine->uabi_capabilities;
engine            403 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
engine            405 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
engine            409 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
engine            411 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
engine            413 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
engine           2453 drivers/gpu/drm/i915/i915_reg.h #define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100 * (engine)->hw_id)
engine            199 drivers/gpu/drm/i915/i915_request.c 	struct intel_engine_cs *engine, *locked;
engine            207 drivers/gpu/drm/i915/i915_request.c 	locked = READ_ONCE(rq->engine);
engine            209 drivers/gpu/drm/i915/i915_request.c 	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
engine            211 drivers/gpu/drm/i915/i915_request.c 		spin_lock(&engine->active.lock);
engine            212 drivers/gpu/drm/i915/i915_request.c 		locked = engine;
engine            227 drivers/gpu/drm/i915/i915_request.c 		  rq->engine->name,
engine            323 drivers/gpu/drm/i915/i915_request.c 		  rq->engine->name,
engine            382 drivers/gpu/drm/i915/i915_request.c 	struct intel_engine_cs *engine = request->engine;
engine            386 drivers/gpu/drm/i915/i915_request.c 		  engine->name,
engine            391 drivers/gpu/drm/i915/i915_request.c 	lockdep_assert_held(&engine->active.lock);
engine            433 drivers/gpu/drm/i915/i915_request.c 		engine->saturated |= request->sched.semaphores;
engine            435 drivers/gpu/drm/i915/i915_request.c 	engine->emit_fini_breadcrumb(request,
engine            439 drivers/gpu/drm/i915/i915_request.c 	engine->serial++;
engine            446 drivers/gpu/drm/i915/i915_request.c 		list_move_tail(&request->sched.link, &engine->active.requests);
engine            451 drivers/gpu/drm/i915/i915_request.c 		intel_engine_queue_breadcrumbs(engine);
engine            462 drivers/gpu/drm/i915/i915_request.c 	struct intel_engine_cs *engine = request->engine;
engine            466 drivers/gpu/drm/i915/i915_request.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            470 drivers/gpu/drm/i915/i915_request.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            475 drivers/gpu/drm/i915/i915_request.c 	struct intel_engine_cs *engine = request->engine;
engine            478 drivers/gpu/drm/i915/i915_request.c 		  engine->name,
engine            483 drivers/gpu/drm/i915/i915_request.c 	lockdep_assert_held(&engine->active.lock);
engine            518 drivers/gpu/drm/i915/i915_request.c 	struct intel_engine_cs *engine = request->engine;
engine            522 drivers/gpu/drm/i915/i915_request.c 	spin_lock_irqsave(&engine->active.lock, flags);
engine            526 drivers/gpu/drm/i915/i915_request.c 	spin_unlock_irqrestore(&engine->active.lock, flags);
engine            551 drivers/gpu/drm/i915/i915_request.c 		request->engine->submit_request(request);
engine            690 drivers/gpu/drm/i915/i915_request.c 	rq->i915 = ce->engine->i915;
engine            693 drivers/gpu/drm/i915/i915_request.c 	rq->engine = ce->engine;
engine            733 drivers/gpu/drm/i915/i915_request.c 		2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
engine            743 drivers/gpu/drm/i915/i915_request.c 	ret = rq->engine->request_alloc(rq);
engine            828 drivers/gpu/drm/i915/i915_request.c 	return rq->sched.semaphores | rq->engine->saturated;
engine            844 drivers/gpu/drm/i915/i915_request.c 	if (already_busywaiting(to) & from->engine->mask)
engine            884 drivers/gpu/drm/i915/i915_request.c 	to->sched.semaphores |= from->engine->mask;
engine            902 drivers/gpu/drm/i915/i915_request.c 	if (to->engine->schedule) {
engine            908 drivers/gpu/drm/i915/i915_request.c 	if (to->engine == from->engine) {
engine            912 drivers/gpu/drm/i915/i915_request.c 	} else if (intel_engine_has_semaphores(to->engine) &&
engine           1154 drivers/gpu/drm/i915/i915_request.c 		if (is_power_of_2(prev->engine->mask | rq->engine->mask))
engine           1162 drivers/gpu/drm/i915/i915_request.c 		if (rq->engine->schedule)
engine           1189 drivers/gpu/drm/i915/i915_request.c 	struct intel_engine_cs *engine = rq->engine;
engine           1194 drivers/gpu/drm/i915/i915_request.c 		  engine->name, rq->fence.context, rq->fence.seqno);
engine           1211 drivers/gpu/drm/i915/i915_request.c 	cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
engine           1232 drivers/gpu/drm/i915/i915_request.c 	if (attr && rq->engine->schedule)
engine           1233 drivers/gpu/drm/i915/i915_request.c 		rq->engine->schedule(rq, attr);
engine           1434 drivers/gpu/drm/i915/i915_request.c 	mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
engine           1512 drivers/gpu/drm/i915/i915_request.c 	mutex_release(&rq->engine->gt->reset.mutex.dep_map, 0, _THIS_IP_);
engine            114 drivers/gpu/drm/i915/i915_request.h 	struct intel_engine_cs *engine;
engine             72 drivers/gpu/drm/i915/i915_scheduler.c i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
engine             74 drivers/gpu/drm/i915/i915_scheduler.c 	struct intel_engine_execlists * const execlists = &engine->execlists;
engine             80 drivers/gpu/drm/i915/i915_scheduler.c 	lockdep_assert_held(&engine->active.lock);
engine            154 drivers/gpu/drm/i915/i915_scheduler.c 	struct intel_engine_cs *engine;
engine            164 drivers/gpu/drm/i915/i915_scheduler.c 	while (locked != (engine = READ_ONCE(rq->engine))) {
engine            167 drivers/gpu/drm/i915/i915_scheduler.c 		spin_lock(&engine->active.lock);
engine            168 drivers/gpu/drm/i915/i915_scheduler.c 		locked = engine;
engine            171 drivers/gpu/drm/i915/i915_scheduler.c 	GEM_BUG_ON(locked != engine);
engine            192 drivers/gpu/drm/i915/i915_scheduler.c static void kick_submission(struct intel_engine_cs *engine,
engine            202 drivers/gpu/drm/i915/i915_scheduler.c 	if (prio <= engine->execlists.queue_priority_hint)
engine            208 drivers/gpu/drm/i915/i915_scheduler.c 	inflight = execlists_active(&engine->execlists);
engine            222 drivers/gpu/drm/i915/i915_scheduler.c 	engine->execlists.queue_priority_hint = prio;
engine            224 drivers/gpu/drm/i915/i915_scheduler.c 		tasklet_hi_schedule(&engine->execlists.tasklet);
engine            233 drivers/gpu/drm/i915/i915_scheduler.c 	struct intel_engine_cs *engine;
engine            312 drivers/gpu/drm/i915/i915_scheduler.c 	engine = node_to_request(node)->engine;
engine            313 drivers/gpu/drm/i915/i915_scheduler.c 	spin_lock(&engine->active.lock);
engine            316 drivers/gpu/drm/i915/i915_scheduler.c 	engine = sched_lock_engine(node, engine, &cache);
engine            321 drivers/gpu/drm/i915/i915_scheduler.c 		engine = sched_lock_engine(node, engine, &cache);
engine            322 drivers/gpu/drm/i915/i915_scheduler.c 		lockdep_assert_held(&engine->active.lock);
engine            328 drivers/gpu/drm/i915/i915_scheduler.c 		GEM_BUG_ON(node_to_request(node)->engine != engine);
engine            344 drivers/gpu/drm/i915/i915_scheduler.c 		if (!intel_engine_is_virtual(engine) &&
engine            348 drivers/gpu/drm/i915/i915_scheduler.c 					i915_sched_lookup_priolist(engine,
engine            354 drivers/gpu/drm/i915/i915_scheduler.c 		kick_submission(engine, node_to_request(node), prio);
engine            357 drivers/gpu/drm/i915/i915_scheduler.c 	spin_unlock(&engine->active.lock);
engine             46 drivers/gpu/drm/i915/i915_scheduler.h i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio);
engine            679 drivers/gpu/drm/i915/i915_trace.h 			   __entry->class = rq->engine->uabi_class;
engine            680 drivers/gpu/drm/i915/i915_trace.h 			   __entry->instance = rq->engine->uabi_instance;
engine            708 drivers/gpu/drm/i915/i915_trace.h 			   __entry->class = rq->engine->uabi_class;
engine            709 drivers/gpu/drm/i915/i915_trace.h 			   __entry->instance = rq->engine->uabi_instance;
engine            753 drivers/gpu/drm/i915/i915_trace.h 			   __entry->class = rq->engine->uabi_class;
engine            754 drivers/gpu/drm/i915/i915_trace.h 			   __entry->instance = rq->engine->uabi_instance;
engine            784 drivers/gpu/drm/i915/i915_trace.h 			   __entry->class = rq->engine->uabi_class;
engine            785 drivers/gpu/drm/i915/i915_trace.h 			   __entry->instance = rq->engine->uabi_instance;
engine            849 drivers/gpu/drm/i915/i915_trace.h 			   __entry->class = rq->engine->uabi_class;
engine            850 drivers/gpu/drm/i915/i915_trace.h 			   __entry->instance = rq->engine->uabi_instance;
engine           7150 drivers/gpu/drm/i915/intel_pm.c 	struct intel_engine_cs *engine;
engine           7171 drivers/gpu/drm/i915/intel_pm.c 	for_each_engine(engine, dev_priv, id)
engine           7172 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
engine           7222 drivers/gpu/drm/i915/intel_pm.c 	struct intel_engine_cs *engine;
engine           7252 drivers/gpu/drm/i915/intel_pm.c 	for_each_engine(engine, dev_priv, id)
engine           7253 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
engine           7313 drivers/gpu/drm/i915/intel_pm.c 	struct intel_engine_cs *engine;
engine           7330 drivers/gpu/drm/i915/intel_pm.c 	for_each_engine(engine, dev_priv, id)
engine           7331 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
engine           7387 drivers/gpu/drm/i915/intel_pm.c 	struct intel_engine_cs *engine;
engine           7413 drivers/gpu/drm/i915/intel_pm.c 	for_each_engine(engine, dev_priv, id)
engine           7414 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
engine           7895 drivers/gpu/drm/i915/intel_pm.c 	struct intel_engine_cs *engine;
engine           7921 drivers/gpu/drm/i915/intel_pm.c 	for_each_engine(engine, dev_priv, id)
engine           7922 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
engine           7992 drivers/gpu/drm/i915/intel_pm.c 	struct intel_engine_cs *engine;
engine           8014 drivers/gpu/drm/i915/intel_pm.c 	for_each_engine(engine, dev_priv, id)
engine           8015 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
engine             79 drivers/gpu/drm/i915/selftests/i915_active.c 	struct intel_engine_cs *engine;
engine            100 drivers/gpu/drm/i915/selftests/i915_active.c 	for_each_engine(engine, i915, id) {
engine            103 drivers/gpu/drm/i915/selftests/i915_active.c 		rq = i915_request_create(engine->kernel_context);
engine             21 drivers/gpu/drm/i915/selftests/i915_gem.c 	struct intel_engine_cs *engine;
engine             24 drivers/gpu/drm/i915/selftests/i915_gem.c 	for_each_engine(engine, i915, id) {
engine             27 drivers/gpu/drm/i915/selftests/i915_gem.c 		rq = igt_request_alloc(ctx, engine);
engine            386 drivers/gpu/drm/i915/selftests/i915_gem_evict.c 	struct intel_engine_cs *engine;
engine            452 drivers/gpu/drm/i915/selftests/i915_gem_evict.c 	for_each_engine(engine, i915, id) {
engine            475 drivers/gpu/drm/i915/selftests/i915_gem_evict.c 			rq = igt_request_alloc(ctx, engine);
engine            482 drivers/gpu/drm/i915/selftests/i915_gem_evict.c 					       ctx->hw_id, engine->name,
engine            504 drivers/gpu/drm/i915/selftests/i915_gem_evict.c 			count, engine->name);
engine             17 drivers/gpu/drm/i915/selftests/i915_mock_selftests.h selftest(engine, intel_engine_cs_mock_selftests)
engine             49 drivers/gpu/drm/i915/selftests/i915_request.c 	request = mock_request(i915->engine[RCS0]->kernel_context, HZ / 10);
engine             71 drivers/gpu/drm/i915/selftests/i915_request.c 	request = mock_request(i915->engine[RCS0]->kernel_context, T);
engine            144 drivers/gpu/drm/i915/selftests/i915_request.c 	request = mock_request(i915->engine[RCS0]->kernel_context, T);
engine            233 drivers/gpu/drm/i915/selftests/i915_request.c 	request->engine->submit_request(request);
engine            263 drivers/gpu/drm/i915/selftests/i915_request.c 	struct intel_engine_cs *engine;
engine            285 drivers/gpu/drm/i915/selftests/i915_request.c 	struct mutex * const BKL = &t->engine->i915->drm.struct_mutex;
engine            342 drivers/gpu/drm/i915/selftests/i915_request.c 			ce = i915_gem_context_get_engine(ctx, t->engine->legacy_idx);
engine            386 drivers/gpu/drm/i915/selftests/i915_request.c 			       t->engine->name);
engine            389 drivers/gpu/drm/i915/selftests/i915_request.c 			intel_gt_set_wedged(t->engine->gt);
engine            433 drivers/gpu/drm/i915/selftests/i915_request.c 		.engine = i915->engine[RCS0],
engine            460 drivers/gpu/drm/i915/selftests/i915_request.c 	mutex_lock(&t.engine->i915->drm.struct_mutex);
engine            462 drivers/gpu/drm/i915/selftests/i915_request.c 		t.contexts[n] = mock_context(t.engine->i915, "mock");
engine            468 drivers/gpu/drm/i915/selftests/i915_request.c 	mutex_unlock(&t.engine->i915->drm.struct_mutex);
engine            498 drivers/gpu/drm/i915/selftests/i915_request.c 	mutex_lock(&t.engine->i915->drm.struct_mutex);
engine            505 drivers/gpu/drm/i915/selftests/i915_request.c 	mutex_unlock(&t.engine->i915->drm.struct_mutex);
engine            541 drivers/gpu/drm/i915/selftests/i915_request.c 	struct intel_engine_cs *engine;
engine            555 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine            561 drivers/gpu/drm/i915/selftests/i915_request.c 		err = igt_live_test_begin(&t, i915, __func__, engine->name);
engine            569 drivers/gpu/drm/i915/selftests/i915_request.c 				request = i915_request_create(engine->kernel_context);
engine            605 drivers/gpu/drm/i915/selftests/i915_request.c 			engine->name,
engine            658 drivers/gpu/drm/i915/selftests/i915_request.c empty_request(struct intel_engine_cs *engine,
engine            664 drivers/gpu/drm/i915/selftests/i915_request.c 	request = i915_request_create(engine->kernel_context);
engine            668 drivers/gpu/drm/i915/selftests/i915_request.c 	err = engine->emit_bb_start(request,
engine            683 drivers/gpu/drm/i915/selftests/i915_request.c 	struct intel_engine_cs *engine;
engine            704 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine            710 drivers/gpu/drm/i915/selftests/i915_request.c 		err = igt_live_test_begin(&t, i915, __func__, engine->name);
engine            715 drivers/gpu/drm/i915/selftests/i915_request.c 		request = empty_request(engine, batch);
engine            726 drivers/gpu/drm/i915/selftests/i915_request.c 				request = empty_request(engine, batch);
engine            747 drivers/gpu/drm/i915/selftests/i915_request.c 			engine->name,
engine            835 drivers/gpu/drm/i915/selftests/i915_request.c 	struct intel_engine_cs *engine;
engine            862 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine            863 drivers/gpu/drm/i915/selftests/i915_request.c 		request[id] = i915_request_create(engine->kernel_context);
engine            871 drivers/gpu/drm/i915/selftests/i915_request.c 		err = engine->emit_bb_start(request[id],
engine            889 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine            892 drivers/gpu/drm/i915/selftests/i915_request.c 			       __func__, engine->name);
engine            904 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine            912 drivers/gpu/drm/i915/selftests/i915_request.c 			       __func__, engine->name, err);
engine            924 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id)
engine            940 drivers/gpu/drm/i915/selftests/i915_request.c 	struct intel_engine_cs *engine;
engine            959 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine            966 drivers/gpu/drm/i915/selftests/i915_request.c 			       __func__, engine->name, err);
engine            970 drivers/gpu/drm/i915/selftests/i915_request.c 		request[id] = i915_request_create(engine->kernel_context);
engine            974 drivers/gpu/drm/i915/selftests/i915_request.c 			       __func__, engine->name, err);
engine            984 drivers/gpu/drm/i915/selftests/i915_request.c 				       __func__, engine->name, err);
engine            989 drivers/gpu/drm/i915/selftests/i915_request.c 		err = engine->emit_bb_start(request[id],
engine           1009 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine           1014 drivers/gpu/drm/i915/selftests/i915_request.c 			       __func__, engine->name);
engine           1031 drivers/gpu/drm/i915/selftests/i915_request.c 			       __func__, engine->name, err);
engine           1041 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine           1051 drivers/gpu/drm/i915/selftests/i915_request.c 			intel_gt_chipset_flush(engine->gt);
engine           1066 drivers/gpu/drm/i915/selftests/i915_request.c max_batches(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
engine           1083 drivers/gpu/drm/i915/selftests/i915_request.c 	rq = igt_request_alloc(ctx, engine);
engine           1108 drivers/gpu/drm/i915/selftests/i915_request.c 	struct intel_engine_cs *engine;
engine           1165 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine           1167 drivers/gpu/drm/i915/selftests/i915_request.c 		t[id].engine = engine;
engine           1168 drivers/gpu/drm/i915/selftests/i915_request.c 		t[id].max_batch = max_batches(t[0].contexts[0], engine);
engine           1177 drivers/gpu/drm/i915/selftests/i915_request.c 			 t[id].max_batch, engine->name);
engine           1201 drivers/gpu/drm/i915/selftests/i915_request.c 	for_each_engine(engine, i915, id) {
engine             18 drivers/gpu/drm/i915/selftests/igt_live_test.c 	struct intel_engine_cs *engine;
engine             40 drivers/gpu/drm/i915/selftests/igt_live_test.c 	for_each_engine(engine, i915, id)
engine             42 drivers/gpu/drm/i915/selftests/igt_live_test.c 			i915_reset_engine_count(&i915->gpu_error, engine);
engine             50 drivers/gpu/drm/i915/selftests/igt_live_test.c 	struct intel_engine_cs *engine;
engine             65 drivers/gpu/drm/i915/selftests/igt_live_test.c 	for_each_engine(engine, i915, id) {
engine             67 drivers/gpu/drm/i915/selftests/igt_live_test.c 		    i915_reset_engine_count(&i915->gpu_error, engine))
engine             71 drivers/gpu/drm/i915/selftests/igt_live_test.c 		       t->func, t->name, engine->name,
engine             72 drivers/gpu/drm/i915/selftests/igt_live_test.c 		       i915_reset_engine_count(&i915->gpu_error, engine) -
engine             16 drivers/gpu/drm/i915/selftests/igt_reset.c 	struct intel_engine_cs *engine;
engine             25 drivers/gpu/drm/i915/selftests/igt_reset.c 	for_each_engine(engine, gt->i915, id) {
engine             35 drivers/gpu/drm/i915/selftests/igt_reset.c 	struct intel_engine_cs *engine;
engine             38 drivers/gpu/drm/i915/selftests/igt_reset.c 	for_each_engine(engine, gt->i915, id)
engine             95 drivers/gpu/drm/i915/selftests/igt_spinner.c 	struct intel_engine_cs *engine = ce->engine;
engine            147 drivers/gpu/drm/i915/selftests/igt_spinner.c 	intel_gt_chipset_flush(engine->gt);
engine            149 drivers/gpu/drm/i915/selftests/igt_spinner.c 	if (engine->emit_init_breadcrumb &&
engine            151 drivers/gpu/drm/i915/selftests/igt_spinner.c 		err = engine->emit_init_breadcrumb(rq);
engine            156 drivers/gpu/drm/i915/selftests/igt_spinner.c 	err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0);
engine            144 drivers/gpu/drm/i915/selftests/intel_uncore.c 	struct intel_engine_cs *engine;
engine            189 drivers/gpu/drm/i915/selftests/intel_uncore.c 	for_each_engine(engine, i915, id) {
engine            190 drivers/gpu/drm/i915/selftests/intel_uncore.c 		i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
engine            191 drivers/gpu/drm/i915/selftests/intel_uncore.c 		u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
engine            195 drivers/gpu/drm/i915/selftests/intel_uncore.c 		if (!engine->default_state)
engine            235 drivers/gpu/drm/i915/selftests/intel_uncore.c 			       engine->name, r->name);
engine            243 drivers/gpu/drm/i915/selftests/intel_uncore.c 			       engine->name, r->name, readl(reg), fw_domains);
engine             41 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	struct intel_engine_cs *engine;
engine             47 drivers/gpu/drm/i915/selftests/mock_gem_device.c 		for_each_engine(engine, i915, id)
engine             48 drivers/gpu/drm/i915/selftests/mock_gem_device.c 			mock_engine_flush(engine);
engine             55 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	struct intel_engine_cs *engine;
engine             66 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	for_each_engine(engine, i915, id)
engine             67 drivers/gpu/drm/i915/selftests/mock_gem_device.c 		mock_engine_free(engine);
engine            205 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	i915->engine[RCS0] = mock_engine(i915, "mock", RCS0);
engine            206 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	if (!i915->engine[RCS0])
engine            213 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	if (mock_engine_init(i915->engine[RCS0]))
engine            226 drivers/gpu/drm/i915/selftests/mock_gem_device.c 	mock_engine_free(i915->engine[RCS0]);
engine             46 drivers/gpu/drm/i915/selftests/mock_request.c 	struct mock_engine *engine =
engine             47 drivers/gpu/drm/i915/selftests/mock_request.c 		container_of(request->engine, typeof(*engine), base);
engine             50 drivers/gpu/drm/i915/selftests/mock_request.c 	spin_lock_irq(&engine->hw_lock);
engine             53 drivers/gpu/drm/i915/selftests/mock_request.c 	spin_unlock_irq(&engine->hw_lock);
engine              6 drivers/gpu/drm/nouveau/include/nvif/fifo.h u64 nvif_fifo_runlist(struct nvif_device *, u64 engine);
engine             11 drivers/gpu/drm/nouveau/include/nvkm/core/object.h 	struct nvkm_engine *engine;
engine             29 drivers/gpu/drm/nouveau/include/nvkm/core/oclass.h 	struct nvkm_engine *engine;
engine              4 drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h #define nvkm_disp(p) container_of((p), struct nvkm_disp, engine)
engine             10 drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h 	struct nvkm_engine engine;
engine             21 drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h 	struct nvkm_engine engine;
engine              4 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h #define nvkm_falcon(p) container_of((p), struct nvkm_falcon, engine)
engine             50 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h 	struct nvkm_engine engine;
engine             37 drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h 	struct nvkm_engine engine;
engine              8 drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h 	struct nvkm_engine engine;
engine              4 drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h #define nvkm_nvdec(p) container_of((p), struct nvkm_nvdec, engine)
engine              8 drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h 	struct nvkm_engine engine;
engine              8 drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h 	struct nvkm_engine engine;
engine              7 drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h 	struct nvkm_engine engine;
engine              8 drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h 	struct nvkm_engine engine;
engine              4 drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h #define nvkm_xtensa(p) container_of((p), struct nvkm_xtensa, engine)
engine             10 drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h 	struct nvkm_engine engine;
engine             24 drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h 	u8 engine;
engine            256 drivers/gpu/drm/nouveau/nouveau_abi16.c 	u64 engine;
engine            271 drivers/gpu/drm/nouveau/nouveau_abi16.c 			case 0x01: engine = NV_DEVICE_INFO_ENGINE_GR    ; break;
engine            272 drivers/gpu/drm/nouveau/nouveau_abi16.c 			case 0x02: engine = NV_DEVICE_INFO_ENGINE_MSPDEC; break;
engine            273 drivers/gpu/drm/nouveau/nouveau_abi16.c 			case 0x04: engine = NV_DEVICE_INFO_ENGINE_MSPPP ; break;
engine            274 drivers/gpu/drm/nouveau/nouveau_abi16.c 			case 0x08: engine = NV_DEVICE_INFO_ENGINE_MSVLD ; break;
engine            275 drivers/gpu/drm/nouveau/nouveau_abi16.c 			case 0x30: engine = NV_DEVICE_INFO_ENGINE_CE    ; break;
engine            280 drivers/gpu/drm/nouveau/nouveau_abi16.c 			engine = NV_DEVICE_INFO_ENGINE_GR;
engine            283 drivers/gpu/drm/nouveau/nouveau_abi16.c 		if (engine != NV_DEVICE_INFO_ENGINE_CE)
engine            284 drivers/gpu/drm/nouveau/nouveau_abi16.c 			engine = nvif_fifo_runlist(device, engine);
engine            286 drivers/gpu/drm/nouveau/nouveau_abi16.c 			engine = nvif_fifo_runlist_ce(device);
engine            287 drivers/gpu/drm/nouveau/nouveau_abi16.c 		init->fb_ctxdma_handle = engine;
engine           1167 drivers/gpu/drm/nouveau/nouveau_bo.c 		int engine;
engine           1202 drivers/gpu/drm/nouveau/nouveau_bo.c 		if (mthd->engine)
engine           1210 drivers/gpu/drm/nouveau/nouveau_bo.c 				       mthd->oclass | (mthd->engine << 16),
engine             58 drivers/gpu/drm/nouveau/nouveau_svm.c 			u32 engine;
engine            446 drivers/gpu/drm/nouveau/nouveau_svm.c 	const u32 engine = nvif_rd32(memory, offset + 0x18);
engine            473 drivers/gpu/drm/nouveau/nouveau_svm.c 	fault->engine = engine;
engine             71 drivers/gpu/drm/nouveau/nvif/fifo.c nvif_fifo_runlist(struct nvif_device *device, u64 engine)
engine             77 drivers/gpu/drm/nouveau/nvif/fifo.c 			struct nv_device_info_v1_data engine;
engine             81 drivers/gpu/drm/nouveau/nvif/fifo.c 		.m.count = sizeof(a.v) / sizeof(a.v.engine),
engine             82 drivers/gpu/drm/nouveau/nvif/fifo.c 		.v.engine.mthd = engine,
engine             93 drivers/gpu/drm/nouveau/nvif/fifo.c 			if (device->runlist[i].engines & a.v.engine.data)
engine             31 drivers/gpu/drm/nouveau/nvkm/core/engine.c nvkm_engine_chsw_load(struct nvkm_engine *engine)
engine             33 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->chsw_load)
engine             34 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		return engine->func->chsw_load(engine);
engine             41 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = *pengine;
engine             42 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine) {
engine             43 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		mutex_lock(&engine->subdev.mutex);
engine             44 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		if (--engine->usecount == 0)
engine             45 drivers/gpu/drm/nouveau/nvkm/core/engine.c 			nvkm_subdev_fini(&engine->subdev, false);
engine             46 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		mutex_unlock(&engine->subdev.mutex);
engine             52 drivers/gpu/drm/nouveau/nvkm/core/engine.c nvkm_engine_ref(struct nvkm_engine *engine)
engine             54 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine) {
engine             55 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		mutex_lock(&engine->subdev.mutex);
engine             56 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		if (++engine->usecount == 1) {
engine             57 drivers/gpu/drm/nouveau/nvkm/core/engine.c 			int ret = nvkm_subdev_init(&engine->subdev);
engine             59 drivers/gpu/drm/nouveau/nvkm/core/engine.c 				engine->usecount--;
engine             60 drivers/gpu/drm/nouveau/nvkm/core/engine.c 				mutex_unlock(&engine->subdev.mutex);
engine             64 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		mutex_unlock(&engine->subdev.mutex);
engine             66 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	return engine;
engine             70 drivers/gpu/drm/nouveau/nvkm/core/engine.c nvkm_engine_tile(struct nvkm_engine *engine, int region)
engine             72 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_fb *fb = engine->subdev.device->fb;
engine             73 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->tile)
engine             74 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		engine->func->tile(engine, region, &fb->tile.region[region]);
engine             80 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = nvkm_engine(subdev);
engine             81 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->intr)
engine             82 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		engine->func->intr(engine);
engine             88 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = nvkm_engine(subdev);
engine             89 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->info) {
engine             90 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		if (!IS_ERR((engine = nvkm_engine_ref(engine)))) {
engine             91 drivers/gpu/drm/nouveau/nvkm/core/engine.c 			int ret = engine->func->info(engine, mthd, data);
engine             92 drivers/gpu/drm/nouveau/nvkm/core/engine.c 			nvkm_engine_unref(&engine);
engine             95 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		return PTR_ERR(engine);
engine            103 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = nvkm_engine(subdev);
engine            104 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->fini)
engine            105 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		return engine->func->fini(engine, suspend);
engine            112 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = nvkm_engine(subdev);
engine            117 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (!engine->usecount) {
engine            122 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->oneinit && !engine->subdev.oneinit) {
engine            125 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		ret = engine->func->oneinit(engine);
engine            131 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		engine->subdev.oneinit = true;
engine            136 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->init)
engine            137 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		ret = engine->func->init(engine);
engine            140 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		nvkm_engine_tile(engine, i);
engine            147 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = nvkm_engine(subdev);
engine            148 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->preinit)
engine            149 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		engine->func->preinit(engine);
engine            156 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	struct nvkm_engine *engine = nvkm_engine(subdev);
engine            157 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	if (engine->func->dtor)
engine            158 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		return engine->func->dtor(engine);
engine            159 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	return engine;
engine            175 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		 struct nvkm_engine *engine)
engine            177 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	nvkm_subdev_ctor(&nvkm_engine_func, device, index, &engine->subdev);
engine            178 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	engine->func = func;
engine            181 drivers/gpu/drm/nouveau/nvkm/core/engine.c 		nvkm_debug(&engine->subdev, "disabled\n");
engine            185 drivers/gpu/drm/nouveau/nvkm/core/engine.c 	spin_lock_init(&engine->lock);
engine            120 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	if (oclass.engine) {
engine            121 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		oclass.engine = nvkm_engine_ref(oclass.engine);
engine            122 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 		if (IS_ERR(oclass.engine))
engine            123 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 			return PTR_ERR(oclass.engine);
engine            127 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 	nvkm_engine_unref(&oclass.engine);
engine            274 drivers/gpu/drm/nouveau/nvkm/core/object.c 	nvkm_engine_unref(&object->engine);
engine            299 drivers/gpu/drm/nouveau/nvkm/core/object.c 	object->engine = nvkm_engine_ref(oclass->engine);
engine            308 drivers/gpu/drm/nouveau/nvkm/core/object.c 	WARN_ON(IS_ERR(object->engine));
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c 	struct nvkm_device *device = ce->engine.subdev.device;
engine             33 drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c 	const int index = ce->engine.subdev.index - NVKM_ENGINE_CE0;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c 	struct nvkm_subdev *subdev = &ce->engine.subdev;
engine             37 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
engine             59 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 	return nvkm_gpuobj_new(object->engine->subdev.device, 256,
engine           2634 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	struct nvkm_engine *engine;
engine           2668 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 		engine = nvkm_device_engine(device, index);
engine           2669 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 		if (engine)
engine           2670 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 			return &engine->subdev;
engine           2695 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(DISP   , device->disp    , &device->disp->engine);
engine           2696 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(DMAOBJ , device->dma     , &device->dma->engine);
engine           2697 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(FIFO   , device->fifo    , &device->fifo->engine);
engine           2698 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(GR     , device->gr      , &device->gr->engine);
engine           2709 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine);
engine           2710 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine);
engine           2711 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine);
engine           2712 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(PM     , device->pm      , &device->pm->engine);
engine           2714 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(SEC2   , device->sec2    , &device->sec2->engine);
engine           2715 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 	_(SW     , device->sw      , &device->sw->engine);
engine            350 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	struct nvkm_engine *engine;
engine            359 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		if (!(engine = nvkm_device_engine(device, i)) ||
engine            360 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		    !(engine->func->base.sclass))
engine            362 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		oclass->engine = engine;
engine            364 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 		index -= engine->func->base.sclass(oclass, index, &sclass);
engine            134 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(object->engine);
engine            151 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(oproxy->base.engine);
engine            152 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	mutex_lock(&disp->engine.subdev.mutex);
engine            155 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	mutex_unlock(&disp->engine.subdev.mutex);
engine            169 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(oclass->engine);
engine            178 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	mutex_lock(&disp->engine.subdev.mutex);
engine            180 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 		mutex_unlock(&disp->engine.subdev.mutex);
engine            184 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	mutex_unlock(&disp->engine.subdev.mutex);
engine            198 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(oclass->engine);
engine            210 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_intr(struct nvkm_engine *engine)
engine            212 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(engine);
engine            217 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_fini(struct nvkm_engine *engine, bool suspend)
engine            219 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(engine);
engine            238 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_init(struct nvkm_engine *engine)
engine            240 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(engine);
engine            270 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_oneinit(struct nvkm_engine *engine)
engine            272 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(engine);
engine            273 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_subdev *subdev = &disp->engine.subdev;
engine            381 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 			nvkm_error(&disp->engine.subdev,
engine            424 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_dtor(struct nvkm_engine *engine)
engine            426 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	struct nvkm_disp *disp = nvkm_disp(engine);
engine            483 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c 	return nvkm_engine_ctor(&nvkm_disp, device, index, true, &disp->engine);
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine             39 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine             54 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             41 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             70 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            110 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            119 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            170 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            180 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            190 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            217 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            249 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            277 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            281 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 		sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ);
engine            283 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 		sclass->engine = NULL;
engine            285 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 	if (sclass->engine && sclass->engine->func->base.sclass) {
engine            286 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c 		sclass->engine->func->base.sclass(sclass, index, &oclass);
engine             37 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c 	struct nvkm_gpio *gpio = disp->engine.subdev.device->gpio;
engine             82 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c 	struct nvkm_gpio *gpio = disp->engine.subdev.device->gpio;
engine             28 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h 	nvkm_##l(&_conn->disp->engine.subdev, "conn %02x:%02x%02x: "f"\n",     \
engine            172 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine            190 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine            138 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            157 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            166 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            175 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine            169 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine            187 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             42 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             27 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c 	struct nvkm_device *device = dac->disp->engine.subdev.device;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c 	struct nvkm_device *device = dac->disp->engine.subdev.device;
engine             67 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c 	struct nvkm_device *device = dac->disp->engine.subdev.device;
engine             39 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c 	struct nvkm_device *device = dac->disp->engine.subdev.device;
engine             69 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c 	struct nvkm_device *device = dac->disp->engine.subdev.device;
engine             86 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c 	struct nvkm_device *device = dac->disp->engine.subdev.device;
engine            118 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             41 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             62 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             82 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine            102 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c 	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
engine             78 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios;
engine            224 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	struct nvkm_subdev *subdev = &disp->engine.subdev;
engine            237 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	if (disp->engine.subdev.device->chipset < 0xd0)
engine            294 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[1],
engine            306 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 		nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[2],
engine            312 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 		nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[3],
engine            320 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
engine            428 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	nvbios_init(&ior->disp->engine.subdev, dp->info.script[4],
engine            573 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	struct nvkm_gpio *gpio = outp->disp->engine.subdev.device->gpio;
engine            630 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine            683 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c;
engine             38 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             92 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            124 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            180 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            188 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine             33 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             44 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             99 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            130 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            172 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            201 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            221 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            241 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            266 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            306 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            313 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             28 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigv100.c 	struct nvkm_device *device = ior->disp->engine.subdev.device;
engine             49 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h 	nvkm_##l(&_h->disp->engine.subdev, "head-%d: "f"\n", _h->id, ##a);     \
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             37 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine            101 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             27 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             41 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             93 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine            102 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgv100.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv04.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             50 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/disp/headnv50.c 	struct nvkm_device *device = head->disp->engine.subdev.device;
engine            168 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h 	nvkm_##l(&_ior->disp->engine.subdev, "%s: "f"\n", _ior->name, ##a);    \
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c 	struct nvkm_subdev *subdev = &disp->engine.subdev;
engine             86 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            186 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_bios *bios = head->disp->engine.subdev.device->bios;
engine            200 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_subdev *subdev = &head->disp->engine.subdev;
engine            269 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	nvbios_init(&head->disp->engine.subdev, iedt.script[id],
engine            327 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_subdev *subdev = &head->disp->engine.subdev;
engine            480 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_devinit *devinit = disp->base.engine.subdev.device->devinit;
engine            548 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            616 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine            650 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            686 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            695 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine            250 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c 	struct nvkm_i2c *i2c = disp->engine.subdev.device->i2c;
engine             50 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h 	nvkm_##l(&_outp->disp->engine.subdev, "outp %02x:%04x:%04x: "f"\n",    \
engine             33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
engine             33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c 	struct nvkm_device *device = pior->disp->engine.subdev.device;
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c 	struct nvkm_device *device = pior->disp->engine.subdev.device;
engine            100 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c 	struct nvkm_device *device = pior->disp->engine.subdev.device;
engine            136 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             40 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             78 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             86 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            105 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            125 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            142 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine            171 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            213 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            239 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            288 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             39 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             48 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             63 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             93 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            101 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            122 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            138 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            192 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c 	struct nvkm_device *device = outp->disp->engine.subdev.device;
engine             68 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c 	struct nvkm_device *device = outp->disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             37 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             46 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            118 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             69 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine            103 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c 	struct nvkm_device *device = disp->engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             40 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c 	struct nvkm_device *device = sor->disp->engine.subdev.device;
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c 	struct nvkm_device *device = disp->base.engine.subdev.device;
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine            133 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c 	struct nvkm_device *device = chan->disp->base.engine.subdev.device;
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	struct nvkm_dma *dma = nvkm_dma(oclass->engine);
engine             55 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	return nvkm_dma_oclass_new(oclass->engine->subdev.device,
engine             93 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c nvkm_dma_dtor(struct nvkm_engine *engine)
engine             95 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	return nvkm_dma(engine);
engine            115 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c 	return nvkm_engine_ctor(&nvkm_dma, device, index, true, &dma->engine);
engine              4 drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h #define nvkm_dma(p) container_of((p), struct nvkm_dma, engine)
engine             75 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	struct nvkm_device *device = dma->engine.subdev.device;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
engine             44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
engine             42 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
engine             84 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	struct nvkm_device *device = dma->engine.subdev.device;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine);
engine             49 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	return nvkm_gpuobj_new(object->engine->subdev.device, 256,
engine             59 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_falcon_intr(struct nvkm_engine *engine)
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_falcon *falcon = nvkm_falcon(engine);
engine             62 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_subdev *subdev = &falcon->engine.subdev;
engine             96 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend)
engine             98 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_falcon *falcon = nvkm_falcon(engine);
engine             99 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_device *device = falcon->engine.subdev.device;
engine            111 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	if (nvkm_mc_enabled(device, engine->subdev.index)) {
engine            129 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_falcon_oneinit(struct nvkm_engine *engine)
engine            131 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_falcon *falcon = nvkm_falcon(engine);
engine            132 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_subdev *subdev = &falcon->engine.subdev;
engine            160 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_falcon_init(struct nvkm_engine *engine)
engine            162 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_falcon *falcon = nvkm_falcon(engine);
engine            163 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	struct nvkm_subdev *subdev = &falcon->engine.subdev;
engine            321 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_falcon_dtor(struct nvkm_engine *engine)
engine            323 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	return nvkm_falcon(engine);
engine            352 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 	*pengine = &falcon->engine;
engine            355 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 				enable, &falcon->engine);
engine            223 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine);
engine            238 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine);
engine            251 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine);
engine            275 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_intr(struct nvkm_engine *engine)
engine            277 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(engine);
engine            282 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_fini(struct nvkm_engine *engine, bool suspend)
engine            284 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(engine);
engine            291 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data)
engine            293 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(engine);
engine            305 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_oneinit(struct nvkm_engine *engine)
engine            307 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(engine);
engine            314 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_preinit(struct nvkm_engine *engine)
engine            316 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	nvkm_mc_reset(engine->subdev.device, NVKM_ENGINE_FIFO);
engine            320 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_init(struct nvkm_engine *engine)
engine            322 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(engine);
engine            328 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_dtor(struct nvkm_engine *engine)
engine            330 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	struct nvkm_fifo *fifo = nvkm_fifo(engine);
engine            368 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c 	ret = nvkm_engine_ctor(&nvkm_fifo, device, index, true, &fifo->engine);
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_engine *engine  = object->oproxy.object->engine;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index];
engine             46 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	const char *name = nvkm_subdev_name[engine->subdev.index];
engine             53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		ret = chan->func->engine_fini(chan, engine, suspend);
engine             76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_engine *engine  = object->oproxy.object->engine;
engine             78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index];
engine             79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	const char *name = nvkm_subdev_name[engine->subdev.index];
engine             92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		ret = chan->func->engine_init(chan, engine);
engine            109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_engine *engine  = object->oproxy.base.engine;
engine            111 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index];
engine            118 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			chan->func->engine_dtor(chan, engine);
engine            121 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			atomic_dec(&chan->vmm->engref[engine->subdev.index]);
engine            136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_engine *engine = oclass->engine;
engine            138 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index];
engine            151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			.engine = oclass->engine,
engine            155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			atomic_inc(&chan->vmm->engref[engine->subdev.index]);
engine            157 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		if (engine->func->fifo.cclass) {
engine            158 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			ret = engine->func->fifo.cclass(chan, &cclass,
engine            161 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		if (engine->func->cclass) {
engine            162 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			ret = nvkm_object_new_(engine->func->cclass, &cclass,
engine            169 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			ret = chan->func->engine_ctor(chan, oclass->engine,
engine            185 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 					.engine = engine,
engine            206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine            207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_engine *engine;
engine            212 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		if (!(engine = nvkm_device_engine(device, i)))
engine            214 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		oclass->engine = engine;
engine            217 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		if (engine->func->fifo.sclass) {
engine            218 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 			ret = engine->func->fifo.sclass(oclass, index);
engine            230 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 		while (engine->func->sclass[c].oclass) {
engine            232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 				oclass->base = engine->func->sclass[index];
engine            360 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             48 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_engine(struct nvkm_engine *engine)
engine             50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	switch (engine->subdev.index) {
engine             68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
engine             70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	switch (engine->subdev.index) {
engine             91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 			  struct nvkm_engine *engine, bool suspend)
engine             95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            101 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	offset = g84_fifo_chan_engine_addr(engine);
engine            105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	engn = g84_fifo_chan_engine(engine);
engine            134 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 			  struct nvkm_engine *engine)
engine            137 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index];
engine            141 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	offset = g84_fifo_chan_engine_addr(engine);
engine            161 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 			  struct nvkm_engine *engine,
engine            165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	int engn = engine->subdev.index;
engine            167 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	if (g84_fifo_chan_engine_addr(engine) < 0)
engine            181 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	switch (object->engine->subdev.index) {
engine            209 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            236 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_engine_addr(struct nvkm_engine *engine)
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	switch (engine->subdev.index) {
engine             47 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 			   struct nvkm_engine *engine, bool suspend)
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine             56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	offset = nv50_fifo_chan_engine_addr(engine);
engine            103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 			   struct nvkm_engine *engine)
engine            106 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index];
engine            110 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	offset = nv50_fifo_chan_engine_addr(engine);
engine            130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 			   struct nvkm_engine *engine)
engine            133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	nvkm_gpuobj_del(&chan->engn[engine->subdev.index]);
engine            138 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 			   struct nvkm_engine *engine,
engine            142 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	int engn = engine->subdev.index;
engine            144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	if (nv50_fifo_chan_engine_addr(engine) < 0)
engine            165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	switch (object->engine->subdev.index) {
engine            183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            235 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
engine             41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	mutex_lock(&chan->fifo->base.engine.subdev.mutex);
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
engine             56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	switch (object->engine->subdev.index) {
engine             66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	mutex_lock(&chan->fifo->base.engine.subdev.mutex);
engine             69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
engine             78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            131 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
engine            174 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
engine             38 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	switch (engine->subdev.index) {
engine             47 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 		if (engine->subdev.device->chipset < 0x44)
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 			  struct nvkm_engine *engine, bool suspend)
engine             64 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	if (!nv40_fifo_dma_engine(engine, &reg, &ctx))
engine             90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 			  struct nvkm_engine *engine)
engine             94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            100 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	if (!nv40_fifo_dma_engine(engine, &reg, &ctx))
engine            102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	inst = chan->engn[engine->subdev.index]->addr >> 4;
engine            121 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 			  struct nvkm_engine *engine)
engine            124 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	nvkm_gpuobj_del(&chan->engn[engine->subdev.index]);
engine            129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 			  struct nvkm_engine *engine,
engine            133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	const int engn = engine->subdev.index;
engine            136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	if (!nv40_fifo_dma_engine(engine, &reg, &ctx))
engine            147 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
engine            152 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	switch (object->engine->subdev.index) {
engine            162 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	mutex_lock(&chan->fifo->base.engine.subdev.mutex);
engine            165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
engine            192 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             46 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine             95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	mutex_lock(&fifo->base.engine.subdev.mutex);
engine             97 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	mutex_unlock(&fifo->base.engine.subdev.mutex);
engine            103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	mutex_lock(&fifo->base.engine.subdev.mutex);
engine            105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	mutex_unlock(&fifo->base.engine.subdev.mutex);
engine            128 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            148 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            149 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_engine *engine;
engine            164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 		if ((engine = nvkm_device_engine(device, engn))) {
engine            165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 			nvkm_subdev_fini(&engine->subdev, false);
engine            166 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 			WARN_ON(nvkm_subdev_init(&engine->subdev));
engine            176 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
engine            179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            184 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 		   nvkm_subdev_name[engine->subdev.index], chid);
engine            191 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	if (engine != &fifo->base.engine)
engine            192 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 		fifo->recover.mask |= 1ULL << engine->subdev.index;
engine            260 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            263 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_engine *engine = NULL;
engine            269 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine);
engine            289 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 			engine = nvkm_device_engine(device, eu->data2);
engine            300 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 		   info->engine, eu ? eu->name : "",
engine            305 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	if (engine && chan)
engine            306 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 		gf100_fifo_recover(fifo, engine, (void *)chan);
engine            319 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            320 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_engine *engine;
engine            338 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 					engine = gf100_fifo_engine(fifo, engn);
engine            339 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 					if (!engine)
engine            341 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 					gf100_fifo_recover(fifo, engine, chan);
engine            353 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            375 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine            385 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	info.engine = unit;
engine            407 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            445 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            464 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            489 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            502 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            577 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            624 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            660 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_engine *engine = fifo->engine[engn].engine;
engine             56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			if (engine && nvkm_engine_chsw_load(engine))
engine            140 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine            147 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine            155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            213 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	mutex_lock(&fifo->base.engine.subdev.mutex);
engine            219 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	mutex_unlock(&fifo->base.engine.subdev.mutex);
engine            226 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	mutex_lock(&fifo->base.engine.subdev.mutex);
engine            234 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	mutex_unlock(&fifo->base.engine.subdev.mutex);
engine            255 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            262 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            279 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_engine *engine;
engine            294 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		if ((engine = fifo->engine[engn].engine)) {
engine            295 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			nvkm_subdev_fini(&engine->subdev, false);
engine            296 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			WARN_ON(nvkm_subdev_init(&engine->subdev));
engine            312 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            359 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            398 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_engine *engine = fifo->engine[engn].engine;
engine            399 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            401 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	const u32 runl = fifo->engine[engn].runl;
engine            424 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	if (!status.faulted && engine) {
engine            425 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		mmui = nvkm_top_fault_id(device, engine->subdev.index);
engine            427 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			const struct nvkm_enum *en = fifo->func->fault.engine;
engine            429 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 				if (en->data2 == engine->subdev.index) {
engine            468 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            471 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_engine *engine = NULL;
engine            478 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	ee = nvkm_enum_find(fifo->func->fault.engine, info->engine);
engine            499 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			engine = nvkm_device_engine(device, ee->data2);
engine            505 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		enum nvkm_devidx engidx = nvkm_top_fault(device, info->engine);
engine            512 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			engine = nvkm_device_engine(device, engidx);
engine            525 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		   info->engine, ee ? ee->name : en,
engine            538 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	for (engn = 0; engn < fifo->engine_nr && engine; engn++) {
engine            539 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		if (fifo->engine[engn].engine == engine) {
engine            562 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            581 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            612 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            633 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            643 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            686 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            735 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            756 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            776 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            868 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            887 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 			struct nvkm_engine *engine;
engine            890 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 				if ((engine = fifo->engine[engn].engine))
engine            891 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 					*data |= BIT_ULL(engine->subdev.index);
engine            906 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            937 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		fifo->engine[engn].engine = nvkm_device_engine(device, engidx);
engine            938 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		fifo->engine[engn].runl = runl;
engine            939 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 		fifo->engine[engn].pbid = pbid;
engine            981 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine           1013 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine           1185 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c 	.fault.engine = gk104_fifo_fault_engine,
engine             25 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h 		struct nvkm_engine *engine;
engine             28 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h 	} engine[16];
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h 		const struct nvkm_enum *engine;
engine             54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c 	.fault.engine = gk104_fifo_fault_engine,
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c 	.fault.engine = gk104_fifo_fault_engine,
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c 	.fault.engine = gk104_fifo_fault_engine,
engine             74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c 	info.engine = unit;
engine            100 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c 	.fault.engine = gm107_fifo_fault_engine,
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             48 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c 	.fault.engine = gm107_fifo_fault_engine,
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c 	.fault.engine = gm107_fifo_fault_engine,
engine             58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c 	struct nvkm_device *device = fifo->engine.subdev.device;
engine             68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c 	info.engine = unit;
engine             84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c 	.fault.engine = gp100_fifo_fault_engine,
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c 	.fault.engine = gp100_fifo_fault_engine,
engine             53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
engine             55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	switch (engine->subdev.index) {
engine             71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 			      struct nvkm_engine *engine, bool suspend)
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
engine             75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev;
engine            107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 			      struct nvkm_engine *engine)
engine            109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
engine            114 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 		u64 addr = chan->engn[engine->subdev.index].vma->addr;
engine            126 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 			      struct nvkm_engine *engine)
engine            129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma);
engine            130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
engine            135 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 			      struct nvkm_engine *engine,
engine            139 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	int engn = engine->subdev.index;
engine            142 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	if (!gf100_fifo_gpfifo_engine_addr(engine))
engine            163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            182 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine             68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	mutex_lock(&chan->base.fifo->engine.subdev.mutex);
engine             70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	mutex_unlock(&chan->base.fifo->engine.subdev.mutex);
engine             75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
engine             77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	switch (engine->subdev.index) {
engine             99 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			      struct nvkm_engine *engine, bool suspend)
engine            103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
engine            126 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			      struct nvkm_engine *engine)
engine            130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
engine            133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 		u64   addr = chan->engn[engine->subdev.index].vma->addr;
engine            151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			      struct nvkm_engine *engine)
engine            154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma);
engine            155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
engine            160 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			      struct nvkm_engine *engine,
engine            164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	int engn = engine->subdev.index;
engine            167 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	if (!gk104_fifo_gpfifo_engine_addr(engine))
engine            188 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            260 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 		if (fifo->engine[i].engine)
engine            261 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c 			subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
engine             40 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	struct nvkm_subdev *subdev = &chan->base.fifo->engine.subdev;
engine             67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 			      struct nvkm_engine *engine, bool suspend)
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
engine             74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	    engine->subdev.index <= NVKM_ENGINE_CE_LAST)
engine             90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 			      struct nvkm_engine *engine)
engine             96 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
engine             97 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	    engine->subdev.index <= NVKM_ENGINE_CE_LAST)
engine            100 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	addr = chan->engn[engine->subdev.index].vma->addr;
engine            129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            143 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 		if (fifo->engine[i].engine)
engine            144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c 			subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
engine            293 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c 	.fault.engine = gv100_fifo_fault_engine,
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             88 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            114 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	u32 engine = nvkm_rd32(device, 0x003280);
engine            119 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 		nvkm_wr32(device, 0x003280, (engine &= ~mask));
engine            126 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 		if (!(engine & mask) && sw)
engine            139 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            190 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            243 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
engine            302 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c 	mutex_lock(&fifo->base.engine.subdev.mutex);
engine             56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c 	mutex_unlock(&fifo->base.engine.subdev.mutex);
engine             63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine              4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h #define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine             85 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c 	struct nvkm_device *device = fifo->base.engine.subdev.device;
engine            102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c 	.fault.engine = tu102_fifo_fault_engine,
engine             28 drivers/gpu/drm/nouveau/nvkm/engine/fifo/usergv100.c 	struct nvkm_device *device = object->engine->subdev.device;
engine             28 drivers/gpu/drm/nouveau/nvkm/engine/fifo/usertu102.c 	struct nvkm_device *device = object->engine->subdev.device;
engine             56 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_chsw_load(struct nvkm_engine *engine)
engine             58 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine             65 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile)
engine             67 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine             91 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(oclass->engine);
engine            116 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(oclass->engine);
engine            123 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_intr(struct nvkm_engine *engine)
engine            125 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine            130 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_oneinit(struct nvkm_engine *engine)
engine            132 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine            139 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_init(struct nvkm_engine *engine)
engine            141 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine            146 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_fini(struct nvkm_engine *engine, bool suspend)
engine            148 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine            155 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_dtor(struct nvkm_engine *engine)
engine            157 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	struct nvkm_gr *gr = nvkm_gr(engine);
engine            181 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c 	return nvkm_engine_ctor(&nvkm_gr, device, index, enable, &gr->engine);
engine           1012 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = info->gr->base.engine.subdev.device;
engine           1035 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1097 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1117 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1163 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1273 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1309 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1317 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1327 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1371 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1442 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            774 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            190 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            200 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            851 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            866 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c 	struct nvkm_device *device = info->gr->base.engine.subdev.device;
engine            906 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            918 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            925 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            932 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            819 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            871 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            951 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000001);
engine            957 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             33 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             40 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             48 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x4041c4, tmp);
engine             79 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000000);
engine             85 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             27 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             98 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            116 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            153 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            160 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            169 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            180 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             98 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            118 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine             51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             67 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
engine            102 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            114 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
engine            163 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
engine            209 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
engine            327 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
engine            387 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            721 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	return nvkm_rd32(gr->engine.subdev.device, 0x409b00);
engine            727 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            777 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            796 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            813 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            830 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            868 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            884 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            900 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            916 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            928 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
engine            932 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
engine            942 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            957 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
engine            993 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1022 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1039 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1077 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1176 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1237 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1303 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1351 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1477 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1496 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1508 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1549 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1650 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1691 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1778 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1941 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1990 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &base->engine.subdev;
engine           2019 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
engine           2036 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           2100 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           2147 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	ret = nvkm_firmware_get(&gr->base.engine.subdev, fwname, &fw);
engine           2203 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464);
engine           2209 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2217 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2224 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2231 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2245 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000);
engine           2252 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
engine           2258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2274 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2281 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           2316 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            109 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x405a14, 0x80000000);
engine            126 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            393 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000);
engine            399 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            408 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            417 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            432 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            341 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            189 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            214 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            222 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63);
engine            296 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            304 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            311 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            346 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            365 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             38 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c 	return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
engine             44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             82 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             90 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000f0002);
engine             96 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             47 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
engine             88 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine             58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             65 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             77 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             84 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1046 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align,
engine           1074 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1087 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_device *device = chan->gr->base.engine.subdev.device;
engine           1102 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_device *device = chan->gr->base.engine.subdev.device;
engine           1116 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1165 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1213 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_subdev *subdev = &gr->engine.subdev;
engine           1275 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1331 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            433 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = chan->object.engine->subdev.device;
engine            506 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = chan->object.engine->subdev.device;
engine            549 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            564 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            583 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            633 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            788 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            801 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            815 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            886 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            913 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            934 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            958 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1007 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1052 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine           1084 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine           1139 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             89 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
engine            152 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            183 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            223 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c 	return nvkm_memory_new(gr->base.engine.subdev.device,
engine            232 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
engine            107 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c 	ret = nvkm_memory_new(gr->base.engine.subdev.device,
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	return nvkm_rd32(gr->engine.subdev.device, 0x1540);
engine             47 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align,
engine             79 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
engine             84 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
engine             96 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            134 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
engine            136 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
engine            162 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
engine            164 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
engine            176 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine            236 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            251 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	spin_lock_irqsave(&gr->base.engine.lock, flags);
engine            283 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	spin_unlock_irqrestore(&gr->base.engine.lock, flags);
engine            290 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	return nvkm_rd32(gr->engine.subdev.device, 0x1540);
engine             46 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
engine             77 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
engine            242 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            284 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            328 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            398 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            623 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	struct nvkm_subdev *subdev = &gr->base.engine.subdev;
engine            682 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 	struct nvkm_device *device = gr->base.engine.subdev.device;
engine              4 drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h #define nvkm_gr(p) container_of((p), struct nvkm_gr, engine)
engine             42 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align,
engine             71 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	spin_lock_irqsave(&mpeg->engine.lock, flags);
engine             74 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	spin_unlock_irqrestore(&mpeg->engine.lock, flags);
engine             88 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine);
engine            100 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	spin_lock_irqsave(&mpeg->engine.lock, flags);
engine            105 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	spin_unlock_irqrestore(&mpeg->engine.lock, flags);
engine            114 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)
engine            116 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nv31_mpeg *mpeg = nv31_mpeg(engine);
engine            117 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nvkm_device *device = mpeg->engine.subdev.device;
engine            128 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nvkm_subdev *subdev = &mpeg->engine.subdev;
engine            171 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nvkm_device *device = mpeg->engine.subdev.device;
engine            184 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nv31_mpeg_intr(struct nvkm_engine *engine)
engine            186 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nv31_mpeg *mpeg = nv31_mpeg(engine);
engine            187 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	struct nvkm_subdev *subdev = &mpeg->engine.subdev;
engine            196 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	spin_lock_irqsave(&mpeg->engine.lock, flags);
engine            221 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	spin_unlock_irqrestore(&mpeg->engine.lock, flags);
engine            257 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nv31_mpeg_dtor(struct nvkm_engine *engine)
engine            259 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	return nv31_mpeg(engine);
engine            284 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 	*pmpeg = &mpeg->engine;
engine            287 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 				true, &mpeg->engine);
engine              4 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h #define nv31_mpeg(p) container_of((p), struct nv31_mpeg, engine)
engine             10 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h 	struct nvkm_engine engine;
engine             35 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c 	struct nvkm_subdev *subdev = &mpeg->engine.subdev;
engine             24 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c #define nv44_mpeg(p) container_of((p), struct nv44_mpeg, engine)
engine             34 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	struct nvkm_engine engine;
engine             56 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	int ret = nvkm_gpuobj_new(chan->object.engine->subdev.device, 264 * 4,
engine             73 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	struct nvkm_device *device = mpeg->engine.subdev.device;
engine             89 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	spin_lock_irqsave(&mpeg->engine.lock, flags);
engine             91 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	spin_unlock_irqrestore(&mpeg->engine.lock, flags);
engine            107 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	struct nv44_mpeg *mpeg = nv44_mpeg(oclass->engine);
engine            118 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	spin_lock_irqsave(&mpeg->engine.lock, flags);
engine            120 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	spin_unlock_irqrestore(&mpeg->engine.lock, flags);
engine            143 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c nv44_mpeg_intr(struct nvkm_engine *engine)
engine            145 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	struct nv44_mpeg *mpeg = nv44_mpeg(engine);
engine            146 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	struct nvkm_subdev *subdev = &mpeg->engine.subdev;
engine            157 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	spin_lock_irqsave(&mpeg->engine.lock, flags);
engine            190 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	spin_unlock_irqrestore(&mpeg->engine.lock, flags);
engine            213 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	*pmpeg = &mpeg->engine;
engine            215 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 	return nvkm_engine_ctor(&nv44_mpeg, device, index, true, &mpeg->engine);
engine             40 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 128 * 4,
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c 	struct nvkm_device *device = mspdec->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c 	struct nvkm_device *device = mspdec->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c 	struct nvkm_device *device = msppp->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c 	struct nvkm_device *device = msppp->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c 	struct nvkm_device *device = msvld->engine.subdev.device;
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c 	struct nvkm_device *device = msvld->engine.subdev.device;
engine             28 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c nvkm_nvdec_oneinit(struct nvkm_engine *engine)
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c 	struct nvkm_nvdec *nvdec = nvkm_nvdec(engine);
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c 	struct nvkm_subdev *subdev = &nvdec->engine.subdev;
engine             43 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c nvkm_nvdec_dtor(struct nvkm_engine *engine)
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c 	struct nvkm_nvdec *nvdec = nvkm_nvdec(engine);
engine             66 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c 				&nvdec->engine);
engine            131 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	struct nvkm_subdev *subdev = &pm->engine.subdev;
engine            170 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	struct nvkm_subdev *subdev = &pm->engine.subdev;
engine            490 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine            631 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	mutex_lock(&pm->engine.subdev.mutex);
engine            634 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	mutex_unlock(&pm->engine.subdev.mutex);
engine            667 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	struct nvkm_pm *pm = nvkm_pm(oclass->engine);
engine            674 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	mutex_lock(&pm->engine.subdev.mutex);
engine            678 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	mutex_unlock(&pm->engine.subdev.mutex);
engine            823 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_pm_fini(struct nvkm_engine *engine, bool suspend)
engine            825 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	struct nvkm_pm *pm = nvkm_pm(engine);
engine            832 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_pm_dtor(struct nvkm_engine *engine)
engine            834 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	struct nvkm_pm *pm = nvkm_pm(engine);
engine            866 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	return nvkm_engine_ctor(&nvkm_pm, device, index, true, &pm->engine);
engine            131 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine            149 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine            163 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine            178 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine             47 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c 	struct nvkm_device *device = pm->engine.subdev.device;
engine              4 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h #define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c 	struct nvkm_subdev *subdev = &sec->engine.subdev;
engine             29 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c nvkm_sec2_dtor(struct nvkm_engine *engine)
engine             31 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
engine             38 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c nvkm_sec2_intr(struct nvkm_engine *engine)
engine             40 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
engine             41 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	struct nvkm_subdev *subdev = &engine->subdev;
engine             65 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 		nvkm_warn(&sec2->engine.subdev,
engine             75 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c nvkm_sec2_oneinit(struct nvkm_engine *engine)
engine             77 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
engine             78 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	struct nvkm_subdev *subdev = &sec2->engine.subdev;
engine             90 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
engine             92 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
engine            116 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c 	return nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine);
engine              6 drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h #define nvkm_sec2(p) container_of((p), struct nvkm_sec2, engine)
engine             36 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c 	spin_lock_irqsave(&sw->engine.lock, flags);
engine             45 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c 	spin_unlock_irqrestore(&sw->engine.lock, flags);
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c 	struct nvkm_sw *sw = nvkm_sw(oclass->engine);
engine             81 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c 	struct nvkm_sw *sw = nvkm_sw(oclass->engine);
engine             86 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c nvkm_sw_dtor(struct nvkm_engine *engine)
engine             88 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c 	return nvkm_sw(engine);
engine            109 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c 	return nvkm_engine_ctor(&nvkm_sw, device, index, true, &sw->engine);
engine             84 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c 	spin_lock_irqsave(&sw->engine.lock, flags);
engine             86 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c 	spin_unlock_irqrestore(&sw->engine.lock, flags);
engine            106 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c 	spin_lock_irqsave(&sw->engine.lock, flags);
engine            108 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c 	spin_unlock_irqrestore(&sw->engine.lock, flags);
engine             44 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c 	struct nvkm_device *device = sw->engine.subdev.device;
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c 	struct nvkm_engine *engine = chan->base.object.engine;
engine             61 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c 	struct nvkm_device *device = engine->subdev.device;
engine            109 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c 	struct nvkm_disp *disp = sw->engine.subdev.device->disp;
engine             44 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c 	struct nvkm_device *device = sw->engine.subdev.device;
engine             65 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c 	struct nvkm_engine *engine = chan->base.object.engine;
engine             66 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c 	struct nvkm_device *device = engine->subdev.device;
engine            103 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c 	struct nvkm_disp *disp = sw->engine.subdev.device->disp;
engine              4 drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h #define nvkm_sw(p) container_of((p), struct nvkm_sw, engine)
engine             30 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_xtensa *xtensa = nvkm_xtensa(oclass->engine);
engine             47 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	return nvkm_gpuobj_new(object->engine->subdev.device, 0x10000, align,
engine             57 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_xtensa_intr(struct nvkm_engine *engine)
engine             59 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
engine             60 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_subdev *subdev = &xtensa->engine.subdev;
engine             79 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_xtensa_fini(struct nvkm_engine *engine, bool suspend)
engine             81 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
engine             82 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_device *device = xtensa->engine.subdev.device;
engine             94 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_xtensa_init(struct nvkm_engine *engine)
engine             96 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
engine             97 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	struct nvkm_subdev *subdev = &xtensa->engine.subdev;
engine            162 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_xtensa_dtor(struct nvkm_engine *engine)
engine            164 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	return nvkm_xtensa(engine);
engine            188 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 	*pengine = &xtensa->engine;
engine            191 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 				enable, &xtensa->engine);
engine             60 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c 		info.engine = (info0 & 0x000000ff);
engine            140 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c 	info.engine = (info0 & 0x000000ff);
engine             87 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c 	info.engine = (info0 & 0x000000ff);
engine             54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c 			nvkm_engine_tile(&device->gr->engine, region);
engine            140 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c 		nvkm_engine_ref(&subdev->device->sec2->engine);
engine             51 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 	struct nvkm_engine *engine;
engine             62 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 	engine = nvkm_engine_ref(&device->nvdec[0]->engine);
engine             63 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 	if (IS_ERR(engine))
engine             64 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 		return PTR_ERR(engine);
engine            116 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 	nvkm_engine_unref(&engine);
engine             38 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c 	for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
engine             39 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c 		if (!nvkm_device_subdev(dev, order[i].engine))
engine             50 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c 	for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
engine             51 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c 		if (!nvkm_device_subdev(dev, order[i].engine))
engine             67 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c 	for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
engine             68 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c 		if (!nvkm_device_subdev(dev, order[i].engine))
engine             34 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h 	enum nvkm_devidx engine;
engine             34 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c 		info->engine = -1;
engine            150 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c 		if (info->engine >= 0 && info->runlist >= 0 && n++ == index) {
engine            152 drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c 			*engn = info->engine;
engine             56 drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c 				info->engine  = (data & 0x3c000000) >> 26;
engine            103 drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c 			   info->addr, info->fault, info->engine, info->runlist,
engine             18 drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h 	int engine;
engine            221 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	struct refill_engine *engine = txn->engine_handle;
engine            233 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
engine            239 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static int wait_status(struct refill_engine *engine, u32 wait_mask)
engine            241 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	struct dmm *dmm = engine->dmm;
engine            246 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		r = dmm_read(dmm, reg[PAT_STATUS][engine->id]);
engine            251 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 				__func__, engine->id, r);
engine            261 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 				__func__, engine->id, r);
engine            271 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static void release_engine(struct refill_engine *engine)
engine            276 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	list_add(&engine->idle_node, &omap_dmm->idle_head);
engine            317 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	struct refill_engine *engine = NULL;
engine            331 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		engine = list_entry(dmm->idle_head.next, struct refill_engine,
engine            333 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		list_del(&engine->idle_node);
engine            337 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	BUG_ON(!engine);
engine            339 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	txn = &engine->txn;
engine            340 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	engine->tcm = tcm;
engine            341 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	txn->engine_handle = engine;
engine            343 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	txn->current_va = engine->refill_va;
engine            344 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	txn->current_pa = engine->refill_pa;
engine            359 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	struct refill_engine *engine = txn->engine_handle;
engine            372 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	pat->area.y0 += engine->tcm->y_offset;
engine            373 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	pat->area.y1 += engine->tcm->y_offset;
engine            377 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 			.lut_id = engine->tcm->lut_id,
engine            389 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 			page_to_phys(pages[n]) : engine->dmm->dummy_pa;
engine            403 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	struct refill_engine *engine = txn->engine_handle;
engine            404 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	struct dmm *dmm = engine->dmm;
engine            407 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		dev_err(engine->dmm->dev, "need at least one txn\n");
engine            426 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);
engine            429 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	ret = wait_status(engine, DMM_PATSTATUS_READY);
engine            436 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	engine->async = wait ? false : true;
engine            437 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	reinit_completion(&engine->compl);
engine            442 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 	dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);
engine            445 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		if (!wait_for_completion_timeout(&engine->compl,
engine            453 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		ret = wait_status(engine, DMM_PATSTATUS_READY |
engine            460 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c 		release_engine(engine);
engine             46 drivers/gpu/drm/sun4i/sun4i_backend.c static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
engine             53 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
engine             57 drivers/gpu/drm/sun4i/sun4i_backend.c 		regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
engine             61 drivers/gpu/drm/sun4i/sun4i_backend.c static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
engine             66 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
engine             70 drivers/gpu/drm/sun4i/sun4i_backend.c static void sun4i_backend_commit(struct sunxi_engine *engine)
engine             74 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
engine             92 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
engine            177 drivers/gpu/drm/sun4i/sun4i_backend.c 		regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
engine            185 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
engine            192 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
engine            210 drivers/gpu/drm/sun4i/sun4i_backend.c 		regmap_write(backend->engine.regs,
engine            218 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
engine            251 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
engine            266 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
engine            273 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
engine            283 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs,
engine            298 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs,
engine            317 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs,
engine            322 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs,
engine            335 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
engine            338 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
engine            354 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs,
engine            368 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs,
engine            375 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
engine            392 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
engine            404 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_update_bits(backend->engine.regs,
engine            474 drivers/gpu/drm/sun4i/sun4i_backend.c static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
engine            479 drivers/gpu/drm/sun4i/sun4i_backend.c 	WARN_ON(regmap_read_poll_timeout(engine->regs,
engine            485 drivers/gpu/drm/sun4i/sun4i_backend.c static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
engine            489 drivers/gpu/drm/sun4i/sun4i_backend.c 	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
engine            629 drivers/gpu/drm/sun4i/sun4i_backend.c static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
engine            631 drivers/gpu/drm/sun4i/sun4i_backend.c 	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
engine            818 drivers/gpu/drm/sun4i/sun4i_backend.c 	backend->engine.node = dev->of_node;
engine            819 drivers/gpu/drm/sun4i/sun4i_backend.c 	backend->engine.ops = &sun4i_backend_engine_ops;
engine            820 drivers/gpu/drm/sun4i/sun4i_backend.c 	backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
engine            821 drivers/gpu/drm/sun4i/sun4i_backend.c 	if (backend->engine.id < 0)
engine            822 drivers/gpu/drm/sun4i/sun4i_backend.c 		return backend->engine.id;
engine            878 drivers/gpu/drm/sun4i/sun4i_backend.c 	backend->engine.regs = devm_regmap_init_mmio(dev, regs,
engine            880 drivers/gpu/drm/sun4i/sun4i_backend.c 	if (IS_ERR(backend->engine.regs)) {
engine            882 drivers/gpu/drm/sun4i/sun4i_backend.c 		return PTR_ERR(backend->engine.regs);
engine            885 drivers/gpu/drm/sun4i/sun4i_backend.c 	list_add_tail(&backend->engine.list, &drv->engine_list);
engine            896 drivers/gpu/drm/sun4i/sun4i_backend.c 		regmap_write(backend->engine.regs, i, 0);
engine            899 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
engine            903 drivers/gpu/drm/sun4i/sun4i_backend.c 	regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
engine            920 drivers/gpu/drm/sun4i/sun4i_backend.c 		regmap_update_bits(backend->engine.regs,
engine            923 drivers/gpu/drm/sun4i/sun4i_backend.c 				   (backend->engine.id
engine            948 drivers/gpu/drm/sun4i/sun4i_backend.c 	list_del(&backend->engine.list);
engine            170 drivers/gpu/drm/sun4i/sun4i_backend.h 	struct sunxi_engine	engine;
engine            190 drivers/gpu/drm/sun4i/sun4i_backend.h engine_to_sun4i_backend(struct sunxi_engine *engine)
engine            192 drivers/gpu/drm/sun4i/sun4i_backend.h 	return container_of(engine, struct sun4i_backend, engine);
engine             51 drivers/gpu/drm/sun4i/sun4i_crtc.c 	struct sunxi_engine *engine = scrtc->engine;
engine             54 drivers/gpu/drm/sun4i/sun4i_crtc.c 	if (engine && engine->ops && engine->ops->atomic_check)
engine             55 drivers/gpu/drm/sun4i/sun4i_crtc.c 		ret = engine->ops->atomic_check(engine, state);
engine             65 drivers/gpu/drm/sun4i/sun4i_crtc.c 	struct sunxi_engine *engine = scrtc->engine;
engine             77 drivers/gpu/drm/sun4i/sun4i_crtc.c 	if (engine->ops->atomic_begin)
engine             78 drivers/gpu/drm/sun4i/sun4i_crtc.c 		engine->ops->atomic_begin(engine, old_state);
engine             89 drivers/gpu/drm/sun4i/sun4i_crtc.c 	sunxi_engine_commit(scrtc->engine);
engine            187 drivers/gpu/drm/sun4i/sun4i_crtc.c 				   struct sunxi_engine *engine,
engine            198 drivers/gpu/drm/sun4i/sun4i_crtc.c 	scrtc->engine = engine;
engine            202 drivers/gpu/drm/sun4i/sun4i_crtc.c 	planes = sunxi_engine_layers_init(drm, engine);
engine             16 drivers/gpu/drm/sun4i/sun4i_crtc.h 	struct sunxi_engine		*engine;
engine             26 drivers/gpu/drm/sun4i/sun4i_crtc.h 				   struct sunxi_engine *engine,
engine            232 drivers/gpu/drm/sun4i/sun4i_layer.c 				     struct sunxi_engine *engine)
engine            235 drivers/gpu/drm/sun4i/sun4i_layer.c 	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
engine             40 drivers/gpu/drm/sun4i/sun4i_layer.h 				     struct sunxi_engine *engine);
engine            720 drivers/gpu/drm/sun4i/sun4i_tcon.c 	struct sunxi_engine *engine = scrtc->engine;
engine            740 drivers/gpu/drm/sun4i/sun4i_tcon.c 	if (engine->ops->vblank_quirk)
engine            741 drivers/gpu/drm/sun4i/sun4i_tcon.c 		engine->ops->vblank_quirk(engine);
engine            863 drivers/gpu/drm/sun4i/sun4i_tcon.c 	struct sunxi_engine *engine = ERR_PTR(-EINVAL);
engine            892 drivers/gpu/drm/sun4i/sun4i_tcon.c 	list_for_each_entry(engine, &drv->engine_list, list)
engine            893 drivers/gpu/drm/sun4i/sun4i_tcon.c 		if (remote == engine->node)
engine            910 drivers/gpu/drm/sun4i/sun4i_tcon.c 	engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
engine            919 drivers/gpu/drm/sun4i/sun4i_tcon.c 	return engine;
engine            964 drivers/gpu/drm/sun4i/sun4i_tcon.c 	struct sunxi_engine *engine;
engine            966 drivers/gpu/drm/sun4i/sun4i_tcon.c 	list_for_each_entry(engine, &drv->engine_list, list)
engine            967 drivers/gpu/drm/sun4i/sun4i_tcon.c 		if (engine->id == id)
engine            968 drivers/gpu/drm/sun4i/sun4i_tcon.c 			return engine;
engine           1041 drivers/gpu/drm/sun4i/sun4i_tcon.c 	struct sunxi_engine *engine;
engine           1072 drivers/gpu/drm/sun4i/sun4i_tcon.c 		engine = sun4i_tcon_get_engine_by_id(drv, id);
engine           1075 drivers/gpu/drm/sun4i/sun4i_tcon.c 		return engine;
engine           1088 drivers/gpu/drm/sun4i/sun4i_tcon.c 	struct sunxi_engine *engine;
engine           1095 drivers/gpu/drm/sun4i/sun4i_tcon.c 	engine = sun4i_tcon_find_engine(drv, dev->of_node);
engine           1096 drivers/gpu/drm/sun4i/sun4i_tcon.c 	if (IS_ERR(engine)) {
engine           1107 drivers/gpu/drm/sun4i/sun4i_tcon.c 	tcon->id = engine->id;
engine           1215 drivers/gpu/drm/sun4i/sun4i_tcon.c 	tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
engine            352 drivers/gpu/drm/sun4i/sun4i_tv.c 	sunxi_engine_disable_color_correction(crtc->engine);
engine            362 drivers/gpu/drm/sun4i/sun4i_tv.c 	sunxi_engine_apply_color_correction(crtc->engine);
engine            236 drivers/gpu/drm/sun4i/sun8i_csc.c 		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
engine            243 drivers/gpu/drm/sun4i/sun8i_csc.c 	sun8i_csc_set_coefficients(mixer->engine.regs, base,
engine            252 drivers/gpu/drm/sun4i/sun8i_csc.c 		sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable);
engine            258 drivers/gpu/drm/sun4i/sun8i_csc.c 	sun8i_csc_enable(mixer->engine.regs, base, enable);
engine            340 drivers/gpu/drm/sun4i/sun8i_mixer.c static void sun8i_mixer_commit(struct sunxi_engine *engine)
engine            344 drivers/gpu/drm/sun4i/sun8i_mixer.c 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
engine            349 drivers/gpu/drm/sun4i/sun8i_mixer.c 					    struct sunxi_engine *engine)
engine            352 drivers/gpu/drm/sun4i/sun8i_mixer.c 	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
engine            452 drivers/gpu/drm/sun4i/sun8i_mixer.c 	mixer->engine.ops = &sun8i_engine_ops;
engine            453 drivers/gpu/drm/sun4i/sun8i_mixer.c 	mixer->engine.node = dev->of_node;
engine            463 drivers/gpu/drm/sun4i/sun8i_mixer.c 	mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
engine            474 drivers/gpu/drm/sun4i/sun8i_mixer.c 	mixer->engine.regs = devm_regmap_init_mmio(dev, regs,
engine            476 drivers/gpu/drm/sun4i/sun8i_mixer.c 	if (IS_ERR(mixer->engine.regs)) {
engine            478 drivers/gpu/drm/sun4i/sun8i_mixer.c 		return PTR_ERR(mixer->engine.regs);
engine            518 drivers/gpu/drm/sun4i/sun8i_mixer.c 	list_add_tail(&mixer->engine.list, &drv->engine_list);
engine            525 drivers/gpu/drm/sun4i/sun8i_mixer.c 			regmap_write(mixer->engine.regs, i, 0);
engine            527 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0);
engine            528 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0);
engine            529 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0);
engine            530 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0);
engine            531 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0);
engine            532 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0);
engine            533 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0);
engine            534 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
engine            535 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
engine            536 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
engine            539 drivers/gpu/drm/sun4i/sun8i_mixer.c 			regmap_write(mixer->engine.regs, i, 0);
engine            541 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0);
engine            542 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0);
engine            543 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0);
engine            544 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0);
engine            545 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0);
engine            546 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0);
engine            547 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
engine            551 drivers/gpu/drm/sun4i/sun8i_mixer.c 	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
engine            555 drivers/gpu/drm/sun4i/sun8i_mixer.c 	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
engine            562 drivers/gpu/drm/sun4i/sun8i_mixer.c 	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
engine            564 drivers/gpu/drm/sun4i/sun8i_mixer.c 	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
engine            569 drivers/gpu/drm/sun4i/sun8i_mixer.c 		regmap_write(mixer->engine.regs,
engine            573 drivers/gpu/drm/sun4i/sun8i_mixer.c 	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
engine            590 drivers/gpu/drm/sun4i/sun8i_mixer.c 	list_del(&mixer->engine.list);
engine            182 drivers/gpu/drm/sun4i/sun8i_mixer.h 	struct sunxi_engine		engine;
engine            193 drivers/gpu/drm/sun4i/sun8i_mixer.h engine_to_sun8i_mixer(struct sunxi_engine *engine)
engine            195 drivers/gpu/drm/sun4i/sun8i_mixer.h 	return container_of(engine, struct sun8i_mixer, engine);
engine             43 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_update_bits(mixer->engine.regs,
engine             48 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_update_bits(mixer->engine.regs,
engine             53 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_update_bits(mixer->engine.regs,
engine             62 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_update_bits(mixer->engine.regs,
engine             68 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_update_bits(mixer->engine.regs,
engine            108 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_write(mixer->engine.regs,
engine            111 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_write(mixer->engine.regs,
engine            123 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		regmap_update_bits(mixer->engine.regs,
engine            136 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_write(mixer->engine.regs,
engine            139 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_write(mixer->engine.regs,
engine            163 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_write(mixer->engine.regs,
engine            166 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_write(mixer->engine.regs,
engine            189 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_update_bits(mixer->engine.regs,
engine            223 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_write(mixer->engine.regs,
engine            229 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	regmap_write(mixer->engine.regs,
engine            145 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val);
engine            169 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs,
engine            171 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs,
engine            173 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs,
engine            175 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs,
engine            177 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs,
engine            179 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 	regmap_write(mixer->engine.regs,
engine            184 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c 		regmap_write(mixer->engine.regs,
engine             36 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_update_bits(mixer->engine.regs,
engine             41 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_update_bits(mixer->engine.regs,
engine             46 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_update_bits(mixer->engine.regs,
engine             55 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_update_bits(mixer->engine.regs,
engine             61 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_update_bits(mixer->engine.regs,
engine            123 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            126 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            182 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            186 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            190 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            194 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            203 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            206 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_write(mixer->engine.regs,
engine            229 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_update_bits(mixer->engine.regs,
engine            247 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	regmap_update_bits(mixer->engine.regs,
engine            253 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_update_bits(mixer->engine.regs,
engine            304 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_write(mixer->engine.regs,
engine            312 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		regmap_write(mixer->engine.regs,
engine            922 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            967 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 		regmap_write(mixer->engine.regs,
engine            971 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            973 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            975 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            977 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            979 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            981 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            983 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            987 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            990 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            993 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            995 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	regmap_write(mixer->engine.regs,
engine            997 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c 	sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
engine             32 drivers/gpu/drm/sun4i/sunxi_engine.h 	void (*atomic_begin)(struct sunxi_engine *engine,
engine             49 drivers/gpu/drm/sun4i/sunxi_engine.h 	int (*atomic_check)(struct sunxi_engine *engine,
engine             61 drivers/gpu/drm/sun4i/sunxi_engine.h 	void (*commit)(struct sunxi_engine *engine);
engine             77 drivers/gpu/drm/sun4i/sunxi_engine.h 					  struct sunxi_engine *engine);
engine             87 drivers/gpu/drm/sun4i/sunxi_engine.h 	void (*apply_color_correction)(struct sunxi_engine *engine);
engine             97 drivers/gpu/drm/sun4i/sunxi_engine.h 	void (*disable_color_correction)(struct sunxi_engine *engine);
engine            110 drivers/gpu/drm/sun4i/sunxi_engine.h 	void (*vblank_quirk)(struct sunxi_engine *engine);
engine            137 drivers/gpu/drm/sun4i/sunxi_engine.h sunxi_engine_commit(struct sunxi_engine *engine)
engine            139 drivers/gpu/drm/sun4i/sunxi_engine.h 	if (engine->ops && engine->ops->commit)
engine            140 drivers/gpu/drm/sun4i/sunxi_engine.h 		engine->ops->commit(engine);
engine            149 drivers/gpu/drm/sun4i/sunxi_engine.h sunxi_engine_layers_init(struct drm_device *drm, struct sunxi_engine *engine)
engine            151 drivers/gpu/drm/sun4i/sunxi_engine.h 	if (engine->ops && engine->ops->layers_init)
engine            152 drivers/gpu/drm/sun4i/sunxi_engine.h 		return engine->ops->layers_init(drm, engine);
engine            166 drivers/gpu/drm/sun4i/sunxi_engine.h sunxi_engine_apply_color_correction(struct sunxi_engine *engine)
engine            168 drivers/gpu/drm/sun4i/sunxi_engine.h 	if (engine->ops && engine->ops->apply_color_correction)
engine            169 drivers/gpu/drm/sun4i/sunxi_engine.h 		engine->ops->apply_color_correction(engine);
engine            179 drivers/gpu/drm/sun4i/sunxi_engine.h sunxi_engine_disable_color_correction(struct sunxi_engine *engine)
engine            181 drivers/gpu/drm/sun4i/sunxi_engine.h 	if (engine->ops && engine->ops->disable_color_correction)
engine            182 drivers/gpu/drm/sun4i/sunxi_engine.h 		engine->ops->disable_color_correction(engine);
engine            210 drivers/gpu/drm/via/via_dmablit.c via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine)
engine            214 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_MAR0 + engine*0x10, 0);
engine            215 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_DAR0 + engine*0x10, 0);
engine            216 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
engine            218 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_MR0  + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
engine            219 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_BCR0 + engine*0x10, 0);
engine            220 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
engine            222 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
engine            223 drivers/gpu/drm/via/via_dmablit.c 	via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04);
engine            287 drivers/gpu/drm/via/via_dmablit.c via_abort_dmablit(struct drm_device *dev, int engine)
engine            291 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
engine            295 drivers/gpu/drm/via/via_dmablit.c via_dmablit_engine_off(struct drm_device *dev, int engine)
engine            299 drivers/gpu/drm/via/via_dmablit.c 	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
engine            312 drivers/gpu/drm/via/via_dmablit.c via_dmablit_handler(struct drm_device *dev, int engine, int from_irq)
engine            315 drivers/gpu/drm/via/via_dmablit.c 	drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
engine            322 drivers/gpu/drm/via/via_dmablit.c 		  engine, from_irq, (unsigned long) blitq);
engine            330 drivers/gpu/drm/via/via_dmablit.c 	  ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
engine            349 drivers/gpu/drm/via/via_dmablit.c 		via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04,  VIA_DMA_CSR_TD);
engine            361 drivers/gpu/drm/via/via_dmablit.c 		via_abort_dmablit(dev, engine);
engine            368 drivers/gpu/drm/via/via_dmablit.c 			via_fire_dmablit(dev, blitq->blits[cur], engine);
engine            378 drivers/gpu/drm/via/via_dmablit.c 			via_dmablit_engine_off(dev, engine);
engine            395 drivers/gpu/drm/via/via_dmablit.c via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue)
engine            427 drivers/gpu/drm/via/via_dmablit.c via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine)
engine            431 drivers/gpu/drm/via/via_dmablit.c 	drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
engine            435 drivers/gpu/drm/via/via_dmablit.c 	if (via_dmablit_active(blitq, engine, handle, &queue)) {
engine            437 drivers/gpu/drm/via/via_dmablit.c 			    !via_dmablit_active(blitq, engine, handle, NULL));
engine            440 drivers/gpu/drm/via/via_dmablit.c 		  handle, engine, ret);
engine            461 drivers/gpu/drm/via/via_dmablit.c 	int engine = (int)
engine            464 drivers/gpu/drm/via/via_dmablit.c 	DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine,
engine            467 drivers/gpu/drm/via/via_dmablit.c 	via_dmablit_handler(dev, engine, 0);
engine            477 drivers/gpu/drm/via/via_dmablit.c 	       via_dmablit_handler(dev, engine, 0);
engine            677 drivers/gpu/drm/via/via_dmablit.c via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine)
engine            727 drivers/gpu/drm/via/via_dmablit.c 	int engine;
engine            735 drivers/gpu/drm/via/via_dmablit.c 	engine = (xfer->to_fb) ? 0 : 1;
engine            736 drivers/gpu/drm/via/via_dmablit.c 	blitq = dev_priv->blit_queues + engine;
engine            737 drivers/gpu/drm/via/via_dmablit.c 	if (0 != (ret = via_dmablit_grab_slot(blitq, engine)))
engine            757 drivers/gpu/drm/via/via_dmablit.c 	xfer->sync.engine = engine;
engine            759 drivers/gpu/drm/via/via_dmablit.c 	via_dmablit_handler(dev, engine, 0);
engine            777 drivers/gpu/drm/via/via_dmablit.c 	if (sync->engine >= VIA_NUM_BLIT_ENGINES)
engine            780 drivers/gpu/drm/via/via_dmablit.c 	err = via_dmablit_sync(dev, sync->sync_handle, sync->engine);
engine            226 drivers/gpu/drm/via/via_drv.h extern void via_dmablit_handler(struct drm_device *dev, int engine, int from_irq);
engine             79 drivers/iio/adc/ingenic-adc.c 			       int engine,
engine             88 drivers/iio/adc/ingenic-adc.c 		val |= BIT(engine);
engine             90 drivers/iio/adc/ingenic-adc.c 		val &= ~BIT(engine);
engine             97 drivers/iio/adc/ingenic-adc.c 			       int engine)
engine            102 drivers/iio/adc/ingenic-adc.c 	ingenic_adc_enable(adc, engine, true);
engine            104 drivers/iio/adc/ingenic-adc.c 				 !(val & BIT(engine)), 250, 1000);
engine            106 drivers/iio/adc/ingenic-adc.c 		ingenic_adc_enable(adc, engine, false);
engine           5784 drivers/infiniband/hw/hfi1/chip.c static int engine_to_vl(struct hfi1_devdata *dd, int engine)
engine           5790 drivers/infiniband/hw/hfi1/chip.c 	if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
engine           5795 drivers/infiniband/hw/hfi1/chip.c 	vl = m->engine_to_vl[engine];
engine           13170 drivers/infiniband/hw/hfi1/chip.c void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr)
engine           13179 drivers/infiniband/hw/hfi1/chip.c 	remap_intr(dd, IS_SDMA_START + engine, msix_intr);
engine           13180 drivers/infiniband/hw/hfi1/chip.c 	remap_intr(dd, IS_SDMA_PROGRESS_START + engine, msix_intr);
engine           13181 drivers/infiniband/hw/hfi1/chip.c 	remap_intr(dd, IS_SDMA_IDLE_START + engine, msix_intr);
engine           1449 drivers/infiniband/hw/hfi1/chip.h void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr);
engine           1897 drivers/infiniband/hw/hfi1/rc.c 			struct sdma_engine *engine;
engine           1903 drivers/infiniband/hw/hfi1/rc.c 			engine = qp_to_sdma_engine(qp, sc5);
engine           1904 drivers/infiniband/hw/hfi1/rc.c 			sdma_engine_progress_schedule(engine);
engine           1204 drivers/infiniband/hw/hfi1/sdma.c 	int engine = 0;
engine           1237 drivers/infiniband/hw/hfi1/sdma.c 		int first_engine = engine;
engine           1253 drivers/infiniband/hw/hfi1/sdma.c 					&dd->per_sdma[engine];
engine           1254 drivers/infiniband/hw/hfi1/sdma.c 				if (++engine >= first_engine + vl_engines[i])
engine           1256 drivers/infiniband/hw/hfi1/sdma.c 					engine = first_engine;
engine           1265 drivers/infiniband/hw/hfi1/sdma.c 		engine = first_engine + vl_engines[i];
engine            453 drivers/infiniband/hw/hfi1/sdma.h static inline int __sdma_running(struct sdma_engine *engine)
engine            455 drivers/infiniband/hw/hfi1/sdma.h 	return engine->state.current_state == sdma_state_s99_running;
engine            469 drivers/infiniband/hw/hfi1/sdma.h static inline int sdma_running(struct sdma_engine *engine)
engine            474 drivers/infiniband/hw/hfi1/sdma.h 	spin_lock_irqsave(&engine->tail_lock, flags);
engine            475 drivers/infiniband/hw/hfi1/sdma.h 	ret = __sdma_running(engine);
engine            476 drivers/infiniband/hw/hfi1/sdma.h 	spin_unlock_irqrestore(&engine->tail_lock, flags);
engine            393 drivers/leds/leds-lp5521.c 	struct lp55xx_engine *engine = &chip->engines[nr - 1];
engine            401 drivers/leds/leds-lp5521.c 		engine->mode = LP55XX_ENGINE_RUN;
engine            405 drivers/leds/leds-lp5521.c 		engine->mode = LP55XX_ENGINE_LOAD;
engine            408 drivers/leds/leds-lp5521.c 		engine->mode = LP55XX_ENGINE_DISABLED;
engine            416 drivers/leds/leds-lp5523.c 	struct lp55xx_engine *engine = &chip->engines[nr - 1];
engine            424 drivers/leds/leds-lp5523.c 		engine->mode = LP55XX_ENGINE_RUN;
engine            428 drivers/leds/leds-lp5523.c 		engine->mode = LP55XX_ENGINE_LOAD;
engine            431 drivers/leds/leds-lp5523.c 		engine->mode = LP55XX_ENGINE_DISABLED;
engine            495 drivers/leds/leds-lp5523.c 	struct lp55xx_engine *engine = &chip->engines[nr - 1];
engine            517 drivers/leds/leds-lp5523.c 	engine->led_mux = mux;
engine            527 drivers/leds/leds-lp5523.c 	struct lp55xx_engine *engine = &chip->engines[nr - 1];
engine            539 drivers/leds/leds-lp5523.c 	if (engine->mode != LP55XX_ENGINE_LOAD)
engine             95 drivers/misc/habanalabs/goya/goya.c #define IS_QM_IDLE(engine, qm_glbl_sts0) \
engine             96 drivers/misc/habanalabs/goya/goya.c 	(((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
engine            101 drivers/misc/habanalabs/goya/goya.c #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
engine            102 drivers/misc/habanalabs/goya/goya.c 	(((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
engine            103 drivers/misc/habanalabs/goya/goya.c 			engine##_CMDQ_IDLE_MASK)
engine            422 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
engine           4466 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
engine           4469 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	u32 bit = engine ?
engine           4553 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
engine           4555 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
engine           4557 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
engine           4566 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	   engine, val);
engine            868 drivers/net/ethernet/marvell/mvpp2/mvpp2.h 	u8 engine;
engine            411 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 				   int engine)
engine            414 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	fe->data[0] |= MVPP2_CLS_FLOW_TBL0_ENG(engine);
engine            739 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	int i, engine, flow_index;
engine            757 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 			engine = MVPP22_CLS_ENGINE_C3HB;
engine            759 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 			engine = MVPP22_CLS_ENGINE_C3HA;
engine            764 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 		mvpp2_cls_flow_eng_set(&fe, engine);
engine           1204 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	if (rule->engine != MVPP22_CLS_ENGINE_C2)
engine           1222 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 		mvpp2_cls_flow_eng_set(&fe, rule->engine);
engine           1322 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c 	rule->engine = MVPP22_CLS_ENGINE_C2;
engine            172 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	int flow_index, engine;
engine            182 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	engine = mvpp2_cls_flow_eng_get(&fe);
engine            184 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c 	seq_printf(s, "%d\n", engine);
engine           8059 drivers/net/ethernet/qlogic/qed/qed_debug.c 				   int engine, u32 feature_size, u8 omit_engine)
engine           8066 drivers/net/ethernet/qlogic/qed/qed_debug.c 	       (engine << REGDUMP_HEADER_ENGINE_SHIFT);
engine            253 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	data = (MT_DFS_CH_EN << 16) | pulse->engine;
engine            277 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (pulse->engine > 3)
engine            280 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (pulse->engine == 3) {
engine            301 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (pulse->engine >= 3)
engine            321 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (pulse->engine > 3)
engine            324 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (pulse->engine == 3) {
engine            380 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	event->engine = MT_DFS_EVENT_ENGINE(data);
engine            392 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	if (event->engine == 2) {
engine            415 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	event_buff = event->engine == 2 ? &dfs_pd->event_rb[1]
engine            438 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 	event_rb = event->engine == 2 ? &dfs_pd->event_rb[1]
engine            458 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 			if (event->engine == 2)
engine            481 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		seq.engine = event->engine;
engine            530 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		if (event->engine != seq->engine)
engine            555 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 			dfs_pd->stats[seq->engine].sw_pattern++;
engine            650 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c 		pulse.engine = i;
engine             66 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h 	u8 engine;
engine             81 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h 	u8 engine;
engine             85 drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h 	u8 engine;
engine             13 drivers/video/fbdev/via/accel.c static int viafb_set_bpp(void __iomem *engine, u8 bpp)
engine             19 drivers/video/fbdev/via/accel.c 	gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
engine             34 drivers/video/fbdev/via/accel.c 	writel(gemode, engine + VIA_REG_GEMODE);
engine             39 drivers/video/fbdev/via/accel.c static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
engine             79 drivers/video/fbdev/via/accel.c 	ret = viafb_set_bpp(engine, dst_bpp);
engine             91 drivers/video/fbdev/via/accel.c 		writel(tmp, engine + 0x08);
engine            100 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x0C);
engine            108 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x10);
engine            111 drivers/video/fbdev/via/accel.c 		writel(fg_color, engine + 0x18);
engine            114 drivers/video/fbdev/via/accel.c 		writel(bg_color, engine + 0x1C);
engine            124 drivers/video/fbdev/via/accel.c 		writel(tmp, engine + 0x30);
engine            133 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x34);
engine            145 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x38);
engine            158 drivers/video/fbdev/via/accel.c 	writel(ge_cmd, engine);
engine            167 drivers/video/fbdev/via/accel.c 		writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
engine            172 drivers/video/fbdev/via/accel.c static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
engine            212 drivers/video/fbdev/via/accel.c 	ret = viafb_set_bpp(engine, dst_bpp);
engine            226 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x08);
engine            234 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x0C);
engine            242 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x10);
engine            250 drivers/video/fbdev/via/accel.c 	writel(tmp, engine + 0x14);
engine            260 drivers/video/fbdev/via/accel.c 		writel(tmp, engine + 0x18);
engine            269 drivers/video/fbdev/via/accel.c 		writel(tmp, engine + 0x1C);
engine            273 drivers/video/fbdev/via/accel.c 		writel(fg_color, engine + 0x58);
engine            275 drivers/video/fbdev/via/accel.c 		writel(fg_color, engine + 0x4C);
engine            276 drivers/video/fbdev/via/accel.c 		writel(bg_color, engine + 0x50);
engine            290 drivers/video/fbdev/via/accel.c 	writel(ge_cmd, engine);
engine            299 drivers/video/fbdev/via/accel.c 		writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
engine            307 drivers/video/fbdev/via/accel.c 	void __iomem *engine;
engine            310 drivers/video/fbdev/via/accel.c 	engine = viapar->shared->vdev->engine_mmio;
engine            311 drivers/video/fbdev/via/accel.c 	if (!engine) {
engine            369 drivers/video/fbdev/via/accel.c 	void __iomem *engine = viapar->shared->vdev->engine_mmio;
engine            384 drivers/video/fbdev/via/accel.c 		writel(0x0, engine + i);
engine            393 drivers/video/fbdev/via/accel.c 		writel(0x00100000, engine + VIA_REG_CR_TRANSET);
engine            394 drivers/video/fbdev/via/accel.c 		writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
engine            395 drivers/video/fbdev/via/accel.c 		writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
engine            399 drivers/video/fbdev/via/accel.c 		writel(0x00100000, engine + VIA_REG_TRANSET);
engine            400 drivers/video/fbdev/via/accel.c 		writel(0x00000000, engine + VIA_REG_TRANSPACE);
engine            401 drivers/video/fbdev/via/accel.c 		writel(0x00333004, engine + VIA_REG_TRANSPACE);
engine            402 drivers/video/fbdev/via/accel.c 		writel(0x60000000, engine + VIA_REG_TRANSPACE);
engine            403 drivers/video/fbdev/via/accel.c 		writel(0x61000000, engine + VIA_REG_TRANSPACE);
engine            404 drivers/video/fbdev/via/accel.c 		writel(0x62000000, engine + VIA_REG_TRANSPACE);
engine            405 drivers/video/fbdev/via/accel.c 		writel(0x63000000, engine + VIA_REG_TRANSPACE);
engine            406 drivers/video/fbdev/via/accel.c 		writel(0x64000000, engine + VIA_REG_TRANSPACE);
engine            407 drivers/video/fbdev/via/accel.c 		writel(0x7D000000, engine + VIA_REG_TRANSPACE);
engine            409 drivers/video/fbdev/via/accel.c 		writel(0xFE020000, engine + VIA_REG_TRANSET);
engine            410 drivers/video/fbdev/via/accel.c 		writel(0x00000000, engine + VIA_REG_TRANSPACE);
engine            435 drivers/video/fbdev/via/accel.c 		writel(0x00100000, engine + VIA_REG_CR_TRANSET);
engine            436 drivers/video/fbdev/via/accel.c 		writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
engine            437 drivers/video/fbdev/via/accel.c 		writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
engine            438 drivers/video/fbdev/via/accel.c 		writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
engine            439 drivers/video/fbdev/via/accel.c 		writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
engine            440 drivers/video/fbdev/via/accel.c 		writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
engine            441 drivers/video/fbdev/via/accel.c 		writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
engine            444 drivers/video/fbdev/via/accel.c 		writel(0x00FE0000, engine + VIA_REG_TRANSET);
engine            445 drivers/video/fbdev/via/accel.c 		writel(0x080003FE, engine + VIA_REG_TRANSPACE);
engine            446 drivers/video/fbdev/via/accel.c 		writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
engine            447 drivers/video/fbdev/via/accel.c 		writel(0x0B000260, engine + VIA_REG_TRANSPACE);
engine            448 drivers/video/fbdev/via/accel.c 		writel(0x0C000274, engine + VIA_REG_TRANSPACE);
engine            449 drivers/video/fbdev/via/accel.c 		writel(0x0D000264, engine + VIA_REG_TRANSPACE);
engine            450 drivers/video/fbdev/via/accel.c 		writel(0x0E000000, engine + VIA_REG_TRANSPACE);
engine            451 drivers/video/fbdev/via/accel.c 		writel(0x0F000020, engine + VIA_REG_TRANSPACE);
engine            452 drivers/video/fbdev/via/accel.c 		writel(0x1000027E, engine + VIA_REG_TRANSPACE);
engine            453 drivers/video/fbdev/via/accel.c 		writel(0x110002FE, engine + VIA_REG_TRANSPACE);
engine            454 drivers/video/fbdev/via/accel.c 		writel(0x200F0060, engine + VIA_REG_TRANSPACE);
engine            456 drivers/video/fbdev/via/accel.c 		writel(0x00000006, engine + VIA_REG_TRANSPACE);
engine            457 drivers/video/fbdev/via/accel.c 		writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
engine            458 drivers/video/fbdev/via/accel.c 		writel(0x44000000, engine + VIA_REG_TRANSPACE);
engine            459 drivers/video/fbdev/via/accel.c 		writel(0x45080C04, engine + VIA_REG_TRANSPACE);
engine            460 drivers/video/fbdev/via/accel.c 		writel(0x46800408, engine + VIA_REG_TRANSPACE);
engine            462 drivers/video/fbdev/via/accel.c 		writel(vq_high, engine + VIA_REG_TRANSPACE);
engine            463 drivers/video/fbdev/via/accel.c 		writel(vq_start_low, engine + VIA_REG_TRANSPACE);
engine            464 drivers/video/fbdev/via/accel.c 		writel(vq_end_low, engine + VIA_REG_TRANSPACE);
engine            465 drivers/video/fbdev/via/accel.c 		writel(vq_len, engine + VIA_REG_TRANSPACE);
engine            470 drivers/video/fbdev/via/accel.c 	writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
engine            471 drivers/video/fbdev/via/accel.c 	writel(0x0, engine + VIA_REG_CURSOR_POS);
engine            472 drivers/video/fbdev/via/accel.c 	writel(0x0, engine + VIA_REG_CURSOR_ORG);
engine            473 drivers/video/fbdev/via/accel.c 	writel(0x0, engine + VIA_REG_CURSOR_BG);
engine            474 drivers/video/fbdev/via/accel.c 	writel(0x0, engine + VIA_REG_CURSOR_FG);
engine            508 drivers/video/fbdev/via/accel.c 	void __iomem *engine = viapar->shared->vdev->engine_mmio;
engine            517 drivers/video/fbdev/via/accel.c 		while (!(readl(engine + VIA_REG_STATUS) &
engine            526 drivers/video/fbdev/via/accel.c 	while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
engine            761 drivers/video/fbdev/via/viafbdev.c 	void __iomem *engine = viapar->shared->vdev->engine_mmio;
engine            778 drivers/video/fbdev/via/viafbdev.c 		writel(temp, engine + VIA_REG_CURSOR_ORG);
engine            786 drivers/video/fbdev/via/viafbdev.c 		writel(temp, engine + VIA_REG_CURSOR_POS);
engine            800 drivers/video/fbdev/via/viafbdev.c 		temp = readl(engine + VIA_REG_CURSOR_MODE);
engine            806 drivers/video/fbdev/via/viafbdev.c 		writel(temp, engine + VIA_REG_CURSOR_MODE);
engine            835 drivers/video/fbdev/via/viafbdev.c 		writel(bg_color, engine + VIA_REG_CURSOR_BG);
engine            836 drivers/video/fbdev/via/viafbdev.c 		writel(fg_color, engine + VIA_REG_CURSOR_FG);
engine             52 drivers/video/fbdev/via/viafbdev.h 	int (*hw_bitblt)(void __iomem *engine, u8 op, u32 width, u32 height,
engine             57 include/crypto/engine.h 	int (*prepare_crypt_hardware)(struct crypto_engine *engine);
engine             58 include/crypto/engine.h 	int (*unprepare_crypt_hardware)(struct crypto_engine *engine);
engine             74 include/crypto/engine.h 	int (*prepare_request)(struct crypto_engine *engine,
engine             76 include/crypto/engine.h 	int (*unprepare_request)(struct crypto_engine *engine,
engine             78 include/crypto/engine.h 	int (*do_one_request)(struct crypto_engine *engine,
engine             86 include/crypto/engine.h int crypto_transfer_ablkcipher_request_to_engine(struct crypto_engine *engine,
engine             88 include/crypto/engine.h int crypto_transfer_aead_request_to_engine(struct crypto_engine *engine,
engine             90 include/crypto/engine.h int crypto_transfer_akcipher_request_to_engine(struct crypto_engine *engine,
engine             92 include/crypto/engine.h int crypto_transfer_hash_request_to_engine(struct crypto_engine *engine,
engine             94 include/crypto/engine.h int crypto_transfer_skcipher_request_to_engine(struct crypto_engine *engine,
engine             96 include/crypto/engine.h void crypto_finalize_ablkcipher_request(struct crypto_engine *engine,
engine             98 include/crypto/engine.h void crypto_finalize_aead_request(struct crypto_engine *engine,
engine            100 include/crypto/engine.h void crypto_finalize_akcipher_request(struct crypto_engine *engine,
engine            102 include/crypto/engine.h void crypto_finalize_hash_request(struct crypto_engine *engine,
engine            104 include/crypto/engine.h void crypto_finalize_skcipher_request(struct crypto_engine *engine,
engine            106 include/crypto/engine.h int crypto_engine_start(struct crypto_engine *engine);
engine            107 include/crypto/engine.h int crypto_engine_stop(struct crypto_engine *engine);
engine            109 include/crypto/engine.h int crypto_engine_exit(struct crypto_engine *engine);
engine            647 include/linux/ccp.h 	enum ccp_engine engine;
engine           1598 include/uapi/drm/i915_drm.h 	struct i915_engine_class_instance engine;
engine           2092 include/uapi/drm/i915_drm.h 	struct i915_engine_class_instance engine;
engine            253 include/uapi/drm/via_drm.h 	unsigned engine;
engine           1598 tools/include/uapi/drm/i915_drm.h 	struct i915_engine_class_instance engine;
engine           2092 tools/include/uapi/drm/i915_drm.h 	struct i915_engine_class_instance engine;