end_reg          1780 drivers/gpu/drm/radeon/evergreen_cs.c 	unsigned start_reg, end_reg, reg;
end_reg          2302 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2305 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
end_reg          2309 drivers/gpu/drm/radeon/evergreen_cs.c 		for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
end_reg          2319 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2322 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
end_reg          2326 drivers/gpu/drm/radeon/evergreen_cs.c 		for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
end_reg          2340 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2343 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_RESOURCE_END)) {
end_reg          2443 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2446 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
end_reg          2453 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2456 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
end_reg          2463 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2466 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_CTL_CONST_END)) {
end_reg          2477 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2480 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_SAMPLER_END)) {
end_reg          3353 drivers/gpu/drm/radeon/evergreen_cs.c 	u32 start_reg, end_reg, reg, i;
end_reg          3423 drivers/gpu/drm/radeon/evergreen_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          3426 drivers/gpu/drm/radeon/evergreen_cs.c 		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
end_reg          1634 drivers/gpu/drm/radeon/r600_cs.c 	unsigned start_reg, end_reg, reg;
end_reg          1910 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          1913 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
end_reg          1926 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          1929 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
end_reg          1946 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          1949 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_RESOURCE_END)) {
end_reg          2026 drivers/gpu/drm/radeon/r600_cs.c 			end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2029 drivers/gpu/drm/radeon/r600_cs.c 			    (end_reg >= PACKET3_SET_ALU_CONST_END)) {
end_reg          2037 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2040 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
end_reg          2047 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2050 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
end_reg          2057 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2060 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_CTL_CONST_END)) {
end_reg          2071 drivers/gpu/drm/radeon/r600_cs.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          2074 drivers/gpu/drm/radeon/r600_cs.c 		    (end_reg >= PACKET3_SET_SAMPLER_END)) {
end_reg          4536 drivers/gpu/drm/radeon/si.c 	u32 start_reg, end_reg, reg, i;
end_reg          4623 drivers/gpu/drm/radeon/si.c 		end_reg = 4 * pkt->count + start_reg - 4;
end_reg          4626 drivers/gpu/drm/radeon/si.c 		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
end_reg           714 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 	u32 end_reg = 0;
end_reg           742 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
end_reg           746 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			end_reg = PXP2_REG_RQ_QM_LAST_ILT;
end_reg           750 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
end_reg           754 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 			end_reg = PXP2_REG_RQ_TM_LAST_ILT;
end_reg           758 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h 		REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
end_reg           648 drivers/net/wireless/intel/iwlwifi/fw/file.h 	__le32 end_reg;
end_reg           968 drivers/net/wireless/intel/iwlwifi/pcie/trans.c 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
end_reg           973 drivers/net/wireless/intel/iwlwifi/pcie/trans.c 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
end_reg          3201 drivers/net/wireless/intel/iwlwifi/pcie/trans.c 			end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);