FBC_CNTL          149 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          150 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
FBC_CNTL          151 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
FBC_CNTL          157 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 			FBC_CNTL,
FBC_CNTL          202 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          207 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 			FBC_CNTL, FBC_SRC_SEL);
FBC_CNTL          218 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          234 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          251 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 			set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          286 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
FBC_CNTL          326 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          327 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
FBC_CNTL          328 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
FBC_CNTL          334 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 			FBC_CNTL,
FBC_CNTL          395 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          399 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 			FBC_CNTL, FBC_SRC_SEL);
FBC_CNTL          408 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          410 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          426 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
FBC_CNTL          460 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c 		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {