enable_state 443 block/blk-wbt.c RQWB(rqos)->enable_state = WBT_STATE_ON_MANUAL; enable_state 711 block/blk-wbt.c if (rwb->enable_state == WBT_STATE_ON_DEFAULT) { enable_state 733 block/blk-wbt.c seq_printf(m, "%d\n", rwb->enable_state); enable_state 843 block/blk-wbt.c rwb->enable_state = WBT_STATE_ON_DEFAULT; enable_state 46 block/blk-wbt.h short enable_state; /* WBT_STATE_* */ enable_state 245 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys_enc->enable_state == DPU_ENC_DISABLED) { enable_state 1474 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) enable_state 1542 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->enable_state = DPU_ENC_ENABLED; enable_state 1569 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys || phys->enable_state == DPU_ENC_DISABLED) enable_state 1796 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) enable_state 230 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h enum dpu_enc_enable_state enable_state; enable_state 326 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) enable_state 235 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET; enable_state 502 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->enable_state == DPU_ENC_ENABLED) { enable_state 508 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_ENABLED; enable_state 557 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state); enable_state 559 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->enable_state == DPU_ENC_DISABLED) { enable_state 566 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_DISABLED; enable_state 791 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_DISABLED; enable_state 468 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->enable_state == DPU_ENC_DISABLED) enable_state 469 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_ENABLING; enable_state 589 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->enable_state == DPU_ENC_DISABLED) { enable_state 618 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_DISABLED; enable_state 630 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->enable_state == DPU_ENC_ENABLING) { enable_state 636 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_ENABLED; enable_state 753 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_DISABLED; enable_state 535 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h uint32_t enable_state; enable_state 126 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); enable_state 191 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c dev_priv->enable_state); enable_state 199 drivers/leds/leds-lm3692x.c int enable_state; enable_state 278 drivers/leds/leds-lm3692x.c enable_state = LM3692X_LED1_EN | LM3692X_LED2_EN | enable_state 281 drivers/leds/leds-lm3692x.c enable_state = LM3692X_LED1_EN | LM3692X_LED2_EN; enable_state 285 drivers/leds/leds-lm3692x.c enable_state = LM3692X_LED1_EN; enable_state 288 drivers/leds/leds-lm3692x.c enable_state = LM3692X_LED2_EN; enable_state 293 drivers/leds/leds-lm3692x.c enable_state = LM36923_LED3_EN; enable_state 304 drivers/leds/leds-lm3692x.c enable_state | LM3692X_DEVICE_EN); enable_state 36 drivers/regulator/qcom_rpm-regulator.c struct request_member enable_state; /* NCP and switch */ enable_state 91 drivers/regulator/qcom_rpm-regulator.c .enable_state = { 0, 0x00000001, 0 }, enable_state 101 drivers/regulator/qcom_rpm-regulator.c .enable_state = { 0, 0x00001000, 12 }, enable_state 133 drivers/regulator/qcom_rpm-regulator.c .enable_state = { 0, 0x00000001, 0 }, enable_state 143 drivers/regulator/qcom_rpm-regulator.c .enable_state = { 0, 0x00800000, 23 }, enable_state 309 drivers/regulator/qcom_rpm-regulator.c const struct request_member *req = &parts->enable_state; enable_state 366 drivers/regulator/qcom_rpm-regulator.c const struct request_member *req = &parts->enable_state; enable_state 120 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h u8 enable_state; enable_state 131 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h u8 enable_state; enable_state 192 drivers/staging/fsl-dpaa2/ethsw/dpsw.c dpsw_set_field(cmd_params->enable_state, ENABLE, en);