en_off            174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	u32 en_off;
en_off            873 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
en_off            916 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
en_off            975 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].en_off, 0x00000000);
en_off            999 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);