emu_ge_int         42 drivers/crypto/cavium/nitrox/nitrox_hal.c 	union emu_ge_int_ena_w1s emu_ge_int;
emu_ge_int         50 drivers/crypto/cavium/nitrox/nitrox_hal.c 	emu_ge_int.value = 0;
emu_ge_int         51 drivers/crypto/cavium/nitrox/nitrox_hal.c 	emu_ge_int.s.se_ge = 0xffff;
emu_ge_int         52 drivers/crypto/cavium/nitrox/nitrox_hal.c 	emu_ge_int.s.ae_ge = 0xfffff;
emu_ge_int         60 drivers/crypto/cavium/nitrox/nitrox_hal.c 		nitrox_write_csr(ndev, offset, emu_ge_int.value);