eld_reg_to_type  1324 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type  1361 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type  1370 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type  1390 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
eld_reg_to_type  1350 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type  1387 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type  1396 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type  1416 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
eld_reg_to_type  1232 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type  1265 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type  1274 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type  1294 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
eld_reg_to_type  1275 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type  1314 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type  1323 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type  1344 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
eld_reg_to_type    71 drivers/gpu/drm/radeon/dce3_1_afmt.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type    86 drivers/gpu/drm/radeon/dce3_1_afmt.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type    95 drivers/gpu/drm/radeon/dce3_1_afmt.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type   112 drivers/gpu/drm/radeon/dce3_1_afmt.c 		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
eld_reg_to_type   209 drivers/gpu/drm/radeon/dce6_afmt.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type   227 drivers/gpu/drm/radeon/dce6_afmt.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type   236 drivers/gpu/drm/radeon/dce6_afmt.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type   253 drivers/gpu/drm/radeon/dce6_afmt.c 		WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
eld_reg_to_type   160 drivers/gpu/drm/radeon/evergreen_hdmi.c 	static const u16 eld_reg_to_type[][2] = {
eld_reg_to_type   175 drivers/gpu/drm/radeon/evergreen_hdmi.c 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
eld_reg_to_type   184 drivers/gpu/drm/radeon/evergreen_hdmi.c 			if (sad->format == eld_reg_to_type[i][1]) {
eld_reg_to_type   201 drivers/gpu/drm/radeon/evergreen_hdmi.c 		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);