eg_pi 2389 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 2447 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, eg_pi 2456 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, eg_pi 3150 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 3153 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->current_rps = *rps; eg_pi 3155 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->current_rps.ps_priv = &ni_pi->current_ps; eg_pi 3156 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.current_ps = &eg_pi->current_rps; eg_pi 3163 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 3166 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->requested_rps = *rps; eg_pi 3168 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; eg_pi 3169 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.requested_ps = &eg_pi->requested_rps; eg_pi 3318 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 3326 drivers/gpu/drm/amd/amdgpu/si_dpm.c new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, eg_pi 3332 drivers/gpu/drm/amd/amdgpu/si_dpm.c new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, eg_pi 4131 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 4140 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 4423 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 4429 drivers/gpu/drm/amd/amdgpu/si_dpm.c VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); eg_pi 4433 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) eg_pi 4436 drivers/gpu/drm/amd/amdgpu/si_dpm.c &eg_pi->vddc_voltage_table); eg_pi 4440 drivers/gpu/drm/amd/amdgpu/si_dpm.c &eg_pi->vddc_voltage_table); eg_pi 4447 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddci_control) { eg_pi 4449 drivers/gpu/drm/amd/amdgpu/si_dpm.c VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); eg_pi 4453 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) eg_pi 4456 drivers/gpu/drm/amd/amdgpu/si_dpm.c &eg_pi->vddci_voltage_table); eg_pi 4461 drivers/gpu/drm/amd/amdgpu/si_dpm.c &eg_pi->vddci_voltage_table); eg_pi 4514 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 4526 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddc_voltage_table.count) { eg_pi 4527 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); eg_pi 4529 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); eg_pi 4531 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { eg_pi 4532 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { eg_pi 4539 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddci_voltage_table.count) { eg_pi 4540 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); eg_pi 4543 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); eg_pi 4836 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 4884 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, eg_pi 4900 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddci_control) eg_pi 4902 drivers/gpu/drm/amd/amdgpu/si_dpm.c &eg_pi->vddci_voltage_table, eg_pi 4955 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 4976 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, eg_pi 4999 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, eg_pi 5028 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->acpi_vddci) eg_pi 5029 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, eg_pi 5030 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->acpi_vddci, eg_pi 5075 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 5096 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 5105 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 5444 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 5451 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->pcie_performance_request && eg_pi 5465 drivers/gpu/drm/amd/amdgpu/si_dpm.c !eg_pi->uvd_enabled && eg_pi 5478 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) eg_pi 5508 drivers/gpu/drm/amd/amdgpu/si_dpm.c &eg_pi->vddc_voltage_table, eg_pi 5523 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->vddci_control) { eg_pi 5524 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, eg_pi 5655 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 5669 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->uvd_enabled = true; eg_pi 5670 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->smu_uvd_hs) eg_pi 5673 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->uvd_enabled = false; eg_pi 5681 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 5706 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 6266 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 6268 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 6784 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 6802 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 6805 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->dynamic_ac_timing = false; eg_pi 6848 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 6941 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 6946 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); eg_pi 6980 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 6981 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *new_ps = &eg_pi->requested_rps; eg_pi 6982 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *old_ps = &eg_pi->current_rps; eg_pi 6995 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->pcie_performance_request) eg_pi 7028 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 7053 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (eg_pi->pcie_performance_request) eg_pi 7083 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 7084 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *new_ps = &eg_pi->requested_rps; eg_pi 7137 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 7167 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->acpi_vddci = pl->vddci; eg_pi 7308 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi; eg_pi 7319 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi = &ni_pi->eg; eg_pi 7320 drivers/gpu/drm/amd/amdgpu/si_dpm.c pi = &eg_pi->rv7xx; eg_pi 7334 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->acpi_vddci = 0; eg_pi 7380 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->smu_uvd_hs = false; eg_pi 7388 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->mclk_edc_wr_enable_threshold = 40000; eg_pi 7390 drivers/gpu/drm/amd/amdgpu/si_dpm.c ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; eg_pi 7408 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->vddci_control = eg_pi 7411 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (!eg_pi->vddci_control) eg_pi 7428 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->sclk_deep_sleep = true; eg_pi 7436 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->dynamic_ac_timing = true; eg_pi 7438 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->light_sleep = true; eg_pi 7440 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->pcie_performance_request = eg_pi 7443 drivers/gpu/drm/amd/amdgpu/si_dpm.c eg_pi->pcie_performance_request = false; eg_pi 7486 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 7487 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = &eg_pi->current_rps; eg_pi 7873 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 7874 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); eg_pi 7885 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 7886 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); eg_pi 7987 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); eg_pi 7988 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ps *rps = &eg_pi->current_rps; eg_pi 1313 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1321 drivers/gpu/drm/radeon/btc_dpm.c new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, eg_pi 1327 drivers/gpu/drm/radeon/btc_dpm.c new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, eg_pi 1389 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1391 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) { eg_pi 1402 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1403 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; eg_pi 1632 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1669 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->sclk_deep_sleep) eg_pi 1677 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) { eg_pi 1680 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ulv.supported = false; eg_pi 1696 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1702 drivers/gpu/drm/radeon/btc_dpm.c if ((idx == 1) && !eg_pi->smu_uvd_hs) { eg_pi 1708 drivers/gpu/drm/radeon/btc_dpm.c pi->rlp = eg_pi->ats[idx].rlp; eg_pi 1709 drivers/gpu/drm/radeon/btc_dpm.c pi->rmp = eg_pi->ats[idx].rmp; eg_pi 1710 drivers/gpu/drm/radeon/btc_dpm.c pi->lhp = eg_pi->ats[idx].lhp; eg_pi 1711 drivers/gpu/drm/radeon/btc_dpm.c pi->lmp = eg_pi->ats[idx].lmp; eg_pi 1719 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1724 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->uvd_enabled = true; eg_pi 1728 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->uvd_enabled = false; eg_pi 1756 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1758 drivers/gpu/drm/radeon/btc_dpm.c &eg_pi->bootup_arb_registers; eg_pi 1786 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1788 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) eg_pi 1789 drivers/gpu/drm/radeon/btc_dpm.c btc_set_arb0_registers(rdev, &eg_pi->bootup_arb_registers); eg_pi 1796 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1797 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; eg_pi 1814 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1815 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; eg_pi 1842 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1844 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) { eg_pi 2022 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2023 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_mc_reg_table *eg_table = &eg_pi->mc_reg_table; eg_pi 2263 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2265 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->current_rps = *rps; eg_pi 2266 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->current_ps = *new_ps; eg_pi 2267 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->current_rps.ps_priv = &eg_pi->current_ps; eg_pi 2274 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2276 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->requested_rps = *rps; eg_pi 2277 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->requested_ps = *new_ps; eg_pi 2278 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->requested_rps.ps_priv = &eg_pi->requested_ps; eg_pi 2293 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2299 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); eg_pi 2306 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2307 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *new_ps = &eg_pi->requested_rps; eg_pi 2308 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *old_ps = &eg_pi->current_rps; eg_pi 2318 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->pcie_performance_request) eg_pi 2328 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->smu_uvd_hs) eg_pi 2335 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 2357 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->pcie_performance_request) eg_pi 2371 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2372 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *new_ps = &eg_pi->requested_rps; eg_pi 2380 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2393 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ls_clock_gating) eg_pi 2413 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 2416 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->dynamic_ac_timing = false; eg_pi 2454 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 2471 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->memory_transition) eg_pi 2482 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ls_clock_gating) eg_pi 2497 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2522 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ls_clock_gating) eg_pi 2535 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2546 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->pcie_performance_request) eg_pi 2556 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi; eg_pi 2560 drivers/gpu/drm/radeon/btc_dpm.c eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL); eg_pi 2561 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi == NULL) eg_pi 2563 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.priv = eg_pi; eg_pi 2564 drivers/gpu/drm/radeon/btc_dpm.c pi = &eg_pi->rv7xx; eg_pi 2568 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ulv.supported = false; eg_pi 2570 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->acpi_vddci = 0; eg_pi 2617 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->mclk_edc_wr_enable_threshold = 40000; eg_pi 2624 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[0].rlp = RV770_RLP_DFLT; eg_pi 2625 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[0].rmp = RV770_RMP_DFLT; eg_pi 2626 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[0].lhp = RV770_LHP_DFLT; eg_pi 2627 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[0].lmp = RV770_LMP_DFLT; eg_pi 2629 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; eg_pi 2630 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; eg_pi 2631 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT; eg_pi 2632 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT; eg_pi 2634 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->smu_uvd_hs = true; eg_pi 2642 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->vddci_control = eg_pi 2657 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ls_clock_gating = false; eg_pi 2658 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->sclk_deep_sleep = false; eg_pi 2676 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->dynamic_ac_timing = true; eg_pi 2677 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->abm = true; eg_pi 2678 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->mcls = true; eg_pi 2679 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->light_sleep = true; eg_pi 2680 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->memory_transition = true; eg_pi 2682 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->pcie_performance_request = eg_pi 2685 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->pcie_performance_request = false; eg_pi 2689 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->dll_default_on = true; eg_pi 2691 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->dll_default_on = false; eg_pi 2693 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->sclk_deep_sleep = false; eg_pi 2739 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2740 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 2764 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2765 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 2787 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2788 drivers/gpu/drm/radeon/btc_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 2810 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2811 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *requested_state = rv770_get_ps(&eg_pi->requested_rps); eg_pi 2821 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2822 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_ps *requested_state = rv770_get_ps(&eg_pi->requested_rps); eg_pi 123 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 126 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->light_sleep) { eg_pi 151 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->light_sleep) { eg_pi 176 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 198 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->mcls) { eg_pi 305 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 317 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->pcie_performance_request_registered = true; eg_pi 320 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->pcie_performance_request_registered) { eg_pi 321 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->pcie_performance_request_registered = false; eg_pi 657 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 660 drivers/gpu/drm/radeon/cypress_dpm.c voltage->index = eg_pi->mvdd_high_index; eg_pi 666 drivers/gpu/drm/radeon/cypress_dpm.c voltage->index = eg_pi->mvdd_low_index; eg_pi 669 drivers/gpu/drm/radeon/cypress_dpm.c voltage->index = eg_pi->mvdd_high_index; eg_pi 682 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 699 drivers/gpu/drm/radeon/cypress_dpm.c !eg_pi->uvd_enabled) { eg_pi 701 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->sclk_deep_sleep) eg_pi 711 drivers/gpu/drm/radeon/cypress_dpm.c if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) eg_pi 723 drivers/gpu/drm/radeon/cypress_dpm.c dll_state_on = eg_pi->dll_default_on; eg_pi 743 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table, eg_pi 749 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddci_control) { eg_pi 751 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddci_voltage_table, eg_pi 768 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 799 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 832 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 835 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) { eg_pi 837 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) eg_pi 841 drivers/gpu/drm/radeon/cypress_dpm.c if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0)) eg_pi 844 drivers/gpu/drm/radeon/cypress_dpm.c cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i], eg_pi 846 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.last, eg_pi 847 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag); eg_pi 889 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 895 drivers/gpu/drm/radeon/cypress_dpm.c address = eg_pi->mc_reg_table_start + eg_pi 951 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 954 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) { eg_pi 955 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->mc_reg_table.valid_flag & (1 << j)) { eg_pi 957 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); eg_pi 959 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); eg_pi 969 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 972 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; eg_pi 973 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; eg_pi 976 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; eg_pi 977 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; eg_pi 980 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; eg_pi 981 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; eg_pi 984 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; eg_pi 985 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; eg_pi 988 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; eg_pi 989 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; eg_pi 992 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; eg_pi 993 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; eg_pi 996 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; eg_pi 997 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; eg_pi 1000 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; eg_pi 1001 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; eg_pi 1004 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; eg_pi 1005 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; eg_pi 1008 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; eg_pi 1009 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; eg_pi 1012 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; eg_pi 1013 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; eg_pi 1016 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; eg_pi 1017 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; eg_pi 1020 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; eg_pi 1021 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; eg_pi 1024 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; eg_pi 1025 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; eg_pi 1028 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.last = (u8)i; eg_pi 1034 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1037 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.last; i++) eg_pi 1039 drivers/gpu/drm/radeon/cypress_dpm.c RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); eg_pi 1046 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1050 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max = eg_pi 1054 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->mc_reg_table.mc_reg_table_entry[i]); eg_pi 1057 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.num_entries = range_table->num_entries; eg_pi 1058 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag = 0; eg_pi 1060 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.last; i++) { eg_pi 1062 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] != eg_pi 1063 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) { eg_pi 1064 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag |= (1 << i); eg_pi 1168 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1172 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.last; i++) { eg_pi 1173 drivers/gpu/drm/radeon/cypress_dpm.c value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); eg_pi 1174 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); eg_pi 1227 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1229 drivers/gpu/drm/radeon/cypress_dpm.c voltage->index = eg_pi->mvdd_high_index; eg_pi 1241 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1284 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table, eg_pi 1288 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddci_control) eg_pi 1290 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddci_voltage_table, eg_pi 1335 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1361 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table, eg_pi 1377 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table, eg_pi 1383 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->acpi_vddci) { eg_pi 1384 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddci_control) { eg_pi 1386 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddci_voltage_table, eg_pi 1387 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->acpi_vddci, eg_pi 1459 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 1486 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1490 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table); eg_pi 1494 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS) eg_pi 1496 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table); eg_pi 1498 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddci_control) { eg_pi 1500 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddci_voltage_table); eg_pi 1504 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS) eg_pi 1506 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddci_voltage_table); eg_pi 1528 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1531 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddc_voltage_table.count) { eg_pi 1533 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddc_voltage_table, eg_pi 1538 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); eg_pi 1540 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { eg_pi 1542 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->vddc_voltage_table.entries[i].value) { eg_pi 1549 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->vddci_voltage_table.count) { eg_pi 1551 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->vddci_voltage_table, eg_pi 1556 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); eg_pi 1574 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1580 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mvdd_high_index = 0; eg_pi 1581 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mvdd_low_index = 1; eg_pi 1587 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mvdd_high_index = 1; eg_pi 1589 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mvdd_high_index = 0; eg_pi 1591 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mvdd_low_index = eg_pi 1592 drivers/gpu/drm/radeon/cypress_dpm.c (eg_pi->mvdd_high_index == 0) ? 1 : 0; eg_pi 1668 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1681 drivers/gpu/drm/radeon/cypress_dpm.c cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0], eg_pi 1682 drivers/gpu/drm/radeon/cypress_dpm.c &mc_reg_table.data[1], eg_pi->mc_reg_table.last, eg_pi 1683 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag); eg_pi 1687 drivers/gpu/drm/radeon/cypress_dpm.c return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start, eg_pi 1695 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1724 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table_start = (u16)tmp; eg_pi 1786 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1793 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->pcie_performance_request) eg_pi 1794 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->pcie_performance_request_registered = false; eg_pi 1796 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->pcie_performance_request) eg_pi 1807 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1834 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 1839 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->dynamic_ac_timing = false; eg_pi 1880 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 1899 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->memory_transition) eg_pi 1918 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1949 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 1957 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1967 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->pcie_performance_request) eg_pi 1981 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 2003 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->pcie_performance_request) eg_pi 2025 drivers/gpu/drm/radeon/cypress_dpm.c struct evergreen_power_info *eg_pi; eg_pi 2029 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL); eg_pi 2030 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi == NULL) eg_pi 2032 drivers/gpu/drm/radeon/cypress_dpm.c rdev->pm.dpm.priv = eg_pi; eg_pi 2033 drivers/gpu/drm/radeon/cypress_dpm.c pi = &eg_pi->rv7xx; eg_pi 2037 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->ulv.supported = false; eg_pi 2039 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->acpi_vddci = 0; eg_pi 2065 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mclk_edc_wr_enable_threshold = 40000; eg_pi 2078 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->vddci_control = eg_pi 2097 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->ls_clock_gating = false; eg_pi 2098 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->sclk_deep_sleep = false; eg_pi 2116 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->dynamic_ac_timing = true; eg_pi 2117 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->abm = true; eg_pi 2118 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mcls = true; eg_pi 2119 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->light_sleep = true; eg_pi 2120 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->memory_transition = true; eg_pi 2122 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->pcie_performance_request = eg_pi 2125 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->pcie_performance_request = false; eg_pi 2131 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->dll_default_on = true; eg_pi 2133 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->dll_default_on = false; eg_pi 2135 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->sclk_deep_sleep = false; eg_pi 1102 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1135 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->mc_reg_table_start = (u16)tmp; eg_pi 1275 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1278 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->vddc_voltage_table.count) { eg_pi 1279 drivers/gpu/drm/radeon/ni_dpm.c ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); eg_pi 1282 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); eg_pi 1284 drivers/gpu/drm/radeon/ni_dpm.c for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { eg_pi 1285 drivers/gpu/drm/radeon/ni_dpm.c if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { eg_pi 1292 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->vddci_voltage_table.count) { eg_pi 1293 drivers/gpu/drm/radeon/ni_dpm.c ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); eg_pi 1297 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); eg_pi 1327 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1330 drivers/gpu/drm/radeon/ni_dpm.c voltage->index = eg_pi->mvdd_high_index; eg_pi 1336 drivers/gpu/drm/radeon/ni_dpm.c voltage->index = eg_pi->mvdd_low_index; eg_pi 1339 drivers/gpu/drm/radeon/ni_dpm.c voltage->index = eg_pi->mvdd_high_index; eg_pi 1387 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1402 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 1412 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 1675 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1677 drivers/gpu/drm/radeon/ni_dpm.c voltage->index = eg_pi->mvdd_high_index; eg_pi 1687 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1730 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 1745 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->vddci_control) eg_pi 1747 drivers/gpu/drm/radeon/ni_dpm.c &eg_pi->vddci_voltage_table, eg_pi 1796 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 1817 drivers/gpu/drm/radeon/ni_dpm.c &eg_pi->vddc_voltage_table, eg_pi 1840 drivers/gpu/drm/radeon/ni_dpm.c &eg_pi->vddc_voltage_table, eg_pi 1857 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->acpi_vddci) { eg_pi 1858 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->vddci_control) eg_pi 1860 drivers/gpu/drm/radeon/ni_dpm.c &eg_pi->vddci_voltage_table, eg_pi 1861 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->acpi_vddci, eg_pi 1923 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 2314 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2331 drivers/gpu/drm/radeon/ni_dpm.c !eg_pi->uvd_enabled && eg_pi 2339 drivers/gpu/drm/radeon/ni_dpm.c if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) eg_pi 2366 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 2378 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->vddci_control) { eg_pi 2379 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, eg_pi 2395 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2414 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->uvd_enabled) eg_pi 2416 drivers/gpu/drm/radeon/ni_dpm.c 1000 * (i * (eg_pi->smu_uvd_hs ? 2 : 8) + 2), eg_pi 2455 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2510 drivers/gpu/drm/radeon/ni_dpm.c if ((max_ps_percent == 0) || (prev_sclk == max_sclk) || eg_pi->uvd_enabled) eg_pi 2628 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2659 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 2996 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3017 drivers/gpu/drm/radeon/ni_dpm.c return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start, eg_pi 3027 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3037 drivers/gpu/drm/radeon/ni_dpm.c address = eg_pi->mc_reg_table_start + eg_pi 3050 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3057 drivers/gpu/drm/radeon/ni_dpm.c table_size = eg_pi->vddc_voltage_table.count; eg_pi 3073 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->vddc_voltage_table.entries[j].value, eg_pi 3096 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3108 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->vddc_voltage_table.count != table_size) eg_pi 3109 drivers/gpu/drm/radeon/ni_dpm.c table_size = (eg_pi->vddc_voltage_table.count < leakage_table->count) ? eg_pi 3110 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->vddc_voltage_table.count : leakage_table->count; eg_pi 3422 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3426 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->pcie_performance_request_registered == false) eg_pi 3428 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->pcie_performance_request_registered = true; eg_pi 3431 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->pcie_performance_request_registered) { eg_pi 3432 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->pcie_performance_request_registered = false; eg_pi 3546 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3555 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->pcie_performance_request) eg_pi 3565 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3568 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->current_rps = *rps; eg_pi 3570 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->current_rps.ps_priv = &ni_pi->current_ps; eg_pi 3577 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3580 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->requested_rps = *rps; eg_pi 3582 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; eg_pi 3588 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3598 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->ls_clock_gating) eg_pi 3608 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 3611 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->dynamic_ac_timing = false; eg_pi 3656 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 3686 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->memory_transition) eg_pi 3693 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->ls_clock_gating) eg_pi 3706 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3731 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->ls_clock_gating) eg_pi 3767 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3773 drivers/gpu/drm/radeon/ni_dpm.c ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); eg_pi 3780 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3781 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *new_ps = &eg_pi->requested_rps; eg_pi 3782 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *old_ps = &eg_pi->current_rps; eg_pi 3806 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->smu_uvd_hs) eg_pi 3813 drivers/gpu/drm/radeon/ni_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 3859 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3860 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *new_ps = &eg_pi->requested_rps; eg_pi 3925 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3948 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->acpi_vddci = pl->vddci; eg_pi 3956 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ulv.supported = true; eg_pi 3957 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ulv.pl = pl; eg_pi 4049 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi; eg_pi 4058 drivers/gpu/drm/radeon/ni_dpm.c eg_pi = &ni_pi->eg; eg_pi 4059 drivers/gpu/drm/radeon/ni_dpm.c pi = &eg_pi->rv7xx; eg_pi 4063 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ulv.supported = false; eg_pi 4065 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->acpi_vddci = 0; eg_pi 4117 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[0].rlp = RV770_RLP_DFLT; eg_pi 4118 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[0].rmp = RV770_RMP_DFLT; eg_pi 4119 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[0].lhp = RV770_LHP_DFLT; eg_pi 4120 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[0].lmp = RV770_LMP_DFLT; eg_pi 4122 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; eg_pi 4123 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; eg_pi 4124 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT; eg_pi 4125 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT; eg_pi 4127 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->smu_uvd_hs = true; eg_pi 4132 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->mclk_edc_wr_enable_threshold = 55000; eg_pi 4136 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->mclk_edc_wr_enable_threshold = 40000; eg_pi 4138 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; eg_pi 4146 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->vddci_control = eg_pi 4161 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ls_clock_gating = false; eg_pi 4162 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->sclk_deep_sleep = false; eg_pi 4177 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->dynamic_ac_timing = true; eg_pi 4178 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->abm = true; eg_pi 4179 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->mcls = true; eg_pi 4180 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->light_sleep = true; eg_pi 4181 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->memory_transition = true; eg_pi 4183 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->pcie_performance_request = eg_pi 4186 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->pcie_performance_request = false; eg_pi 4189 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->dll_default_on = false; eg_pi 4191 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->sclk_deep_sleep = false; eg_pi 4307 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4308 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 4327 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4328 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 4345 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4346 drivers/gpu/drm/radeon/ni_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 4363 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4364 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps); eg_pi 4374 drivers/gpu/drm/radeon/ni_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4375 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps); eg_pi 2178 drivers/gpu/drm/radeon/rv770_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2227 drivers/gpu/drm/radeon/rv770_dpm.c eg_pi->acpi_vddci = pl->vddci; eg_pi 2236 drivers/gpu/drm/radeon/rv770_dpm.c eg_pi->ulv.supported = true; eg_pi 2237 drivers/gpu/drm/radeon/rv770_dpm.c eg_pi->ulv.pl = pl; eg_pi 2292 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 2351 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 2360 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 3672 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3675 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 3961 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 3967 drivers/gpu/drm/radeon/si_dpm.c VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); eg_pi 3971 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) eg_pi 3974 drivers/gpu/drm/radeon/si_dpm.c &eg_pi->vddc_voltage_table); eg_pi 3978 drivers/gpu/drm/radeon/si_dpm.c &eg_pi->vddc_voltage_table); eg_pi 3985 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddci_control) { eg_pi 3987 drivers/gpu/drm/radeon/si_dpm.c VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); eg_pi 3991 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) eg_pi 3994 drivers/gpu/drm/radeon/si_dpm.c &eg_pi->vddci_voltage_table); eg_pi 3999 drivers/gpu/drm/radeon/si_dpm.c &eg_pi->vddci_voltage_table); eg_pi 4052 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4064 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddc_voltage_table.count) { eg_pi 4065 drivers/gpu/drm/radeon/si_dpm.c si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); eg_pi 4067 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); eg_pi 4069 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { eg_pi 4070 drivers/gpu/drm/radeon/si_dpm.c if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { eg_pi 4077 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddci_voltage_table.count) { eg_pi 4078 drivers/gpu/drm/radeon/si_dpm.c si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); eg_pi 4081 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); eg_pi 4372 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4420 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 4436 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddci_control) eg_pi 4438 drivers/gpu/drm/radeon/si_dpm.c &eg_pi->vddci_voltage_table, eg_pi 4493 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4514 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 4537 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, eg_pi 4565 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->acpi_vddci) eg_pi 4566 drivers/gpu/drm/radeon/si_dpm.c si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, eg_pi 4567 drivers/gpu/drm/radeon/si_dpm.c eg_pi->acpi_vddci, eg_pi 4612 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 4633 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4642 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 4982 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 4989 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->pcie_performance_request && eg_pi 5003 drivers/gpu/drm/radeon/si_dpm.c !eg_pi->uvd_enabled && eg_pi 5016 drivers/gpu/drm/radeon/si_dpm.c if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) eg_pi 5046 drivers/gpu/drm/radeon/si_dpm.c &eg_pi->vddc_voltage_table, eg_pi 5061 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->vddci_control) { eg_pi 5062 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, eg_pi 5193 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 5207 drivers/gpu/drm/radeon/si_dpm.c eg_pi->uvd_enabled = true; eg_pi 5208 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->smu_uvd_hs) eg_pi 5211 drivers/gpu/drm/radeon/si_dpm.c eg_pi->uvd_enabled = false; eg_pi 5219 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 5244 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->dynamic_ac_timing) eg_pi 5814 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 5816 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->sclk_deep_sleep) { eg_pi 6352 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 6370 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 6373 drivers/gpu/drm/radeon/si_dpm.c eg_pi->dynamic_ac_timing = false; eg_pi 6416 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 6522 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 6528 drivers/gpu/drm/radeon/si_dpm.c si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); eg_pi 6561 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 6562 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *new_ps = &eg_pi->requested_rps; eg_pi 6563 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *old_ps = &eg_pi->current_rps; eg_pi 6576 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->pcie_performance_request) eg_pi 6609 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->dynamic_ac_timing) { eg_pi 6635 drivers/gpu/drm/radeon/si_dpm.c if (eg_pi->pcie_performance_request) eg_pi 6664 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 6665 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *new_ps = &eg_pi->requested_rps; eg_pi 6737 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 6767 drivers/gpu/drm/radeon/si_dpm.c eg_pi->acpi_vddci = pl->vddci; eg_pi 6903 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi; eg_pi 6916 drivers/gpu/drm/radeon/si_dpm.c eg_pi = &ni_pi->eg; eg_pi 6917 drivers/gpu/drm/radeon/si_dpm.c pi = &eg_pi->rv7xx; eg_pi 6944 drivers/gpu/drm/radeon/si_dpm.c eg_pi->acpi_vddci = 0; eg_pi 6990 drivers/gpu/drm/radeon/si_dpm.c eg_pi->smu_uvd_hs = false; eg_pi 6998 drivers/gpu/drm/radeon/si_dpm.c eg_pi->mclk_edc_wr_enable_threshold = 40000; eg_pi 7000 drivers/gpu/drm/radeon/si_dpm.c ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; eg_pi 7018 drivers/gpu/drm/radeon/si_dpm.c eg_pi->vddci_control = eg_pi 7021 drivers/gpu/drm/radeon/si_dpm.c if (!eg_pi->vddci_control) eg_pi 7038 drivers/gpu/drm/radeon/si_dpm.c eg_pi->sclk_deep_sleep = true; eg_pi 7046 drivers/gpu/drm/radeon/si_dpm.c eg_pi->dynamic_ac_timing = true; eg_pi 7048 drivers/gpu/drm/radeon/si_dpm.c eg_pi->light_sleep = true; eg_pi 7050 drivers/gpu/drm/radeon/si_dpm.c eg_pi->pcie_performance_request = eg_pi 7053 drivers/gpu/drm/radeon/si_dpm.c eg_pi->pcie_performance_request = false; eg_pi 7095 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 7096 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 7115 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 7116 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = &eg_pi->current_rps; eg_pi 7133 drivers/gpu/drm/radeon/si_dpm.c struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); eg_pi 7134 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ps *rps = &eg_pi->current_rps;