ecc_ctrl          849 drivers/edac/amd64_edac.c 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
ecc_ctrl         2716 drivers/edac/amd64_edac.c 				if (pvt->umc[i].ecc_ctrl & BIT(9)) {
ecc_ctrl         2719 drivers/edac/amd64_edac.c 				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
ecc_ctrl         2757 drivers/edac/amd64_edac.c 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
ecc_ctrl          333 drivers/edac/amd64_edac.h 	u32 ecc_ctrl;		/* DRAM ECC Control reg */
ecc_ctrl          437 drivers/edac/pnd2_edac.c static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS];
ecc_ctrl          493 drivers/edac/pnd2_edac.c 		if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) ||
ecc_ctrl         1101 drivers/edac/pnd2_edac.c 	if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) {