ebb4             12806 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
ebb4             1595 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	temp |= pll->state.hw_state.ebb4;
ebb4             1674 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
ebb4             1675 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
ebb4             1859 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
ebb4             1926 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->ebb4,
ebb4              195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;