ebb0             1663 drivers/gpu/drm/i915/display/intel_ddi.c 	clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
ebb0             1664 drivers/gpu/drm/i915/display/intel_ddi.c 	clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
ebb0             12805 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
ebb0             1538 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	temp |= pll->state.hw_state.ebb0;
ebb0             1671 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
ebb0             1672 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
ebb0             1840 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
ebb0             1925 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->ebb0,
ebb0              195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;