ebase              48 arch/mips/bmips/setup.c 	ebase = kbase;
ebase             808 arch/mips/cavium-octeon/setup.c 		uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
ebase             811 arch/mips/cavium-octeon/setup.c 		cvmx_l2c_lock_mem_region(ebase, 0x100);
ebase             815 arch/mips/cavium-octeon/setup.c 		cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
ebase             819 arch/mips/cavium-octeon/setup.c 		cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
ebase             244 arch/mips/cavium-octeon/smp.c 	write_c0_ebase((u32)ebase);
ebase             712 arch/mips/include/asm/kvm_host.h __BUILD_KVM_RW_HW(ebase,          l,  MIPS_CP0_PRID,         1)
ebase             735 arch/mips/include/asm/kvm_host.h __BUILD_KVM_SET_HW(ebase,         l,  MIPS_CP0_PRID,         1)
ebase              54 arch/mips/include/asm/mach-netlogic/multi-node.h 	unsigned long	ebase;		/* not used now */
ebase            2845 arch/mips/include/asm/mipsregs.h __BUILD_SET_GC0(ebase)
ebase              26 arch/mips/include/asm/setup.h extern unsigned long ebase;
ebase             977 arch/mips/kernel/cpu-probe.c 		u64 ebase;
ebase             981 arch/mips/kernel/cpu-probe.c 		ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
ebase             983 arch/mips/kernel/cpu-probe.c 		if (ebase & MIPS_EBASE_WG) {
ebase             997 arch/mips/kernel/cpu-probe.c 				write_c0_ebase_64(ebase | MIPS_EBASE_WG);
ebase             999 arch/mips/kernel/cpu-probe.c 				write_c0_ebase(ebase | MIPS_EBASE_WG);
ebase            1005 arch/mips/kernel/cpu-probe.c 				write_c0_ebase(ebase);
ebase             527 arch/mips/kernel/smp-bmips.c 	unsigned long new_ebase = ebase;
ebase             529 arch/mips/kernel/smp-bmips.c 	BUG_ON(ebase != CKSEG0);
ebase             570 arch/mips/kernel/smp-bmips.c 	ebase = new_ebase;
ebase            1925 arch/mips/kernel/traps.c unsigned long ebase;
ebase            1926 arch/mips/kernel/traps.c EXPORT_SYMBOL_GPL(ebase);
ebase            1954 arch/mips/kernel/traps.c 		u32 *buf = (u32 *)(ebase + 0x200);
ebase            1956 arch/mips/kernel/traps.c 		if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
ebase            1964 arch/mips/kernel/traps.c 		local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
ebase            1992 arch/mips/kernel/traps.c 	b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
ebase            2033 arch/mips/kernel/traps.c 		set_handler(((unsigned long)b - ebase), vec_start,
ebase            2159 arch/mips/kernel/traps.c 			write_c0_ebase_64(ebase | MIPS_EBASE_WG);
ebase            2161 arch/mips/kernel/traps.c 			write_c0_ebase(ebase | MIPS_EBASE_WG);
ebase            2164 arch/mips/kernel/traps.c 		write_c0_ebase(ebase);
ebase            2233 arch/mips/kernel/traps.c 	memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
ebase            2235 arch/mips/kernel/traps.c 	memcpy((void *)(ebase + offset), addr, size);
ebase            2237 arch/mips/kernel/traps.c 	local_flush_icache_range(ebase + offset, ebase + offset + size);
ebase            2251 arch/mips/kernel/traps.c 	unsigned long uncached_ebase = CKSEG1ADDR(ebase);
ebase            2279 arch/mips/kernel/traps.c 		ebase = CAC_BASE;
ebase            2280 arch/mips/kernel/traps.c 		ebase_pa = virt_to_phys((void *)ebase);
ebase            2307 arch/mips/kernel/traps.c 			ebase = CKSEG0ADDR(ebase_pa);
ebase            2309 arch/mips/kernel/traps.c 			ebase = (unsigned long)phys_to_virt(ebase_pa);
ebase            2443 arch/mips/kernel/traps.c 	local_flush_icache_range(ebase, ebase + vec_size);
ebase             674 arch/mips/kvm/entry.c 	UASM_i_LA_mostly(&p, K0, (long)&ebase);
ebase             675 arch/mips/kvm/entry.c 	UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0);
ebase             443 arch/mips/mm/tlbex.c 	memcpy((void *)ebase, tlb_handler, 0x80);
ebase             444 arch/mips/mm/tlbex.c 	local_flush_icache_range(ebase, ebase + 0x80);
ebase             445 arch/mips/mm/tlbex.c 	dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80));
ebase            1476 arch/mips/mm/tlbex.c 	memcpy((void *)ebase, final_handler, 0x100);
ebase            1477 arch/mips/mm/tlbex.c 	local_flush_icache_range(ebase, ebase + 0x100);
ebase            1478 arch/mips/mm/tlbex.c 	dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100));
ebase            1581 arch/mips/mm/tlbex.c 	memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
ebase            1582 arch/mips/mm/tlbex.c 	local_flush_icache_range(ebase + 0x80, ebase + 0x100);
ebase            1584 arch/mips/mm/tlbex.c 		     (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100));
ebase             114 arch/mips/netlogic/common/smp.c 	write_c0_ebase(nlm_current_node()->ebase);
ebase              61 arch/mips/netlogic/xlp/nlm_hal.c 	nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE;
ebase             171 arch/mips/netlogic/xlr/setup.c 	nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE;
ebase              88 arch/mips/paravirt/paravirt-smp.c 	write_c0_ebase((u32)ebase);
ebase             195 drivers/media/rc/winbond-cir.c 	unsigned long ebase;        /* Enhanced Func. Baseaddr	*/
ebase             265 drivers/media/rc/winbond-cir.c 	if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
ebase             279 drivers/media/rc/winbond-cir.c 	wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
ebase             312 drivers/media/rc/winbond-cir.c 	unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) |
ebase             313 drivers/media/rc/winbond-cir.c 			inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8;
ebase             327 drivers/media/rc/winbond-cir.c 	wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
ebase             329 drivers/media/rc/winbond-cir.c 	wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN,
ebase             513 drivers/media/rc/winbond-cir.c 	wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
ebase             517 drivers/media/rc/winbond-cir.c 		wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL,
ebase             618 drivers/media/rc/winbond-cir.c 		wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
ebase             905 drivers/media/rc/winbond-cir.c 		outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL);
ebase             907 drivers/media/rc/winbond-cir.c 		outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
ebase             913 drivers/media/rc/winbond-cir.c 	outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
ebase            1032 drivers/media/rc/winbond-cir.c 	data->ebase = pnp_port_start(device, 0);
ebase            1037 drivers/media/rc/winbond-cir.c 	if (data->wbase == 0 || data->ebase == 0 ||
ebase            1045 drivers/media/rc/winbond-cir.c 		data->wbase, data->ebase, data->sbase, data->irq);
ebase            1102 drivers/media/rc/winbond-cir.c 	if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
ebase            1104 drivers/media/rc/winbond-cir.c 			data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
ebase            1133 drivers/media/rc/winbond-cir.c 	release_region(data->ebase, EHFUNC_IOMEM_LEN);
ebase            1176 drivers/media/rc/winbond-cir.c 	release_region(data->ebase, EHFUNC_IOMEM_LEN);
ebase             265 fs/erofs/zmap.c 	const erofs_off_t ebase = ALIGN(iloc(EROFS_I_SB(inode), vi->nid) +
ebase             282 fs/erofs/zmap.c 	compacted_4b_initial = (32 - ebase % 32) / 4;
ebase             291 fs/erofs/zmap.c 	pos = ebase;