dyn_state 1361 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; dyn_state 1365 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == dyn_state 1377 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); dyn_state 334 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 345 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 356 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 367 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, dyn_state 380 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = dyn_state 383 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = dyn_state 386 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = dyn_state 388 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = dyn_state 399 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = dyn_state 403 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { dyn_state 410 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = dyn_state 412 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = dyn_state 414 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = dyn_state 419 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = dyn_state 446 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); dyn_state 447 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { dyn_state 454 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = dyn_state 456 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = dyn_state 458 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = dyn_state 461 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = dyn_state 463 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = dyn_state 469 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; dyn_state 500 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = dyn_state 502 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { dyn_state 506 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = dyn_state 514 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = dyn_state 516 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = dyn_state 518 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = dyn_state 555 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = dyn_state 557 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { dyn_state 561 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = dyn_state 568 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = dyn_state 570 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = dyn_state 572 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = dyn_state 587 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = dyn_state 589 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { dyn_state 593 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = dyn_state 597 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = dyn_state 599 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = dyn_state 610 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table = dyn_state 612 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.ppm_table) { dyn_state 616 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; dyn_state 617 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = dyn_state 619 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->platform_tdp = dyn_state 621 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = dyn_state 623 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->platform_tdc = dyn_state 625 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = dyn_state 627 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->apu_tdp = dyn_state 629 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = dyn_state 631 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = dyn_state 633 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.ppm_table->tj_max = dyn_state 645 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = dyn_state 647 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { dyn_state 651 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = dyn_state 655 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = dyn_state 657 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = dyn_state 668 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table = dyn_state 670 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c if (!adev->pm.dpm.dyn_state.cac_tdp_table) { dyn_state 678 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = dyn_state 685 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; dyn_state 688 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); dyn_state 689 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = dyn_state 691 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); dyn_state 692 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = dyn_state 694 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = dyn_state 696 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = dyn_state 698 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = dyn_state 707 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, dyn_state 710 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); dyn_state 721 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; dyn_state 723 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->vddc_dependency_on_sclk.entries); dyn_state 724 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->vddci_dependency_on_mclk.entries); dyn_state 725 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->vddc_dependency_on_mclk.entries); dyn_state 726 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->mvdd_dependency_on_mclk.entries); dyn_state 727 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->cac_leakage_table.entries); dyn_state 728 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->phase_shedding_limits_table.entries); dyn_state 729 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->ppm_table); dyn_state 730 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->cac_tdp_table); dyn_state 731 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->vce_clock_voltage_dependency_table.entries); dyn_state 732 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); dyn_state 733 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->samu_clock_voltage_dependency_table.entries); dyn_state 734 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->acp_clock_voltage_dependency_table.entries); dyn_state 735 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c kfree(dyn_state->vddgfx_dependency_on_sclk.entries); dyn_state 410 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h struct amdgpu_dpm_dynamic_state dyn_state; dyn_state 76 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 98 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 803 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 905 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; dyn_state 978 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 1039 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; dyn_state 1105 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 1164 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 1497 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; dyn_state 1533 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 1549 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 1583 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; dyn_state 1614 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 1647 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 1778 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2055 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; dyn_state 2057 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 2059 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; dyn_state 2061 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 2174 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2215 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2218 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 2352 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 2419 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2617 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); dyn_state 2256 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; dyn_state 2637 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.cac_leakage_table; dyn_state 3041 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 3239 drivers/gpu/drm/amd/amdgpu/si_dpm.c return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, dyn_state 3246 drivers/gpu/drm/amd/amdgpu/si_dpm.c return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, dyn_state 3299 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) dyn_state 3303 drivers/gpu/drm/amd/amdgpu/si_dpm.c (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / dyn_state 3304 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.mclk_sclk_ratio); dyn_state 3306 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) dyn_state 3310 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.sclk_mclk_delta); dyn_state 3325 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { dyn_state 3327 drivers/gpu/drm/amd/amdgpu/si_dpm.c (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); dyn_state 3331 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { dyn_state 3333 drivers/gpu/drm/amd/amdgpu/si_dpm.c (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); dyn_state 3486 drivers/gpu/drm/amd/amdgpu/si_dpm.c max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 3488 drivers/gpu/drm/amd/amdgpu/si_dpm.c max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 3508 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 3510 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 3512 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 3614 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 3617 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 3620 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 3623 drivers/gpu/drm/amd/amdgpu/si_dpm.c btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, dyn_state 3637 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) dyn_state 4439 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 4460 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 4556 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { dyn_state 4618 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { dyn_state 4620 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) dyn_state 4623 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { dyn_state 4625 drivers/gpu/drm/amd/amdgpu/si_dpm.c (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { dyn_state 4627 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 4629 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; dyn_state 4632 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; dyn_state 4638 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { dyn_state 4640 drivers/gpu/drm/amd/amdgpu/si_dpm.c (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { dyn_state 4642 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 4644 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; dyn_state 4647 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; dyn_state 4653 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 4654 drivers/gpu/drm/amd/amdgpu/si_dpm.c *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; dyn_state 4908 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 4992 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 5020 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 5532 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 5622 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { dyn_state 5624 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { dyn_state 5626 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) dyn_state 6358 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); dyn_state 6362 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); dyn_state 6366 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); dyn_state 7201 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; dyn_state 7202 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; dyn_state 7203 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; dyn_state 7204 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; dyn_state 7350 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = dyn_state 7354 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { dyn_state 7358 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; dyn_state 7359 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; dyn_state 7360 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; dyn_state 7361 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; dyn_state 7362 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; dyn_state 7363 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; dyn_state 7364 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; dyn_state 7365 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; dyn_state 7366 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; dyn_state 7448 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; dyn_state 7449 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; dyn_state 7450 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; dyn_state 7451 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; dyn_state 7452 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; dyn_state 7453 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; dyn_state 7454 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; dyn_state 7459 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || dyn_state 7460 drivers/gpu/drm/amd/amdgpu/si_dpm.c (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) dyn_state 7461 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = dyn_state 7462 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 7478 drivers/gpu/drm/amd/amdgpu/si_dpm.c kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); dyn_state 237 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || dyn_state 238 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) dyn_state 239 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_dc = dyn_state 240 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac; dyn_state 1130 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { dyn_state 1131 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { dyn_state 1137 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { dyn_state 1146 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); dyn_state 602 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); dyn_state 604 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c if (NULL == hwmgr->dyn_state.cac_dtp_table) { dyn_state 824 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = dyn_state 826 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = dyn_state 828 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = dyn_state 830 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = dyn_state 1138 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c kfree(hwmgr->dyn_state.cac_dtp_table); dyn_state 1139 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.cac_dtp_table = NULL; dyn_state 1239 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; dyn_state 1240 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; dyn_state 1241 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; dyn_state 1242 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; dyn_state 1243 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; dyn_state 1244 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; dyn_state 1245 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; dyn_state 1246 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; dyn_state 1247 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; dyn_state 1248 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.ppm_parameter_table = NULL; dyn_state 1249 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; dyn_state 1263 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.vce_clock_voltage_dependency_table, dyn_state 1278 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array); dyn_state 1289 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable); dyn_state 1300 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable); dyn_state 1311 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table, dyn_state 1314 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = dyn_state 1321 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.cac_dtp_table, dyn_state 1335 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.vddc_dependency_on_sclk, table); dyn_state 1343 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.vddci_dependency_on_mclk, table); dyn_state 1351 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.vddc_dependency_on_mclk, table); dyn_state 1359 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); dyn_state 1362 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && dyn_state 1363 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) dyn_state 1364 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values, dyn_state 1365 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dependency_on_mclk); dyn_state 1367 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && dyn_state 1368 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) dyn_state 1370 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.valid_sclk_values, dyn_state 1371 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dependency_on_sclk); dyn_state 1378 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); dyn_state 1389 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table); dyn_state 1450 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.ppm_parameter_table = ptr; dyn_state 1496 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.cac_leakage_table = NULL; dyn_state 1503 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table); dyn_state 1508 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.ppm_parameter_table = NULL; dyn_state 1564 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_phase_shed_limits_table = table; dyn_state 1676 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); dyn_state 1677 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; dyn_state 1679 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); dyn_state 1680 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; dyn_state 1682 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); dyn_state 1683 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; dyn_state 1685 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); dyn_state 1686 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; dyn_state 1688 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.valid_mclk_values); dyn_state 1689 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.valid_mclk_values = NULL; dyn_state 1691 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.valid_sclk_values); dyn_state 1692 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.valid_sclk_values = NULL; dyn_state 1694 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.cac_leakage_table); dyn_state 1695 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.cac_leakage_table = NULL; dyn_state 1697 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); dyn_state 1698 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; dyn_state 1700 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); dyn_state 1701 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; dyn_state 1703 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); dyn_state 1704 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; dyn_state 1706 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); dyn_state 1707 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; dyn_state 1709 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); dyn_state 1710 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; dyn_state 1712 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.cac_dtp_table); dyn_state 1713 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.cac_dtp_table = NULL; dyn_state 1715 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.ppm_parameter_table); dyn_state 1716 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.ppm_parameter_table = NULL; dyn_state 1718 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); dyn_state 1719 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; dyn_state 165 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; dyn_state 181 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c &hwmgr->dyn_state.max_clock_voltage_on_ac); dyn_state 558 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); dyn_state 559 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; dyn_state 271 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.mvdd_dependency_on_mclk); dyn_state 291 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.vddci_dependency_on_mclk); dyn_state 316 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_mclk); dyn_state 672 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 674 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_mclk; dyn_state 676 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.cac_leakage_table; dyn_state 726 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; dyn_state 737 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; dyn_state 1837 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = dyn_state 2103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; dyn_state 2104 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; dyn_state 2105 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; dyn_state 2106 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; dyn_state 2213 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = dyn_state 2216 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = dyn_state 2219 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = dyn_state 2222 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = dyn_state 2225 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = dyn_state 2402 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); dyn_state 2406 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); dyn_state 2410 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); dyn_state 2414 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); dyn_state 2418 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); dyn_state 2422 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); dyn_state 2426 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); dyn_state 2430 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); dyn_state 2434 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); dyn_state 2438 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); dyn_state 2442 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); dyn_state 2446 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); dyn_state 2458 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 2459 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; dyn_state 2460 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; dyn_state 2479 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = dyn_state 2481 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = dyn_state 2483 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = dyn_state 2491 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) dyn_state 2492 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; dyn_state 2499 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); dyn_state 2500 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; dyn_state 2755 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; dyn_state 2757 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { dyn_state 2758 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; dyn_state 2765 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; dyn_state 2769 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; dyn_state 2911 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(hwmgr->dyn_state.max_clock_voltage_on_ac) : dyn_state 2912 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(hwmgr->dyn_state.max_clock_voltage_on_dc); dyn_state 2929 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); dyn_state 3368 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.vddci_dependency_on_mclk; dyn_state 4667 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 4707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; dyn_state 1122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cac_table = hwmgr->dyn_state.cac_dtp_table; dyn_state 1207 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cac_table = hwmgr->dyn_state.cac_dtp_table; dyn_state 73 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 104 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 134 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 260 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 302 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; dyn_state 403 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c &hwmgr->dyn_state.max_clock_voltage_on_ac); dyn_state 442 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 444 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; dyn_state 446 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.acp_clock_voltage_dependency_table; dyn_state 448 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 450 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 556 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 582 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 609 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 636 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.acp_clock_voltage_dependency_table; dyn_state 685 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 721 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * dyn_state 1059 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; dyn_state 1113 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); dyn_state 1114 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; dyn_state 1145 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 1250 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 1344 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 1477 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl; dyn_state 1479 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c &hwmgr->dyn_state.max_clock_voltage_on_ac; dyn_state 1517 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 1615 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c table = hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 1634 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 1637 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c &hwmgr->dyn_state.max_clock_voltage_on_ac; dyn_state 1675 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vddc_dependency_on_sclk; dyn_state 1678 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 1681 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 1844 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 517 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; dyn_state 796 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = dyn_state 798 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = dyn_state 800 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = dyn_state 802 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = dyn_state 810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); dyn_state 811 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; dyn_state 3161 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c &(hwmgr->dyn_state.max_clock_voltage_on_ac) : dyn_state 3162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c &(hwmgr->dyn_state.max_clock_voltage_on_dc); dyn_state 3191 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); dyn_state 1023 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = dyn_state 1025 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = dyn_state 1027 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = dyn_state 1029 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = dyn_state 1266 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c kfree(hwmgr->dyn_state.cac_dtp_table); dyn_state 1267 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c hwmgr->dyn_state.cac_dtp_table = NULL; dyn_state 766 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h struct phm_dynamic_state_info dyn_state; dyn_state 417 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vddc_dependency_on_sclk, clock, dyn_state 429 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vddc_phase_shed_limits_table, dyn_state 530 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); dyn_state 583 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, dyn_state 585 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, dyn_state 587 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, dyn_state 590 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { dyn_state 592 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); dyn_state 593 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); dyn_state 594 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); dyn_state 596 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc); dyn_state 597 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage); dyn_state 658 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; dyn_state 719 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; dyn_state 720 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; dyn_state 771 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, dyn_state 775 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (NULL == hwmgr->dyn_state.cac_leakage_table) { dyn_state 780 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { dyn_state 781 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { dyn_state 783 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { dyn_state 784 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; dyn_state 785 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); dyn_state 788 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; dyn_state 789 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); dyn_state 796 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { dyn_state 797 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { dyn_state 799 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { dyn_state 800 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; dyn_state 801 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; dyn_state 804 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; dyn_state 805 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); dyn_state 965 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) dyn_state 969 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage); dyn_state 972 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) dyn_state 976 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) dyn_state 1185 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { dyn_state 1187 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); dyn_state 1192 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { dyn_state 1194 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vddci_dependency_on_mclk, dyn_state 1201 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { dyn_state 1203 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.mvdd_dependency_on_mclk, dyn_state 1213 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, dyn_state 1357 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { dyn_state 1358 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { dyn_state 1365 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, dyn_state 1523 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 1564 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 1596 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.acp_clock_voltage_dependency_table; dyn_state 1858 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); dyn_state 1861 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk dyn_state 1868 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); dyn_state 1871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk dyn_state 2859 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.uvd_clock_voltage_dependency_table; dyn_state 2864 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : dyn_state 2865 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; dyn_state 2895 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vce_clock_voltage_dependency_table; dyn_state 2900 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc : dyn_state 2901 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; dyn_state 325 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); dyn_state 376 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; dyn_state 396 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, dyn_state 398 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, dyn_state 400 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, dyn_state 404 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { dyn_state 405 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); dyn_state 406 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); dyn_state 540 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, dyn_state 544 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (NULL == hwmgr->dyn_state.cac_leakage_table) { dyn_state 554 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { dyn_state 555 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { dyn_state 557 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { dyn_state 558 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; dyn_state 559 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE); dyn_state 562 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; dyn_state 563 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); dyn_state 574 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { dyn_state 575 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { dyn_state 577 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) { dyn_state 578 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE; dyn_state 579 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE; dyn_state 582 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE; dyn_state 583 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE); dyn_state 734 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) dyn_state 738 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage); dyn_state 741 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) dyn_state 745 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) dyn_state 902 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, dyn_state 913 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c hwmgr->dyn_state.vddc_phase_shed_limits_table, dyn_state 1240 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { dyn_state 1242 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); dyn_state 1249 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { dyn_state 1251 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c hwmgr->dyn_state.vddci_dependency_on_mclk, dyn_state 1261 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table, dyn_state 1404 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { dyn_state 1405 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { dyn_state 1412 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, dyn_state 1826 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); dyn_state 1829 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk dyn_state 1836 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); dyn_state 1839 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk dyn_state 1855 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; dyn_state 1856 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; dyn_state 1232 drivers/gpu/drm/radeon/btc_dpm.c return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, dyn_state 1239 drivers/gpu/drm/radeon/btc_dpm.c return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, dyn_state 1282 drivers/gpu/drm/radeon/btc_dpm.c if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) dyn_state 1286 drivers/gpu/drm/radeon/btc_dpm.c (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / dyn_state 1287 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.mclk_sclk_ratio); dyn_state 1289 drivers/gpu/drm/radeon/btc_dpm.c if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) dyn_state 1293 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.sclk_mclk_delta); dyn_state 1320 drivers/gpu/drm/radeon/btc_dpm.c if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { dyn_state 1322 drivers/gpu/drm/radeon/btc_dpm.c (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); dyn_state 1326 drivers/gpu/drm/radeon/btc_dpm.c if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { dyn_state 1328 drivers/gpu/drm/radeon/btc_dpm.c (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); dyn_state 2112 drivers/gpu/drm/radeon/btc_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 2114 drivers/gpu/drm/radeon/btc_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 2210 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 2212 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 2214 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 2216 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, dyn_state 2219 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 2221 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 2223 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 2225 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, dyn_state 2228 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 2230 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 2232 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 2234 drivers/gpu/drm/radeon/btc_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, dyn_state 2244 drivers/gpu/drm/radeon/btc_dpm.c if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && dyn_state 2245 drivers/gpu/drm/radeon/btc_dpm.c (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) && dyn_state 2246 drivers/gpu/drm/radeon/btc_dpm.c (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)) dyn_state 2251 drivers/gpu/drm/radeon/btc_dpm.c if (ps->low.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) dyn_state 2253 drivers/gpu/drm/radeon/btc_dpm.c if (ps->medium.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) dyn_state 2255 drivers/gpu/drm/radeon/btc_dpm.c if (ps->high.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) dyn_state 2585 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = dyn_state 2589 drivers/gpu/drm/radeon/btc_dpm.c if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { dyn_state 2593 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; dyn_state 2594 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; dyn_state 2595 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; dyn_state 2596 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; dyn_state 2597 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800; dyn_state 2598 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; dyn_state 2599 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800; dyn_state 2600 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; dyn_state 2601 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800; dyn_state 2701 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; dyn_state 2702 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; dyn_state 2703 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; dyn_state 2704 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); dyn_state 2705 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; dyn_state 2706 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; dyn_state 2707 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; dyn_state 2710 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; dyn_state 2712 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000; dyn_state 2715 drivers/gpu/drm/radeon/btc_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || dyn_state 2716 drivers/gpu/drm/radeon/btc_dpm.c (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) dyn_state 2717 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = dyn_state 2718 drivers/gpu/drm/radeon/btc_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 2732 drivers/gpu/drm/radeon/btc_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); dyn_state 283 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) dyn_state 285 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) dyn_state 287 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != dyn_state 288 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) dyn_state 291 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { dyn_state 293 drivers/gpu/drm/radeon/ci_dpm.c lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); dyn_state 294 drivers/gpu/drm/radeon/ci_dpm.c hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); dyn_state 295 drivers/gpu/drm/radeon/ci_dpm.c hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); dyn_state 297 drivers/gpu/drm/radeon/ci_dpm.c lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); dyn_state 298 drivers/gpu/drm/radeon/ci_dpm.c hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); dyn_state 338 drivers/gpu/drm/radeon/ci_dpm.c tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; dyn_state 420 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table; dyn_state 437 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table; dyn_state 438 drivers/gpu/drm/radeon/ci_dpm.c struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; dyn_state 672 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table; dyn_state 746 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table; dyn_state 825 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 827 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 1636 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table; dyn_state 2147 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 2165 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 2183 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, dyn_state 2314 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { dyn_state 2315 drivers/gpu/drm/radeon/ci_dpm.c if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { dyn_state 2321 drivers/gpu/drm/radeon/ci_dpm.c if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) dyn_state 2337 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) dyn_state 2340 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { dyn_state 2341 drivers/gpu/drm/radeon/ci_dpm.c for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { dyn_state 2343 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { dyn_state 2345 drivers/gpu/drm/radeon/ci_dpm.c if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 2348 drivers/gpu/drm/radeon/ci_dpm.c idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; dyn_state 2350 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; dyn_state 2352 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; dyn_state 2358 drivers/gpu/drm/radeon/ci_dpm.c for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { dyn_state 2360 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { dyn_state 2362 drivers/gpu/drm/radeon/ci_dpm.c if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 2365 drivers/gpu/drm/radeon/ci_dpm.c idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; dyn_state 2367 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; dyn_state 2369 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; dyn_state 2593 drivers/gpu/drm/radeon/ci_dpm.c for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { dyn_state 2594 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= dyn_state 2601 drivers/gpu/drm/radeon/ci_dpm.c for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { dyn_state 2602 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= dyn_state 2656 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; dyn_state 2660 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; dyn_state 2662 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; dyn_state 2664 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; dyn_state 2699 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; dyn_state 2703 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; dyn_state 2705 drivers/gpu/drm/radeon/ci_dpm.c (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; dyn_state 2732 drivers/gpu/drm/radeon/ci_dpm.c (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); dyn_state 2736 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; dyn_state 2738 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; dyn_state 2764 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; dyn_state 2768 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; dyn_state 2770 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; dyn_state 2883 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { dyn_state 2885 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 2891 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { dyn_state 2893 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 2899 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { dyn_state 2901 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, dyn_state 2911 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 3137 drivers/gpu/drm/radeon/ci_dpm.c if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) dyn_state 3141 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; dyn_state 3143 drivers/gpu/drm/radeon/ci_dpm.c if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) dyn_state 3147 drivers/gpu/drm/radeon/ci_dpm.c ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * dyn_state 3228 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 3240 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 3445 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 3447 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; dyn_state 3449 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.cac_leakage_table; dyn_state 3514 drivers/gpu/drm/radeon/ci_dpm.c allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; dyn_state 3524 drivers/gpu/drm/radeon/ci_dpm.c allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; dyn_state 3786 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; dyn_state 3788 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 3938 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 3940 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 3945 drivers/gpu/drm/radeon/ci_dpm.c for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { dyn_state 3946 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { dyn_state 3987 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 3989 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 3993 drivers/gpu/drm/radeon/ci_dpm.c for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { dyn_state 3994 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { dyn_state 4020 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 4022 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 4026 drivers/gpu/drm/radeon/ci_dpm.c for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { dyn_state 4027 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { dyn_state 4051 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 4053 drivers/gpu/drm/radeon/ci_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 4057 drivers/gpu/drm/radeon/ci_dpm.c for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { dyn_state 4058 drivers/gpu/drm/radeon/ci_dpm.c if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { dyn_state 4084 drivers/gpu/drm/radeon/ci_dpm.c (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) dyn_state 4088 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; dyn_state 4104 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 4921 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 4923 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; dyn_state 4925 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; dyn_state 4948 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = dyn_state 4950 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = dyn_state 4952 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = dyn_state 4954 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = dyn_state 5067 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); dyn_state 5069 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); dyn_state 5071 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); dyn_state 5073 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); dyn_state 5075 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); dyn_state 5077 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); dyn_state 5079 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); dyn_state 5081 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); dyn_state 5083 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); dyn_state 5085 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); dyn_state 5087 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); dyn_state 5089 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.dyn_state.cac_leakage_table); dyn_state 5671 drivers/gpu/drm/radeon/ci_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); dyn_state 5788 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = dyn_state 5792 drivers/gpu/drm/radeon/ci_dpm.c if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { dyn_state 5796 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; dyn_state 5797 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; dyn_state 5798 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; dyn_state 5799 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; dyn_state 5800 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; dyn_state 5801 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; dyn_state 5802 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; dyn_state 5803 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; dyn_state 5804 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; dyn_state 5806 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; dyn_state 5807 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; dyn_state 5808 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; dyn_state 5810 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; dyn_state 5811 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; dyn_state 5812 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; dyn_state 5813 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; dyn_state 5932 drivers/gpu/drm/radeon/ci_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || dyn_state 5933 drivers/gpu/drm/radeon/ci_dpm.c (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) dyn_state 5934 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = dyn_state 5935 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 558 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 580 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 721 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 823 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; dyn_state 896 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 957 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; dyn_state 1023 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 1082 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 1429 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; dyn_state 1465 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 1481 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 1522 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; dyn_state 1553 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 1586 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 1714 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 1989 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; dyn_state 1991 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 1993 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; dyn_state 1995 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; dyn_state 2109 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2150 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2153 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 2287 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 2354 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; dyn_state 2549 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); dyn_state 804 drivers/gpu/drm/radeon/ni_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 806 drivers/gpu/drm/radeon/ni_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 875 drivers/gpu/drm/radeon/ni_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 878 drivers/gpu/drm/radeon/ni_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 881 drivers/gpu/drm/radeon/ni_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 884 drivers/gpu/drm/radeon/ni_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, dyn_state 898 drivers/gpu/drm/radeon/ni_dpm.c if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) dyn_state 901 drivers/gpu/drm/radeon/ni_dpm.c if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) dyn_state 1014 drivers/gpu/drm/radeon/ni_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); dyn_state 1017 drivers/gpu/drm/radeon/ni_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); dyn_state 1348 drivers/gpu/drm/radeon/ni_dpm.c if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries && dyn_state 1349 drivers/gpu/drm/radeon/ni_dpm.c ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)) dyn_state 1350 drivers/gpu/drm/radeon/ni_dpm.c *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; dyn_state 3098 drivers/gpu/drm/radeon/ni_dpm.c &rdev->pm.dpm.dyn_state.cac_leakage_table; dyn_state 3978 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; dyn_state 3979 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; dyn_state 3980 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; dyn_state 3981 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; dyn_state 4080 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = dyn_state 4084 drivers/gpu/drm/radeon/ni_dpm.c if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { dyn_state 4088 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; dyn_state 4089 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; dyn_state 4090 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; dyn_state 4091 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; dyn_state 4092 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; dyn_state 4093 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; dyn_state 4094 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; dyn_state 4095 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; dyn_state 4096 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; dyn_state 4197 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3; dyn_state 4198 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; dyn_state 4199 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; dyn_state 4200 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk); dyn_state 4201 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk; dyn_state 4202 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; dyn_state 4203 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; dyn_state 4204 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500; dyn_state 4261 drivers/gpu/drm/radeon/ni_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || dyn_state 4262 drivers/gpu/drm/radeon/ni_dpm.c (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) dyn_state 4263 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = dyn_state 4264 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 4278 drivers/gpu/drm/radeon/ni_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); dyn_state 926 drivers/gpu/drm/radeon/r600_dpm.c ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 935 drivers/gpu/drm/radeon/r600_dpm.c ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 938 drivers/gpu/drm/radeon/r600_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); dyn_state 946 drivers/gpu/drm/radeon/r600_dpm.c ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 949 drivers/gpu/drm/radeon/r600_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); dyn_state 950 drivers/gpu/drm/radeon/r600_dpm.c kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); dyn_state 958 drivers/gpu/drm/radeon/r600_dpm.c ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, dyn_state 961 drivers/gpu/drm/radeon/r600_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); dyn_state 962 drivers/gpu/drm/radeon/r600_dpm.c kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); dyn_state 963 drivers/gpu/drm/radeon/r600_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); dyn_state 973 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = dyn_state 976 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = dyn_state 979 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = dyn_state 981 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = dyn_state 992 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = dyn_state 996 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { dyn_state 1003 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = dyn_state 1005 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = dyn_state 1007 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = dyn_state 1012 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count = dyn_state 1039 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); dyn_state 1040 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { dyn_state 1047 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = dyn_state 1049 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = dyn_state 1051 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = dyn_state 1054 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = dyn_state 1056 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = dyn_state 1062 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; dyn_state 1093 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = dyn_state 1095 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { dyn_state 1099 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = dyn_state 1107 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = dyn_state 1109 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = dyn_state 1111 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = dyn_state 1147 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = dyn_state 1149 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { dyn_state 1153 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = dyn_state 1160 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = dyn_state 1162 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = dyn_state 1164 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = dyn_state 1179 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = dyn_state 1181 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { dyn_state 1185 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = dyn_state 1189 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = dyn_state 1191 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = dyn_state 1202 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table = dyn_state 1204 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.ppm_table) { dyn_state 1208 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; dyn_state 1209 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number = dyn_state 1211 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->platform_tdp = dyn_state 1213 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = dyn_state 1215 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->platform_tdc = dyn_state 1217 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = dyn_state 1219 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->apu_tdp = dyn_state 1221 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = dyn_state 1223 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = dyn_state 1225 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.ppm_table->tj_max = dyn_state 1237 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = dyn_state 1239 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { dyn_state 1243 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = dyn_state 1247 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = dyn_state 1249 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = dyn_state 1260 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table = dyn_state 1262 drivers/gpu/drm/radeon/r600_dpm.c if (!rdev->pm.dpm.dyn_state.cac_tdp_table) { dyn_state 1270 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = dyn_state 1277 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; dyn_state 1280 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); dyn_state 1281 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = dyn_state 1283 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); dyn_state 1284 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = dyn_state 1286 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = dyn_state 1288 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = dyn_state 1290 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = dyn_state 1300 drivers/gpu/drm/radeon/r600_dpm.c struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; dyn_state 1302 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->vddc_dependency_on_sclk.entries); dyn_state 1303 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->vddci_dependency_on_mclk.entries); dyn_state 1304 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->vddc_dependency_on_mclk.entries); dyn_state 1305 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->mvdd_dependency_on_mclk.entries); dyn_state 1306 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->cac_leakage_table.entries); dyn_state 1307 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->phase_shedding_limits_table.entries); dyn_state 1308 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->ppm_table); dyn_state 1309 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->cac_tdp_table); dyn_state 1310 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->vce_clock_voltage_dependency_table.entries); dyn_state 1311 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); dyn_state 1312 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->samu_clock_voltage_dependency_table.entries); dyn_state 1313 drivers/gpu/drm/radeon/r600_dpm.c kfree(dyn_state->acp_clock_voltage_dependency_table.entries); dyn_state 1560 drivers/gpu/drm/radeon/radeon.h struct radeon_dpm_dynamic_state dyn_state; dyn_state 3316 drivers/gpu/drm/radeon/radeon_atombios.c u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; dyn_state 3320 drivers/gpu/drm/radeon/radeon_atombios.c if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == dyn_state 3332 drivers/gpu/drm/radeon/radeon_atombios.c cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); dyn_state 520 drivers/gpu/drm/radeon/radeon_kms.c *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; dyn_state 2259 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; dyn_state 2260 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; dyn_state 2261 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; dyn_state 2262 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; dyn_state 2166 drivers/gpu/drm/radeon/si_dpm.c struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; dyn_state 2539 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.cac_leakage_table; dyn_state 2942 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; dyn_state 3027 drivers/gpu/drm/radeon/si_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 3029 drivers/gpu/drm/radeon/si_dpm.c max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; dyn_state 3049 drivers/gpu/drm/radeon/si_dpm.c btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 3051 drivers/gpu/drm/radeon/si_dpm.c btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 3053 drivers/gpu/drm/radeon/si_dpm.c btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 3155 drivers/gpu/drm/radeon/si_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, dyn_state 3158 drivers/gpu/drm/radeon/si_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 3161 drivers/gpu/drm/radeon/si_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 3164 drivers/gpu/drm/radeon/si_dpm.c btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, dyn_state 3178 drivers/gpu/drm/radeon/si_dpm.c if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) dyn_state 3977 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, dyn_state 3998 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, dyn_state 4094 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { dyn_state 4156 drivers/gpu/drm/radeon/si_dpm.c if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { dyn_state 4158 drivers/gpu/drm/radeon/si_dpm.c if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) dyn_state 4161 drivers/gpu/drm/radeon/si_dpm.c for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { dyn_state 4163 drivers/gpu/drm/radeon/si_dpm.c (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { dyn_state 4165 drivers/gpu/drm/radeon/si_dpm.c if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 4167 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; dyn_state 4170 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; dyn_state 4176 drivers/gpu/drm/radeon/si_dpm.c for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { dyn_state 4178 drivers/gpu/drm/radeon/si_dpm.c (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { dyn_state 4180 drivers/gpu/drm/radeon/si_dpm.c if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 4182 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; dyn_state 4185 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; dyn_state 4191 drivers/gpu/drm/radeon/si_dpm.c if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) dyn_state 4192 drivers/gpu/drm/radeon/si_dpm.c *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; dyn_state 4444 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 4530 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 4557 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 5070 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, dyn_state 5160 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { dyn_state 5162 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { dyn_state 5164 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) dyn_state 5906 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); dyn_state 5908 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); dyn_state 5910 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); dyn_state 6801 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; dyn_state 6802 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; dyn_state 6803 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; dyn_state 6804 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; dyn_state 6960 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = dyn_state 6964 drivers/gpu/drm/radeon/si_dpm.c if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { dyn_state 6968 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; dyn_state 6969 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; dyn_state 6970 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; dyn_state 6971 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; dyn_state 6972 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; dyn_state 6973 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; dyn_state 6974 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; dyn_state 6975 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; dyn_state 6976 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; dyn_state 7058 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; dyn_state 7059 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; dyn_state 7060 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; dyn_state 7061 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; dyn_state 7062 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; dyn_state 7063 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; dyn_state 7064 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; dyn_state 7069 drivers/gpu/drm/radeon/si_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || dyn_state 7070 drivers/gpu/drm/radeon/si_dpm.c (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) dyn_state 7071 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = dyn_state 7072 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; dyn_state 7088 drivers/gpu/drm/radeon/si_dpm.c kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); dyn_state 1511 drivers/gpu/drm/radeon/trinity_dpm.c &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;