dwbc20             34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->dwbc_regs->reg
dwbc20             37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->base.ctx
dwbc20             40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->base.ctx->logger
dwbc20             43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
dwbc20             52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20             64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst);
dwbc20             67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst);
dwbc20             74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20             75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
dwbc20            101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);
dwbc20            110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst);
dwbc20            137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst);
dwbc20            160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);
dwbc20            169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base.inst);
dwbc20            200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 		dwbc20->base.inst, stereo_params->stereo_enabled);
dwbc20            229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
dwbc20            238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
dwbc20            252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
dwbc20            253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
dwbc20            279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 			dwb_program_horz_scalar(dwbc20, params->cnv_params.crop_width,
dwbc20            284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 			dwb_program_vert_scalar(dwbc20, params->cnv_params.crop_height,
dwbc20            290 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 			dwb_program_horz_scalar(dwbc20, params->cnv_params.src_width,
dwbc20            295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 			dwb_program_vert_scalar(dwbc20, params->cnv_params.src_height,
dwbc20            316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
dwbc20            323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->base.ctx = ctx;
dwbc20            325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->base.inst = inst;
dwbc20            326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->base.funcs = &dcn20_dwbc_funcs;
dwbc20            328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->dwbc_regs = dwbc_regs;
dwbc20            329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->dwbc_shift = dwbc_shift;
dwbc20            330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	dwbc20->dwbc_mask = dwbc_mask;
dwbc20            422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
dwbc20            444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
dwbc20            450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
dwbc20             37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	dwbc20->dwbc_regs->reg
dwbc20             40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	dwbc20->base.ctx
dwbc20             44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
dwbc20            683 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	struct dcn20_dwbc *dwbc20,
dwbc20            719 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
dwbc20            790 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	wbscl_set_scaler_filter(dwbc20, h_taps_luma,
dwbc20            793 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	wbscl_set_scaler_filter(dwbc20, h_taps_chroma,
dwbc20            799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
dwbc20            871 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	wbscl_set_scaler_filter(dwbc20, v_taps_luma,
dwbc20            874 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	wbscl_set_scaler_filter(dwbc20, v_taps_chroma,
dwbc20           3025 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
dwbc20           3028 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (!dwbc20) {
dwbc20           3032 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dcn20_dwbc_construct(dwbc20, ctx,
dwbc20           3037 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->dwbc[i] = &dwbc20->base;