dwb_pipe_inst     389 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
dwb_pipe_inst     396 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb_pipe_inst     404 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
dwb_pipe_inst     422 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb_pipe_inst     438 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		uint32_t dwb_pipe_inst)
dwb_pipe_inst     446 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (dwb_pipe_inst >= MAX_DWB_PIPES) {
dwb_pipe_inst     455 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
dwb_pipe_inst     479 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		dc->hwss.disable_writeback(dc, dwb_pipe_inst);
dwb_pipe_inst      90 drivers/gpu/drm/amd/display/dc/dc_stream.h 	int dwb_pipe_inst;
dwb_pipe_inst     342 drivers/gpu/drm/amd/display/dc/dc_stream.h 		uint32_t dwb_pipe_inst);
dwb_pipe_inst    1365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
dwb_pipe_inst    1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb_pipe_inst    1368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
dwb_pipe_inst    1373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
dwb_pipe_inst    1376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
dwb_pipe_inst    1386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		unsigned int dwb_pipe_inst)
dwb_pipe_inst    1391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
dwb_pipe_inst    1392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
dwb_pipe_inst    1393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
dwb_pipe_inst      63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 		unsigned int dwb_pipe_inst);
dwb_pipe_inst     305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		uint32_t dwb_pipe_inst)
dwb_pipe_inst     309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	if (dwb_pipe_inst == 0)
dwb_pipe_inst     312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	else if (dwb_pipe_inst == 1)
dwb_pipe_inst     240 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 		uint32_t dwb_pipe_inst);
dwb_pipe_inst     331 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			unsigned int dwb_pipe_inst);