dwb               748 arch/mips/include/asm/octeon/cvmx-iob-defs.h 		uint64_t dwb:3;
dwb               754 arch/mips/include/asm/octeon/cvmx-iob-defs.h 		uint64_t dwb:3;
dwb               716 arch/mips/include/asm/octeon/cvmx-pko-defs.h 		uint64_t dwb:9;
dwb               722 arch/mips/include/asm/octeon/cvmx-pko-defs.h 		uint64_t dwb:9;
dwb               377 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dwbc *dwb;
dwb               396 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb               397 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	dwb->dwb_is_drc = false;
dwb               422 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb               424 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		if (dwb->funcs->is_enabled(dwb)) {
dwb              1361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dwbc *dwb;
dwb              1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb              1380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
dwb              1388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dwbc *dwb;
dwb              1392 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
dwb              1395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dwb->funcs->disable(dwb);