dw_plat_data      138 drivers/gpu/drm/meson/meson_dw_hdmi.c 	struct dw_hdmi_plat_data dw_plat_data;
dw_plat_data      813 drivers/gpu/drm/meson/meson_dw_hdmi.c 	struct dw_hdmi_plat_data *dw_plat_data;
dw_plat_data      840 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data = &meson_dw_hdmi->dw_plat_data;
dw_plat_data      894 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi,
dw_plat_data      896 drivers/gpu/drm/meson/meson_dw_hdmi.c 	if (IS_ERR(dw_plat_data->regm))
dw_plat_data      897 drivers/gpu/drm/meson/meson_dw_hdmi.c 		return PTR_ERR(dw_plat_data->regm);
dw_plat_data      965 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->mode_valid = dw_hdmi_mode_valid;
dw_plat_data      966 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops;
dw_plat_data      967 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->phy_name = "meson_dw_hdmi_phy";
dw_plat_data      968 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->phy_data = meson_dw_hdmi;
dw_plat_data      969 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
dw_plat_data      970 drivers/gpu/drm/meson/meson_dw_hdmi.c 	dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
dw_plat_data      975 drivers/gpu/drm/meson/meson_dw_hdmi.c 					   &meson_dw_hdmi->dw_plat_data);