dw9 50 drivers/crypto/hisilicon/zip/zip.h u32 dw9; dw9 83 drivers/crypto/hisilicon/zip/zip_crypto.c val = (sqe->dw9) & ~HZIP_BUF_TYPE_M; dw9 85 drivers/crypto/hisilicon/zip/zip_crypto.c sqe->dw9 = val; dw9 102 drivers/crypto/hisilicon/zip/zip_crypto.c sqe->dw9 = FIELD_PREP(HZIP_REQ_TYPE_M, req_type); dw9 26 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 dw1, dw9, dw10; dw9 29 drivers/gpu/drm/i915/display/intel_combo_phy.c { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, dw9 31 drivers/gpu/drm/i915/display/intel_combo_phy.c { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, dw9 33 drivers/gpu/drm/i915/display/intel_combo_phy.c { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, dw9 35 drivers/gpu/drm/i915/display/intel_combo_phy.c { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, dw9 37 drivers/gpu/drm/i915/display/intel_combo_phy.c { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, dw9 89 drivers/gpu/drm/i915/display/intel_combo_phy.c I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); dw9 121 drivers/gpu/drm/i915/display/intel_combo_phy.c -1U, procmon->dw9);