dvo_val 284 drivers/gpu/drm/i915/display/intel_dvo.c u32 dvo_val; dvo_val 289 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val = I915_READ(dvo_reg) & dvo_val 291 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | dvo_val 294 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val |= DVO_PIPE_SEL(pipe); dvo_val 295 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val |= DVO_PIPE_STALL; dvo_val 297 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val |= DVO_HSYNC_ACTIVE_HIGH; dvo_val 299 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val |= DVO_VSYNC_ACTIVE_HIGH; dvo_val 308 drivers/gpu/drm/i915/display/intel_dvo.c I915_WRITE(dvo_reg, dvo_val);