dvo 376 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; dvo 410 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.dvo.sDVOEncoder.ucAction = action; dvo 411 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); dvo 413 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; dvo 416 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; dvo 166 drivers/gpu/drm/i915/display/dvo_ch7017.c static void ch7017_dump_regs(struct intel_dvo_device *dvo); dvo 167 drivers/gpu/drm/i915/display/dvo_ch7017.c static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable); dvo 169 drivers/gpu/drm/i915/display/dvo_ch7017.c static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val) dvo 173 drivers/gpu/drm/i915/display/dvo_ch7017.c .addr = dvo->slave_addr, dvo 179 drivers/gpu/drm/i915/display/dvo_ch7017.c .addr = dvo->slave_addr, dvo 185 drivers/gpu/drm/i915/display/dvo_ch7017.c return i2c_transfer(dvo->i2c_bus, msgs, 2) == 2; dvo 188 drivers/gpu/drm/i915/display/dvo_ch7017.c static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val) dvo 192 drivers/gpu/drm/i915/display/dvo_ch7017.c .addr = dvo->slave_addr, dvo 197 drivers/gpu/drm/i915/display/dvo_ch7017.c return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1; dvo 201 drivers/gpu/drm/i915/display/dvo_ch7017.c static bool ch7017_init(struct intel_dvo_device *dvo, dvo 212 drivers/gpu/drm/i915/display/dvo_ch7017.c dvo->i2c_bus = adapter; dvo 213 drivers/gpu/drm/i915/display/dvo_ch7017.c dvo->dev_priv = priv; dvo 215 drivers/gpu/drm/i915/display/dvo_ch7017.c if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val)) dvo 231 drivers/gpu/drm/i915/display/dvo_ch7017.c val, adapter->name, dvo->slave_addr); dvo 236 drivers/gpu/drm/i915/display/dvo_ch7017.c str, adapter->name, dvo->slave_addr); dvo 244 drivers/gpu/drm/i915/display/dvo_ch7017.c static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo) dvo 249 drivers/gpu/drm/i915/display/dvo_ch7017.c static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo, dvo 258 drivers/gpu/drm/i915/display/dvo_ch7017.c static void ch7017_mode_set(struct intel_dvo_device *dvo, dvo 269 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_dump_regs(dvo); dvo 313 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_dpms(dvo, false); dvo 314 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, dvo 316 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT, dvo 318 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, dvo 320 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, dvo 322 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control); dvo 323 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div); dvo 324 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_LVDS_CONTROL_2, lvds_control_2); dvo 325 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, outputs_enable); dvo 328 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); dvo 331 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_dump_regs(dvo); dvo 335 drivers/gpu/drm/i915/display/dvo_ch7017.c static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable) dvo 339 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); dvo 342 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_POWER_MANAGEMENT, dvo 351 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, dvo 355 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, dvo 363 drivers/gpu/drm/i915/display/dvo_ch7017.c static bool ch7017_get_hw_state(struct intel_dvo_device *dvo) dvo 367 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); dvo 375 drivers/gpu/drm/i915/display/dvo_ch7017.c static void ch7017_dump_regs(struct intel_dvo_device *dvo) dvo 381 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, reg, &val); \ dvo 396 drivers/gpu/drm/i915/display/dvo_ch7017.c static void ch7017_destroy(struct intel_dvo_device *dvo) dvo 398 drivers/gpu/drm/i915/display/dvo_ch7017.c struct ch7017_priv *priv = dvo->dev_priv; dvo 402 drivers/gpu/drm/i915/display/dvo_ch7017.c dvo->dev_priv = NULL; dvo 136 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch) dvo 138 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct ch7xxx_priv *ch7xxx = dvo->dev_priv; dvo 139 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 145 drivers/gpu/drm/i915/display/dvo_ch7xxx.c .addr = dvo->slave_addr, dvo 151 drivers/gpu/drm/i915/display/dvo_ch7xxx.c .addr = dvo->slave_addr, dvo 168 drivers/gpu/drm/i915/display/dvo_ch7xxx.c addr, adapter->name, dvo->slave_addr); dvo 174 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch) dvo 176 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct ch7xxx_priv *ch7xxx = dvo->dev_priv; dvo 177 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 180 drivers/gpu/drm/i915/display/dvo_ch7xxx.c .addr = dvo->slave_addr, dvo 194 drivers/gpu/drm/i915/display/dvo_ch7xxx.c addr, adapter->name, dvo->slave_addr); dvo 200 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static bool ch7xxx_init(struct intel_dvo_device *dvo, dvo 212 drivers/gpu/drm/i915/display/dvo_ch7xxx.c dvo->i2c_bus = adapter; dvo 213 drivers/gpu/drm/i915/display/dvo_ch7xxx.c dvo->dev_priv = ch7xxx; dvo 216 drivers/gpu/drm/i915/display/dvo_ch7xxx.c if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) dvo 222 drivers/gpu/drm/i915/display/dvo_ch7xxx.c vendor, adapter->name, dvo->slave_addr); dvo 227 drivers/gpu/drm/i915/display/dvo_ch7xxx.c if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) dvo 233 drivers/gpu/drm/i915/display/dvo_ch7xxx.c device, adapter->name, dvo->slave_addr); dvo 246 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) dvo 250 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); dvo 256 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_PM, pm); dvo 258 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); dvo 260 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); dvo 267 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, dvo 276 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static void ch7xxx_mode_set(struct intel_dvo_device *dvo, dvo 294 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); dvo 295 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); dvo 296 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); dvo 297 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); dvo 298 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); dvo 299 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); dvo 300 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); dvo 302 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, CH7xxx_IDF, &idf); dvo 311 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_IDF, idf); dvo 315 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) dvo 318 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); dvo 320 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); dvo 323 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo) dvo 327 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, CH7xxx_PM, &val); dvo 335 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) dvo 343 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, i, &val); dvo 348 drivers/gpu/drm/i915/display/dvo_ch7xxx.c static void ch7xxx_destroy(struct intel_dvo_device *dvo) dvo 350 drivers/gpu/drm/i915/display/dvo_ch7xxx.c struct ch7xxx_priv *ch7xxx = dvo->dev_priv; dvo 354 drivers/gpu/drm/i915/display/dvo_ch7xxx.c dvo->dev_priv = NULL; dvo 186 drivers/gpu/drm/i915/display/dvo_ivch.c static void ivch_dump_regs(struct intel_dvo_device *dvo); dvo 192 drivers/gpu/drm/i915/display/dvo_ivch.c static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data) dvo 194 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dvo 195 drivers/gpu/drm/i915/display/dvo_ivch.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 201 drivers/gpu/drm/i915/display/dvo_ivch.c .addr = dvo->slave_addr, dvo 212 drivers/gpu/drm/i915/display/dvo_ivch.c .addr = dvo->slave_addr, dvo 229 drivers/gpu/drm/i915/display/dvo_ivch.c addr, adapter->name, dvo->slave_addr); dvo 235 drivers/gpu/drm/i915/display/dvo_ivch.c static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data) dvo 237 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dvo 238 drivers/gpu/drm/i915/display/dvo_ivch.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 241 drivers/gpu/drm/i915/display/dvo_ivch.c .addr = dvo->slave_addr, dvo 256 drivers/gpu/drm/i915/display/dvo_ivch.c addr, adapter->name, dvo->slave_addr); dvo 263 drivers/gpu/drm/i915/display/dvo_ivch.c static bool ivch_init(struct intel_dvo_device *dvo, dvo 274 drivers/gpu/drm/i915/display/dvo_ivch.c dvo->i2c_bus = adapter; dvo 275 drivers/gpu/drm/i915/display/dvo_ivch.c dvo->dev_priv = priv; dvo 278 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR00, &temp)) dvo 286 drivers/gpu/drm/i915/display/dvo_ivch.c if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { dvo 289 drivers/gpu/drm/i915/display/dvo_ivch.c (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); dvo 293 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR20, &priv->width); dvo 294 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR21, &priv->height); dvo 300 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, backup_addresses[i], priv->reg_backup + i); dvo 302 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_dump_regs(dvo); dvo 311 drivers/gpu/drm/i915/display/dvo_ivch.c static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) dvo 316 drivers/gpu/drm/i915/display/dvo_ivch.c static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, dvo 329 drivers/gpu/drm/i915/display/dvo_ivch.c static void ivch_reset(struct intel_dvo_device *dvo) dvo 331 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dvo 336 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR10, 0x0000); dvo 339 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]); dvo 343 drivers/gpu/drm/i915/display/dvo_ivch.c static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) dvo 348 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_reset(dvo); dvo 351 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR01, &vr01)) dvo 359 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR80, backlight); dvo 366 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR01, vr01); dvo 370 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR30, &vr30)) dvo 381 drivers/gpu/drm/i915/display/dvo_ivch.c static bool ivch_get_hw_state(struct intel_dvo_device *dvo) dvo 385 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_reset(dvo); dvo 388 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR01, &vr01)) dvo 397 drivers/gpu/drm/i915/display/dvo_ivch.c static void ivch_mode_set(struct intel_dvo_device *dvo, dvo 401 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dvo 406 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_reset(dvo); dvo 428 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR42, x_ratio); dvo 429 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR41, y_ratio); dvo 436 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR01, vr01); dvo 437 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_write(dvo, VR40, vr40); dvo 440 drivers/gpu/drm/i915/display/dvo_ivch.c static void ivch_dump_regs(struct intel_dvo_device *dvo) dvo 444 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR00, &val); dvo 446 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR01, &val); dvo 448 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR10, &val); dvo 450 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR30, &val); dvo 452 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR40, &val); dvo 456 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR80, &val); dvo 458 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR81, &val); dvo 460 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR82, &val); dvo 462 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR83, &val); dvo 464 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR84, &val); dvo 466 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR85, &val); dvo 468 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR86, &val); dvo 470 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR87, &val); dvo 472 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR88, &val); dvo 476 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR8E, &val); dvo 480 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR8F, &val); dvo 484 drivers/gpu/drm/i915/display/dvo_ivch.c static void ivch_destroy(struct intel_dvo_device *dvo) dvo 486 drivers/gpu/drm/i915/display/dvo_ivch.c struct ivch_priv *priv = dvo->dev_priv; dvo 490 drivers/gpu/drm/i915/display/dvo_ivch.c dvo->dev_priv = NULL; dvo 393 drivers/gpu/drm/i915/display/dvo_ns2501.c static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch) dvo 395 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = dvo->dev_priv; dvo 396 drivers/gpu/drm/i915/display/dvo_ns2501.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 402 drivers/gpu/drm/i915/display/dvo_ns2501.c .addr = dvo->slave_addr, dvo 408 drivers/gpu/drm/i915/display/dvo_ns2501.c .addr = dvo->slave_addr, dvo 426 drivers/gpu/drm/i915/display/dvo_ns2501.c adapter->name, dvo->slave_addr); dvo 438 drivers/gpu/drm/i915/display/dvo_ns2501.c static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch) dvo 440 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = dvo->dev_priv; dvo 441 drivers/gpu/drm/i915/display/dvo_ns2501.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 445 drivers/gpu/drm/i915/display/dvo_ns2501.c .addr = dvo->slave_addr, dvo 460 drivers/gpu/drm/i915/display/dvo_ns2501.c addr, adapter->name, dvo->slave_addr); dvo 472 drivers/gpu/drm/i915/display/dvo_ns2501.c static bool ns2501_init(struct intel_dvo_device *dvo, dvo 483 drivers/gpu/drm/i915/display/dvo_ns2501.c dvo->i2c_bus = adapter; dvo 484 drivers/gpu/drm/i915/display/dvo_ns2501.c dvo->dev_priv = ns; dvo 487 drivers/gpu/drm/i915/display/dvo_ns2501.c if (!ns2501_readb(dvo, NS2501_VID_LO, &ch)) dvo 492 drivers/gpu/drm/i915/display/dvo_ns2501.c ch, adapter->name, dvo->slave_addr); dvo 496 drivers/gpu/drm/i915/display/dvo_ns2501.c if (!ns2501_readb(dvo, NS2501_DID_LO, &ch)) dvo 501 drivers/gpu/drm/i915/display/dvo_ns2501.c ch, adapter->name, dvo->slave_addr); dvo 515 drivers/gpu/drm/i915/display/dvo_ns2501.c static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo) dvo 527 drivers/gpu/drm/i915/display/dvo_ns2501.c static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo, dvo 549 drivers/gpu/drm/i915/display/dvo_ns2501.c static void ns2501_mode_set(struct intel_dvo_device *dvo, dvo 554 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); dvo 602 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value); dvo 606 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, mode_agnostic_values[i].offset, dvo 613 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG8, conf->conf); dvo 614 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG1B, conf->pll_a); dvo 615 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG1C, conf->pll_b & 0xff); dvo 616 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG1D, conf->pll_b >> 8); dvo 617 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC1, conf->hstart & 0xff); dvo 618 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC2, conf->hstart >> 8); dvo 619 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC3, conf->hstop & 0xff); dvo 620 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC4, conf->hstop >> 8); dvo 621 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC5, conf->vstart & 0xff); dvo 622 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC6, conf->vstart >> 8); dvo 623 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC7, conf->vstop & 0xff); dvo 624 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC8, conf->vstop >> 8); dvo 625 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG80, conf->vsync & 0xff); dvo 626 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG81, conf->vsync >> 8); dvo 627 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG82, conf->vtotal & 0xff); dvo 628 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG83, conf->vtotal >> 8); dvo 629 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG98, conf->hpos & 0xff); dvo 630 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG99, conf->hpos >> 8); dvo 631 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG8E, conf->vpos & 0xff); dvo 632 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG8F, conf->vpos >> 8); dvo 633 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG9C, conf->voffs & 0xff); dvo 634 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG9D, conf->voffs >> 8); dvo 635 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGB8, conf->hscale & 0xff); dvo 636 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGB9, conf->hscale >> 8); dvo 637 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG10, conf->vscale & 0xff); dvo 638 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG11, conf->vscale >> 8); dvo 639 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGF9, conf->dither); dvo 640 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG41, conf->syncb); dvo 641 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC0, conf->sync); dvo 645 drivers/gpu/drm/i915/display/dvo_ns2501.c static bool ns2501_get_hw_state(struct intel_dvo_device *dvo) dvo 649 drivers/gpu/drm/i915/display/dvo_ns2501.c if (!ns2501_readb(dvo, NS2501_REG8, &ch)) dvo 656 drivers/gpu/drm/i915/display/dvo_ns2501.c static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) dvo 658 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); dvo 663 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync | 0x08); dvo 665 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG41, ns->conf->syncb); dvo 667 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT); dvo 670 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG8, dvo 673 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG8, ns->conf->conf); dvo 676 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG34, dvo 679 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync); dvo 681 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT); dvo 684 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG8, NS2501_8_VEN | NS2501_8_HEN | dvo 688 drivers/gpu/drm/i915/display/dvo_ns2501.c ns2501_writeb(dvo, NS2501_REG34, 0x00); dvo 692 drivers/gpu/drm/i915/display/dvo_ns2501.c static void ns2501_destroy(struct intel_dvo_device *dvo) dvo 694 drivers/gpu/drm/i915/display/dvo_ns2501.c struct ns2501_priv *ns = dvo->dev_priv; dvo 698 drivers/gpu/drm/i915/display/dvo_ns2501.c dvo->dev_priv = NULL; dvo 69 drivers/gpu/drm/i915/display/dvo_sil164.c static bool sil164_readb(struct intel_dvo_device *dvo, int addr, u8 *ch) dvo 71 drivers/gpu/drm/i915/display/dvo_sil164.c struct sil164_priv *sil = dvo->dev_priv; dvo 72 drivers/gpu/drm/i915/display/dvo_sil164.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 78 drivers/gpu/drm/i915/display/dvo_sil164.c .addr = dvo->slave_addr, dvo 84 drivers/gpu/drm/i915/display/dvo_sil164.c .addr = dvo->slave_addr, dvo 101 drivers/gpu/drm/i915/display/dvo_sil164.c addr, adapter->name, dvo->slave_addr); dvo 106 drivers/gpu/drm/i915/display/dvo_sil164.c static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, u8 ch) dvo 108 drivers/gpu/drm/i915/display/dvo_sil164.c struct sil164_priv *sil = dvo->dev_priv; dvo 109 drivers/gpu/drm/i915/display/dvo_sil164.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 112 drivers/gpu/drm/i915/display/dvo_sil164.c .addr = dvo->slave_addr, dvo 126 drivers/gpu/drm/i915/display/dvo_sil164.c addr, adapter->name, dvo->slave_addr); dvo 133 drivers/gpu/drm/i915/display/dvo_sil164.c static bool sil164_init(struct intel_dvo_device *dvo, dvo 144 drivers/gpu/drm/i915/display/dvo_sil164.c dvo->i2c_bus = adapter; dvo 145 drivers/gpu/drm/i915/display/dvo_sil164.c dvo->dev_priv = sil; dvo 148 drivers/gpu/drm/i915/display/dvo_sil164.c if (!sil164_readb(dvo, SIL164_VID_LO, &ch)) dvo 153 drivers/gpu/drm/i915/display/dvo_sil164.c ch, adapter->name, dvo->slave_addr); dvo 157 drivers/gpu/drm/i915/display/dvo_sil164.c if (!sil164_readb(dvo, SIL164_DID_LO, &ch)) dvo 162 drivers/gpu/drm/i915/display/dvo_sil164.c ch, adapter->name, dvo->slave_addr); dvo 175 drivers/gpu/drm/i915/display/dvo_sil164.c static enum drm_connector_status sil164_detect(struct intel_dvo_device *dvo) dvo 179 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REG9, ®9); dvo 187 drivers/gpu/drm/i915/display/dvo_sil164.c static enum drm_mode_status sil164_mode_valid(struct intel_dvo_device *dvo, dvo 193 drivers/gpu/drm/i915/display/dvo_sil164.c static void sil164_mode_set(struct intel_dvo_device *dvo, dvo 212 drivers/gpu/drm/i915/display/dvo_sil164.c static void sil164_dpms(struct intel_dvo_device *dvo, bool enable) dvo 217 drivers/gpu/drm/i915/display/dvo_sil164.c ret = sil164_readb(dvo, SIL164_REG8, &ch); dvo 226 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_writeb(dvo, SIL164_REG8, ch); dvo 230 drivers/gpu/drm/i915/display/dvo_sil164.c static bool sil164_get_hw_state(struct intel_dvo_device *dvo) dvo 235 drivers/gpu/drm/i915/display/dvo_sil164.c ret = sil164_readb(dvo, SIL164_REG8, &ch); dvo 245 drivers/gpu/drm/i915/display/dvo_sil164.c static void sil164_dump_regs(struct intel_dvo_device *dvo) dvo 249 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_FREQ_LO, &val); dvo 251 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_FREQ_HI, &val); dvo 253 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REG8, &val); dvo 255 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REG9, &val); dvo 257 drivers/gpu/drm/i915/display/dvo_sil164.c sil164_readb(dvo, SIL164_REGC, &val); dvo 261 drivers/gpu/drm/i915/display/dvo_sil164.c static void sil164_destroy(struct intel_dvo_device *dvo) dvo 263 drivers/gpu/drm/i915/display/dvo_sil164.c struct sil164_priv *sil = dvo->dev_priv; dvo 267 drivers/gpu/drm/i915/display/dvo_sil164.c dvo->dev_priv = NULL; dvo 94 drivers/gpu/drm/i915/display/dvo_tfp410.c static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch) dvo 96 drivers/gpu/drm/i915/display/dvo_tfp410.c struct tfp410_priv *tfp = dvo->dev_priv; dvo 97 drivers/gpu/drm/i915/display/dvo_tfp410.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 103 drivers/gpu/drm/i915/display/dvo_tfp410.c .addr = dvo->slave_addr, dvo 109 drivers/gpu/drm/i915/display/dvo_tfp410.c .addr = dvo->slave_addr, dvo 126 drivers/gpu/drm/i915/display/dvo_tfp410.c addr, adapter->name, dvo->slave_addr); dvo 131 drivers/gpu/drm/i915/display/dvo_tfp410.c static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch) dvo 133 drivers/gpu/drm/i915/display/dvo_tfp410.c struct tfp410_priv *tfp = dvo->dev_priv; dvo 134 drivers/gpu/drm/i915/display/dvo_tfp410.c struct i2c_adapter *adapter = dvo->i2c_bus; dvo 137 drivers/gpu/drm/i915/display/dvo_tfp410.c .addr = dvo->slave_addr, dvo 151 drivers/gpu/drm/i915/display/dvo_tfp410.c addr, adapter->name, dvo->slave_addr); dvo 157 drivers/gpu/drm/i915/display/dvo_tfp410.c static int tfp410_getid(struct intel_dvo_device *dvo, int addr) dvo 161 drivers/gpu/drm/i915/display/dvo_tfp410.c if (tfp410_readb(dvo, addr+0, &ch1) && dvo 162 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, addr+1, &ch2)) dvo 169 drivers/gpu/drm/i915/display/dvo_tfp410.c static bool tfp410_init(struct intel_dvo_device *dvo, dvo 180 drivers/gpu/drm/i915/display/dvo_tfp410.c dvo->i2c_bus = adapter; dvo 181 drivers/gpu/drm/i915/display/dvo_tfp410.c dvo->dev_priv = tfp; dvo 184 drivers/gpu/drm/i915/display/dvo_tfp410.c if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) { dvo 187 drivers/gpu/drm/i915/display/dvo_tfp410.c id, adapter->name, dvo->slave_addr); dvo 191 drivers/gpu/drm/i915/display/dvo_tfp410.c if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) { dvo 194 drivers/gpu/drm/i915/display/dvo_tfp410.c id, adapter->name, dvo->slave_addr); dvo 204 drivers/gpu/drm/i915/display/dvo_tfp410.c static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo) dvo 209 drivers/gpu/drm/i915/display/dvo_tfp410.c if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { dvo 219 drivers/gpu/drm/i915/display/dvo_tfp410.c static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo, dvo 225 drivers/gpu/drm/i915/display/dvo_tfp410.c static void tfp410_mode_set(struct intel_dvo_device *dvo, dvo 238 drivers/gpu/drm/i915/display/dvo_tfp410.c static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable) dvo 242 drivers/gpu/drm/i915/display/dvo_tfp410.c if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1)) dvo 250 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_writeb(dvo, TFP410_CTL_1, ctl1); dvo 253 drivers/gpu/drm/i915/display/dvo_tfp410.c static bool tfp410_get_hw_state(struct intel_dvo_device *dvo) dvo 257 drivers/gpu/drm/i915/display/dvo_tfp410.c if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1)) dvo 266 drivers/gpu/drm/i915/display/dvo_tfp410.c static void tfp410_dump_regs(struct intel_dvo_device *dvo) dvo 270 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_REV, &val); dvo 272 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_CTL_1, &val); dvo 274 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_CTL_2, &val); dvo 276 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_CTL_3, &val); dvo 278 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_USERCFG, &val); dvo 280 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_DLY, &val); dvo 282 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_CTL, &val); dvo 284 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_TOP, &val); dvo 286 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); dvo 287 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); dvo 289 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); dvo 290 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); dvo 292 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_H_RES_LO, &val); dvo 293 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_H_RES_HI, &val2); dvo 295 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_V_RES_LO, &val); dvo 296 drivers/gpu/drm/i915/display/dvo_tfp410.c tfp410_readb(dvo, TFP410_V_RES_HI, &val2); dvo 300 drivers/gpu/drm/i915/display/dvo_tfp410.c static void tfp410_destroy(struct intel_dvo_device *dvo) dvo 302 drivers/gpu/drm/i915/display/dvo_tfp410.c struct tfp410_priv *tfp = dvo->dev_priv; dvo 306 drivers/gpu/drm/i915/display/dvo_tfp410.c dvo->dev_priv = NULL; dvo 442 drivers/gpu/drm/i915/display/intel_dvo.c const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; dvo 455 drivers/gpu/drm/i915/display/intel_dvo.c if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) dvo 456 drivers/gpu/drm/i915/display/intel_dvo.c gpio = dvo->gpio; dvo 457 drivers/gpu/drm/i915/display/intel_dvo.c else if (dvo->type == INTEL_DVO_CHIP_LVDS) dvo 469 drivers/gpu/drm/i915/display/intel_dvo.c intel_dvo->dev = *dvo; dvo 488 drivers/gpu/drm/i915/display/intel_dvo.c dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); dvo 500 drivers/gpu/drm/i915/display/intel_dvo.c port = intel_dvo_port(dvo->dvo_reg); dvo 510 drivers/gpu/drm/i915/display/intel_dvo.c switch (dvo->type) { dvo 535 drivers/gpu/drm/i915/display/intel_dvo.c if (dvo->type == INTEL_DVO_CHIP_LVDS) { dvo 52 drivers/gpu/drm/i915/display/intel_dvo_dev.h bool (*init)(struct intel_dvo_device *dvo, dvo 59 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*create_resources)(struct intel_dvo_device *dvo); dvo 67 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*dpms)(struct intel_dvo_device *dvo, bool enable); dvo 78 drivers/gpu/drm/i915/display/intel_dvo_dev.h int (*mode_valid)(struct intel_dvo_device *dvo, dvo 84 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*prepare)(struct intel_dvo_device *dvo); dvo 89 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*commit)(struct intel_dvo_device *dvo); dvo 98 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*mode_set)(struct intel_dvo_device *dvo, dvo 105 drivers/gpu/drm/i915/display/intel_dvo_dev.h enum drm_connector_status (*detect)(struct intel_dvo_device *dvo); dvo 120 drivers/gpu/drm/i915/display/intel_dvo_dev.h struct drm_display_mode *(*get_modes)(struct intel_dvo_device *dvo); dvo 125 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*destroy) (struct intel_dvo_device *dvo); dvo 130 drivers/gpu/drm/i915/display/intel_dvo_dev.h void (*dump_regs)(struct intel_dvo_device *dvo); dvo 487 drivers/gpu/drm/radeon/atombios_encoders.c DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; dvo 525 drivers/gpu/drm/radeon/atombios_encoders.c args.dvo.sDVOEncoder.ucAction = action; dvo 526 drivers/gpu/drm/radeon/atombios_encoders.c args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); dvo 528 drivers/gpu/drm/radeon/atombios_encoders.c args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; dvo 531 drivers/gpu/drm/radeon/atombios_encoders.c args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; dvo 104 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo; dvo 111 drivers/gpu/drm/sti/sti_dvo.c static int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code) dvo 113 drivers/gpu/drm/sti/sti_dvo.c struct drm_display_mode *mode = &dvo->mode; dvo 114 drivers/gpu/drm/sti/sti_dvo.c struct dvo_config *config = dvo->config; dvo 147 drivers/gpu/drm/sti/sti_dvo.c static void dvo_awg_configure(struct sti_dvo *dvo, u32 *awg_ram_code, int nb) dvo 155 drivers/gpu/drm/sti/sti_dvo.c dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4); dvo 157 drivers/gpu/drm/sti/sti_dvo.c writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4); dvo 159 drivers/gpu/drm/sti/sti_dvo.c writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL); dvo 163 drivers/gpu/drm/sti/sti_dvo.c readl(dvo->regs + reg)) dvo 181 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = (struct sti_dvo *)node->info_ent->data; dvo 183 drivers/gpu/drm/sti/sti_dvo.c seq_printf(s, "DVO: (vaddr = 0x%p)", dvo->regs); dvo 189 drivers/gpu/drm/sti/sti_dvo.c dvo_dbg_awg_microcode(s, dvo->regs + DVO_DIGSYNC_INSTR_I); dvo 198 drivers/gpu/drm/sti/sti_dvo.c static int dvo_debugfs_init(struct sti_dvo *dvo, struct drm_minor *minor) dvo 203 drivers/gpu/drm/sti/sti_dvo.c dvo_debugfs_files[i].data = dvo; dvo 212 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = bridge->driver_private; dvo 214 drivers/gpu/drm/sti/sti_dvo.c if (!dvo->enabled) dvo 219 drivers/gpu/drm/sti/sti_dvo.c if (dvo->config->awg_fwgen_fct) dvo 220 drivers/gpu/drm/sti/sti_dvo.c writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL); dvo 222 drivers/gpu/drm/sti/sti_dvo.c writel(0x00000000, dvo->regs + DVO_DOF_CFG); dvo 224 drivers/gpu/drm/sti/sti_dvo.c drm_panel_disable(dvo->panel); dvo 227 drivers/gpu/drm/sti/sti_dvo.c clk_disable_unprepare(dvo->clk_pix); dvo 228 drivers/gpu/drm/sti/sti_dvo.c clk_disable_unprepare(dvo->clk); dvo 230 drivers/gpu/drm/sti/sti_dvo.c dvo->enabled = false; dvo 235 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = bridge->driver_private; dvo 236 drivers/gpu/drm/sti/sti_dvo.c struct dvo_config *config = dvo->config; dvo 241 drivers/gpu/drm/sti/sti_dvo.c if (dvo->enabled) dvo 245 drivers/gpu/drm/sti/sti_dvo.c writel(0x00000000, dvo->regs + DVO_DOF_CFG); dvo 246 drivers/gpu/drm/sti/sti_dvo.c writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL); dvo 252 drivers/gpu/drm/sti/sti_dvo.c if (!dvo_awg_generate_code(dvo, &nb_instr, awg_ram_code)) dvo 253 drivers/gpu/drm/sti/sti_dvo.c dvo_awg_configure(dvo, awg_ram_code, nb_instr); dvo 259 drivers/gpu/drm/sti/sti_dvo.c if (clk_prepare_enable(dvo->clk_pix)) dvo 261 drivers/gpu/drm/sti/sti_dvo.c if (clk_prepare_enable(dvo->clk)) dvo 264 drivers/gpu/drm/sti/sti_dvo.c drm_panel_enable(dvo->panel); dvo 267 drivers/gpu/drm/sti/sti_dvo.c writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW); dvo 268 drivers/gpu/drm/sti/sti_dvo.c writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID); dvo 269 drivers/gpu/drm/sti/sti_dvo.c writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH); dvo 273 drivers/gpu/drm/sti/sti_dvo.c writel(val, dvo->regs + DVO_DOF_CFG); dvo 275 drivers/gpu/drm/sti/sti_dvo.c dvo->enabled = true; dvo 282 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = bridge->driver_private; dvo 283 drivers/gpu/drm/sti/sti_dvo.c struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc); dvo 290 drivers/gpu/drm/sti/sti_dvo.c memcpy(&dvo->mode, mode, sizeof(struct drm_display_mode)); dvo 295 drivers/gpu/drm/sti/sti_dvo.c clkp = dvo->clk_main_parent; dvo 297 drivers/gpu/drm/sti/sti_dvo.c clkp = dvo->clk_aux_parent; dvo 300 drivers/gpu/drm/sti/sti_dvo.c clk_set_parent(dvo->clk_pix, clkp); dvo 301 drivers/gpu/drm/sti/sti_dvo.c clk_set_parent(dvo->clk, clkp); dvo 305 drivers/gpu/drm/sti/sti_dvo.c ret = clk_set_rate(dvo->clk_pix, rate); dvo 311 drivers/gpu/drm/sti/sti_dvo.c ret = clk_set_rate(dvo->clk, rate); dvo 318 drivers/gpu/drm/sti/sti_dvo.c dvo->config = &rgb_24bit_de_cfg; dvo 338 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = dvo_connector->dvo; dvo 340 drivers/gpu/drm/sti/sti_dvo.c if (dvo->panel) dvo 341 drivers/gpu/drm/sti/sti_dvo.c return drm_panel_get_modes(dvo->panel); dvo 357 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = dvo_connector->dvo; dvo 359 drivers/gpu/drm/sti/sti_dvo.c result = clk_round_rate(dvo->clk_pix, target); dvo 383 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = dvo_connector->dvo; dvo 387 drivers/gpu/drm/sti/sti_dvo.c if (!dvo->panel) { dvo 388 drivers/gpu/drm/sti/sti_dvo.c dvo->panel = of_drm_find_panel(dvo->panel_node); dvo 389 drivers/gpu/drm/sti/sti_dvo.c if (IS_ERR(dvo->panel)) dvo 390 drivers/gpu/drm/sti/sti_dvo.c dvo->panel = NULL; dvo 392 drivers/gpu/drm/sti/sti_dvo.c drm_panel_attach(dvo->panel, connector); dvo 395 drivers/gpu/drm/sti/sti_dvo.c if (dvo->panel) dvo 405 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = dvo_connector->dvo; dvo 407 drivers/gpu/drm/sti/sti_dvo.c if (dvo_debugfs_init(dvo, dvo->drm_dev->primary)) { dvo 439 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = dev_get_drvdata(dev); dvo 448 drivers/gpu/drm/sti/sti_dvo.c dvo->drm_dev = drm_dev; dvo 458 drivers/gpu/drm/sti/sti_dvo.c connector->dvo = dvo; dvo 464 drivers/gpu/drm/sti/sti_dvo.c bridge->driver_private = dvo; dvo 466 drivers/gpu/drm/sti/sti_dvo.c bridge->of_node = dvo->dev.of_node; dvo 475 drivers/gpu/drm/sti/sti_dvo.c dvo->bridge = bridge; dvo 477 drivers/gpu/drm/sti/sti_dvo.c dvo->encoder = encoder; dvo 504 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo = dev_get_drvdata(dev); dvo 506 drivers/gpu/drm/sti/sti_dvo.c drm_bridge_remove(dvo->bridge); dvo 517 drivers/gpu/drm/sti/sti_dvo.c struct sti_dvo *dvo; dvo 523 drivers/gpu/drm/sti/sti_dvo.c dvo = devm_kzalloc(dev, sizeof(*dvo), GFP_KERNEL); dvo 524 drivers/gpu/drm/sti/sti_dvo.c if (!dvo) { dvo 529 drivers/gpu/drm/sti/sti_dvo.c dvo->dev = pdev->dev; dvo 536 drivers/gpu/drm/sti/sti_dvo.c dvo->regs = devm_ioremap_nocache(dev, res->start, dvo 538 drivers/gpu/drm/sti/sti_dvo.c if (!dvo->regs) dvo 541 drivers/gpu/drm/sti/sti_dvo.c dvo->clk_pix = devm_clk_get(dev, "dvo_pix"); dvo 542 drivers/gpu/drm/sti/sti_dvo.c if (IS_ERR(dvo->clk_pix)) { dvo 544 drivers/gpu/drm/sti/sti_dvo.c return PTR_ERR(dvo->clk_pix); dvo 547 drivers/gpu/drm/sti/sti_dvo.c dvo->clk = devm_clk_get(dev, "dvo"); dvo 548 drivers/gpu/drm/sti/sti_dvo.c if (IS_ERR(dvo->clk)) { dvo 550 drivers/gpu/drm/sti/sti_dvo.c return PTR_ERR(dvo->clk); dvo 553 drivers/gpu/drm/sti/sti_dvo.c dvo->clk_main_parent = devm_clk_get(dev, "main_parent"); dvo 554 drivers/gpu/drm/sti/sti_dvo.c if (IS_ERR(dvo->clk_main_parent)) { dvo 556 drivers/gpu/drm/sti/sti_dvo.c dvo->clk_main_parent = NULL; dvo 559 drivers/gpu/drm/sti/sti_dvo.c dvo->clk_aux_parent = devm_clk_get(dev, "aux_parent"); dvo 560 drivers/gpu/drm/sti/sti_dvo.c if (IS_ERR(dvo->clk_aux_parent)) { dvo 562 drivers/gpu/drm/sti/sti_dvo.c dvo->clk_aux_parent = NULL; dvo 565 drivers/gpu/drm/sti/sti_dvo.c dvo->panel_node = of_parse_phandle(np, "sti,panel", 0); dvo 566 drivers/gpu/drm/sti/sti_dvo.c if (!dvo->panel_node) dvo 568 drivers/gpu/drm/sti/sti_dvo.c of_node_put(dvo->panel_node); dvo 570 drivers/gpu/drm/sti/sti_dvo.c platform_set_drvdata(pdev, dvo); dvo 119 drivers/gpu/drm/sti/sti_tvout.c struct drm_encoder *dvo; dvo 518 drivers/gpu/drm/sti/sti_tvout.c crtc = tvout->dvo->crtc; dvo 789 drivers/gpu/drm/sti/sti_tvout.c tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout); dvo 792 drivers/gpu/drm/sti/sti_tvout.c drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo); dvo 794 drivers/gpu/drm/sti/sti_tvout.c drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo); dvo 795 drivers/gpu/drm/sti/sti_tvout.c tvout->dvo->possible_clones = drm_encoder_mask(tvout->hdmi) | dvo 796 drivers/gpu/drm/sti/sti_tvout.c drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo); dvo 809 drivers/gpu/drm/sti/sti_tvout.c if (tvout->dvo) dvo 810 drivers/gpu/drm/sti/sti_tvout.c drm_encoder_cleanup(tvout->dvo); dvo 811 drivers/gpu/drm/sti/sti_tvout.c tvout->dvo = NULL; dvo 474 drivers/video/fbdev/intelfb/intelfbdrv.c int i, err, dvo; dvo 771 drivers/video/fbdev/intelfb/intelfbdrv.c dvo = intelfbhw_check_non_crt(dinfo); dvo 772 drivers/video/fbdev/intelfb/intelfbdrv.c if (dvo) { dvo 776 drivers/video/fbdev/intelfb/intelfbdrv.c while (dvo) { dvo 777 drivers/video/fbdev/intelfb/intelfbdrv.c if (dvo & 1) { dvo 782 drivers/video/fbdev/intelfb/intelfbdrv.c dvo >>= 1; dvo 284 drivers/video/fbdev/intelfb/intelfbhw.c int dvo = 0; dvo 287 drivers/video/fbdev/intelfb/intelfbhw.c dvo |= LVDS_PORT; dvo 289 drivers/video/fbdev/intelfb/intelfbhw.c dvo |= DVOA_PORT; dvo 291 drivers/video/fbdev/intelfb/intelfbhw.c dvo |= DVOB_PORT; dvo 293 drivers/video/fbdev/intelfb/intelfbhw.c dvo |= DVOC_PORT; dvo 295 drivers/video/fbdev/intelfb/intelfbhw.c return dvo; dvo 298 drivers/video/fbdev/intelfb/intelfbhw.c const char * intelfbhw_dvo_to_string(int dvo) dvo 300 drivers/video/fbdev/intelfb/intelfbhw.c if (dvo & DVOA_PORT) dvo 302 drivers/video/fbdev/intelfb/intelfbhw.c else if (dvo & DVOB_PORT) dvo 304 drivers/video/fbdev/intelfb/intelfbhw.c else if (dvo & DVOC_PORT) dvo 306 drivers/video/fbdev/intelfb/intelfbhw.c else if (dvo & LVDS_PORT) dvo 565 drivers/video/fbdev/intelfb/intelfbhw.h extern const char *intelfbhw_dvo_to_string(int dvo);