dtv_hsync_skew     90 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
dtv_hsync_skew    109 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	dtv_hsync_skew = 0;  /* get this from panel? */
dtv_hsync_skew    116 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
dtv_hsync_skew    117 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
dtv_hsync_skew    133 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
dtv_hsync_skew    102 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
dtv_hsync_skew    123 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	dtv_hsync_skew = 0;  /* get this from panel? */
dtv_hsync_skew    152 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
dtv_hsync_skew    153 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
dtv_hsync_skew    179 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);