dstate           9661 drivers/gpu/drm/i915/intel_pm.c 	u32 dstate = I915_READ(D_STATE);
dstate           9663 drivers/gpu/drm/i915/intel_pm.c 	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
dstate           9665 drivers/gpu/drm/i915/intel_pm.c 	I915_WRITE(D_STATE, dstate);
dstate            103 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h 	int dstate; /* display adjustment (min+) */
dstate            310 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		   clk->astate, clk->temp, clk->dstate);
dstate            316 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		pstate = max(pstate, clk->dstate);
dstate            553 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (!rel) clk->dstate  = req;
dstate            554 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if ( rel) clk->dstate += rel;
dstate            555 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	clk->dstate = min(clk->dstate, clk->state_nr - 1);
dstate            556 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	clk->dstate = max(clk->dstate, 0);
dstate            617 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	clk->dstate = 0;
dstate           1727 drivers/staging/rts5208/rtsx_chip.c static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
dstate           1732 drivers/staging/rts5208/rtsx_chip.c 		chip->product_id, dstate);
dstate           1745 drivers/staging/rts5208/rtsx_chip.c 		rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
dstate           1748 drivers/staging/rts5208/rtsx_chip.c 	rtsx_write_config_byte(chip, 0x44, dstate);