dst_y_per_meta_row_nom_l  614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
dst_y_per_meta_row_nom_l  910 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
dst_y_per_meta_row_nom_l  210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
dst_y_per_meta_row_nom_l  270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
dst_y_per_meta_row_nom_l  115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
dst_y_per_meta_row_nom_l 1108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
dst_y_per_meta_row_nom_l 1461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
dst_y_per_meta_row_nom_l 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
dst_y_per_meta_row_nom_l 1465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
dst_y_per_meta_row_nom_l 1461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
dst_y_per_meta_row_nom_l 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
dst_y_per_meta_row_nom_l 1465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
dst_y_per_meta_row_nom_l 1557 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
dst_y_per_meta_row_nom_l 1559 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
dst_y_per_meta_row_nom_l 1561 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
dst_y_per_meta_row_nom_l  435 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int dst_y_per_meta_row_nom_l;
dst_y_per_meta_row_nom_l  278 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 			dlg_regs.dst_y_per_meta_row_nom_l);
dst_y_per_meta_row_nom_l 1553 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
dst_y_per_meta_row_nom_l 1555 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
dst_y_per_meta_row_nom_l 1557 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now */