dst_y_delta_drq_limit  215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
dst_y_delta_drq_limit  275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
dst_y_delta_drq_limit 1522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
dst_y_delta_drq_limit 1524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
dst_y_delta_drq_limit 1522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
dst_y_delta_drq_limit 1524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
dst_y_delta_drq_limit 1622 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
dst_y_delta_drq_limit 1624 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
dst_y_delta_drq_limit  452 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int dst_y_delta_drq_limit;
dst_y_delta_drq_limit  314 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 			dlg_regs.dst_y_delta_drq_limit);