dst_reloc        2800 drivers/gpu/drm/radeon/evergreen_cs.c 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;
dst_reloc        2821 drivers/gpu/drm/radeon/evergreen_cs.c 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
dst_reloc        2832 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        2840 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2841 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2848 drivers/gpu/drm/radeon/evergreen_cs.c 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2850 drivers/gpu/drm/radeon/evergreen_cs.c 					 dst_offset, radeon_bo_size(dst_reloc->robj));
dst_reloc        2860 drivers/gpu/drm/radeon/evergreen_cs.c 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
dst_reloc        2878 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2880 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        2883 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2885 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2900 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2901 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2911 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        2918 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2920 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        2937 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2939 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + count, radeon_bo_size(dst_reloc->robj));
dst_reloc        2942 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff);
dst_reloc        2944 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2957 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff);
dst_reloc        2958 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2981 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2983 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        2991 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2994 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        3021 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        3023 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        3031 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        3049 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        3050 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        3056 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        3083 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        3085 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        3093 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        3111 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        3112 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        3122 drivers/gpu/drm/radeon/evergreen_cs.c 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        3129 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        3131 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        3144 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        3170 drivers/gpu/drm/radeon/evergreen_cs.c 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        3172 drivers/gpu/drm/radeon/evergreen_cs.c 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        3180 drivers/gpu/drm/radeon/evergreen_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        3192 drivers/gpu/drm/radeon/evergreen_cs.c 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
dst_reloc        3199 drivers/gpu/drm/radeon/evergreen_cs.c 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        3201 drivers/gpu/drm/radeon/evergreen_cs.c 					 dst_offset, radeon_bo_size(dst_reloc->robj));
dst_reloc        3204 drivers/gpu/drm/radeon/evergreen_cs.c 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        3205 drivers/gpu/drm/radeon/evergreen_cs.c 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;
dst_reloc        2381 drivers/gpu/drm/radeon/r600_cs.c 	struct radeon_bo_list *src_reloc, *dst_reloc;
dst_reloc        2402 drivers/gpu/drm/radeon/r600_cs.c 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
dst_reloc        2411 drivers/gpu/drm/radeon/r600_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        2417 drivers/gpu/drm/radeon/r600_cs.c 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2418 drivers/gpu/drm/radeon/r600_cs.c 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2421 drivers/gpu/drm/radeon/r600_cs.c 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2423 drivers/gpu/drm/radeon/r600_cs.c 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        2433 drivers/gpu/drm/radeon/r600_cs.c 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
dst_reloc        2449 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2450 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2460 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
dst_reloc        2470 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2472 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
dst_reloc        2481 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2484 drivers/gpu/drm/radeon/r600_cs.c 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;
dst_reloc        2493 drivers/gpu/drm/radeon/r600_cs.c 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2495 drivers/gpu/drm/radeon/r600_cs.c 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        2504 drivers/gpu/drm/radeon/r600_cs.c 			r = r600_dma_cs_next_reloc(p, &dst_reloc);
dst_reloc        2511 drivers/gpu/drm/radeon/r600_cs.c 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dst_reloc        2513 drivers/gpu/drm/radeon/r600_cs.c 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
dst_reloc        2516 drivers/gpu/drm/radeon/r600_cs.c 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
dst_reloc        2517 drivers/gpu/drm/radeon/r600_cs.c 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;