dst2_offset 2804 drivers/gpu/drm/radeon/evergreen_cs.c u64 src_offset, dst_offset, dst2_offset; dst2_offset 2972 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset = radeon_get_ib_value(p, idx+2); dst2_offset 2973 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; dst2_offset 2986 drivers/gpu/drm/radeon/evergreen_cs.c if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { dst2_offset 2988 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); dst2_offset 3012 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset = radeon_get_ib_value(p, idx+2); dst2_offset 3013 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset <<= 8; dst2_offset 3026 drivers/gpu/drm/radeon/evergreen_cs.c if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { dst2_offset 3028 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); dst2_offset 3074 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset = radeon_get_ib_value(p, idx+2); dst2_offset 3075 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset <<= 8; dst2_offset 3088 drivers/gpu/drm/radeon/evergreen_cs.c if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { dst2_offset 3090 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); dst2_offset 3161 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset = radeon_get_ib_value(p, idx+2); dst2_offset 3162 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset <<= 8; dst2_offset 3175 drivers/gpu/drm/radeon/evergreen_cs.c if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { dst2_offset 3177 drivers/gpu/drm/radeon/evergreen_cs.c dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));