dspp             1261 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case 0: return (mdp5_cfg->dspp.base[0]);
dspp             1262 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case 1: return (mdp5_cfg->dspp.base[1]);
dspp             1263 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case 2: return (mdp5_cfg->dspp.base[2]);
dspp             1264 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case 3: return (mdp5_cfg->dspp.base[3]);
dspp               66 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp               68 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = 1, .dspp = 1,
dspp               70 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 2, .pp = 2, .dspp = 2,
dspp               72 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp               74 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 4, .pp = -1, .dspp = -1,
dspp               81 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              144 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              146 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = 1, .dspp = 1,
dspp              148 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 2, .pp = 2, .dspp = 2,
dspp              150 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp              152 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 4, .pp = -1, .dspp = -1,
dspp              159 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              234 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              237 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = 1, .dspp = 1,
dspp              239 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 2, .pp = 2, .dspp = 2,
dspp              242 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp              244 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 4, .pp = -1, .dspp = -1,
dspp              246 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 5, .pp = 3, .dspp = 3,
dspp              253 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              321 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              323 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp              330 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              396 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              399 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = 1, .dspp = 1,
dspp              401 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 2, .pp = 2, .dspp = 2,
dspp              404 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp              406 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 4, .pp = -1, .dspp = -1,
dspp              408 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 5, .pp = 3, .dspp = 3,
dspp              415 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              497 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              500 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = 1, .dspp = 1,
dspp              502 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 2, .pp = 2, .dspp = -1,
dspp              505 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp              507 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 4, .pp = -1, .dspp = -1,
dspp              509 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 5, .pp = 3, .dspp = -1,
dspp              516 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              601 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              603 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = -1, .dspp = -1,
dspp              610 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp              690 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 0, .pp = 0, .dspp = 0,
dspp              693 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 1, .pp = 1, .dspp = 1,
dspp              695 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 2, .pp = 2, .dspp = -1,
dspp              698 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 3, .pp = -1, .dspp = -1,
dspp              700 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 4, .pp = -1, .dspp = -1,
dspp              702 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 				{ .id = 5, .pp = 3, .dspp = -1,
dspp              709 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.dspp = {
dspp               37 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h 	int dspp;
dspp               90 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h 	struct mdp5_sub_block dspp;
dspp              157 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c 	mixer->dspp = lm->dspp;
dspp               18 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h 	int dspp;