dspcntr           581 drivers/gpu/drm/gma500/cdv_intel_display.c 	u32 dpll = 0, dspcntr, pipeconf;
dspcntr           716 drivers/gpu/drm/gma500/cdv_intel_display.c 	dspcntr = DISPPLANE_GAMMA_ENABLE;
dspcntr           719 drivers/gpu/drm/gma500/cdv_intel_display.c 		dspcntr |= DISPPLANE_SEL_PIPE_A;
dspcntr           721 drivers/gpu/drm/gma500/cdv_intel_display.c 		dspcntr |= DISPPLANE_SEL_PIPE_B;
dspcntr           723 drivers/gpu/drm/gma500/cdv_intel_display.c 	dspcntr |= DISPLAY_PLANE_ENABLE;
dspcntr           812 drivers/gpu/drm/gma500/cdv_intel_display.c 	REG_WRITE(map->cntr, dspcntr);
dspcntr            61 drivers/gpu/drm/gma500/gma_display.c 	u32 dspcntr;
dspcntr            85 drivers/gpu/drm/gma500/gma_display.c 	dspcntr = REG_READ(map->cntr);
dspcntr            86 drivers/gpu/drm/gma500/gma_display.c 	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
dspcntr            90 drivers/gpu/drm/gma500/gma_display.c 		dspcntr |= DISPPLANE_8BPP;
dspcntr            94 drivers/gpu/drm/gma500/gma_display.c 			dspcntr |= DISPPLANE_15_16BPP;
dspcntr            96 drivers/gpu/drm/gma500/gma_display.c 			dspcntr |= DISPPLANE_16BPP;
dspcntr           100 drivers/gpu/drm/gma500/gma_display.c 		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
dspcntr           107 drivers/gpu/drm/gma500/gma_display.c 	REG_WRITE(map->cntr, dspcntr);
dspcntr           125 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	u32 dspcntr = dev_priv->dspcntr[pipe];
dspcntr           143 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 		REG_WRITE(dspcntr_reg, dspcntr);
dspcntr           828 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	u32 pipeconf, dspcntr;
dspcntr           836 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	dspcntr = dev_priv->dspcntr[pipe];
dspcntr           913 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	REG_WRITE(dspcntr_reg, dspcntr);
dspcntr           122 drivers/gpu/drm/gma500/mdfld_intel_display.c 	u32 dspcntr;
dspcntr           124 drivers/gpu/drm/gma500/mdfld_intel_display.c 	dspcntr = REG_READ(dspcntr_reg);
dspcntr           127 drivers/gpu/drm/gma500/mdfld_intel_display.c 		dspcntr &= ~DISPPLANE_32BPP_NO_ALPHA;
dspcntr           128 drivers/gpu/drm/gma500/mdfld_intel_display.c 		dspcntr |= DISPPLANE_32BPP;
dspcntr           130 drivers/gpu/drm/gma500/mdfld_intel_display.c 		dspcntr &= ~DISPPLANE_32BPP;
dspcntr           131 drivers/gpu/drm/gma500/mdfld_intel_display.c 		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
dspcntr           134 drivers/gpu/drm/gma500/mdfld_intel_display.c 	REG_WRITE(dspcntr_reg, dspcntr);
dspcntr           164 drivers/gpu/drm/gma500/mdfld_intel_display.c 	u32 dspcntr;
dspcntr           193 drivers/gpu/drm/gma500/mdfld_intel_display.c 	dspcntr = REG_READ(map->cntr);
dspcntr           194 drivers/gpu/drm/gma500/mdfld_intel_display.c 	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
dspcntr           198 drivers/gpu/drm/gma500/mdfld_intel_display.c 		dspcntr |= DISPPLANE_8BPP;
dspcntr           202 drivers/gpu/drm/gma500/mdfld_intel_display.c 			dspcntr |= DISPPLANE_15_16BPP;
dspcntr           204 drivers/gpu/drm/gma500/mdfld_intel_display.c 			dspcntr |= DISPPLANE_16BPP;
dspcntr           208 drivers/gpu/drm/gma500/mdfld_intel_display.c 		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
dspcntr           211 drivers/gpu/drm/gma500/mdfld_intel_display.c 	REG_WRITE(map->cntr, dspcntr);
dspcntr           848 drivers/gpu/drm/gma500/mdfld_intel_display.c 	dev_priv->dspcntr[pipe] = REG_READ(map->cntr);
dspcntr           849 drivers/gpu/drm/gma500/mdfld_intel_display.c 	dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS;
dspcntr           850 drivers/gpu/drm/gma500/mdfld_intel_display.c 	dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE;
dspcntr          1004 drivers/gpu/drm/gma500/mdfld_intel_display.c 	REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);
dspcntr           370 drivers/gpu/drm/gma500/oaktrail_crtc.c 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
dspcntr           487 drivers/gpu/drm/gma500/oaktrail_crtc.c 	dspcntr = REG_READ(map->cntr);
dspcntr           488 drivers/gpu/drm/gma500/oaktrail_crtc.c 	dspcntr |= DISPPLANE_GAMMA_ENABLE;
dspcntr           491 drivers/gpu/drm/gma500/oaktrail_crtc.c 		dspcntr |= DISPPLANE_SEL_PIPE_A;
dspcntr           493 drivers/gpu/drm/gma500/oaktrail_crtc.c 		dspcntr |= DISPPLANE_SEL_PIPE_B;
dspcntr           579 drivers/gpu/drm/gma500/oaktrail_crtc.c 		REG_WRITE_WITH_AUX(map->cntr, dspcntr, i);
dspcntr           599 drivers/gpu/drm/gma500/oaktrail_crtc.c 	u32 dspcntr;
dspcntr           616 drivers/gpu/drm/gma500/oaktrail_crtc.c 	dspcntr = REG_READ(map->cntr);
dspcntr           617 drivers/gpu/drm/gma500/oaktrail_crtc.c 	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
dspcntr           621 drivers/gpu/drm/gma500/oaktrail_crtc.c 		dspcntr |= DISPPLANE_8BPP;
dspcntr           625 drivers/gpu/drm/gma500/oaktrail_crtc.c 			dspcntr |= DISPPLANE_15_16BPP;
dspcntr           627 drivers/gpu/drm/gma500/oaktrail_crtc.c 			dspcntr |= DISPPLANE_16BPP;
dspcntr           631 drivers/gpu/drm/gma500/oaktrail_crtc.c 		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
dspcntr           638 drivers/gpu/drm/gma500/oaktrail_crtc.c 	REG_WRITE(map->cntr, dspcntr);
dspcntr           283 drivers/gpu/drm/gma500/oaktrail_hdmi.c 	u32 dspcntr, pipeconf, dpll, temp;
dspcntr           357 drivers/gpu/drm/gma500/oaktrail_hdmi.c 	dspcntr = REG_READ(dspcntr_reg);
dspcntr           358 drivers/gpu/drm/gma500/oaktrail_hdmi.c 	dspcntr |= DISPPLANE_GAMMA_ENABLE;
dspcntr           359 drivers/gpu/drm/gma500/oaktrail_hdmi.c 	dspcntr |= DISPPLANE_SEL_PIPE_B;
dspcntr           360 drivers/gpu/drm/gma500/oaktrail_hdmi.c 	dspcntr |= DISPLAY_PLANE_ENABLE;
dspcntr           373 drivers/gpu/drm/gma500/oaktrail_hdmi.c 	REG_WRITE(dspcntr_reg, dspcntr);
dspcntr           592 drivers/gpu/drm/gma500/psb_drv.h 	u32 dspcntr[3];
dspcntr           105 drivers/gpu/drm/gma500/psb_intel_display.c 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
dspcntr           194 drivers/gpu/drm/gma500/psb_intel_display.c 	dspcntr = DISPPLANE_GAMMA_ENABLE;
dspcntr           197 drivers/gpu/drm/gma500/psb_intel_display.c 		dspcntr |= DISPPLANE_SEL_PIPE_A;
dspcntr           199 drivers/gpu/drm/gma500/psb_intel_display.c 		dspcntr |= DISPPLANE_SEL_PIPE_B;
dspcntr           201 drivers/gpu/drm/gma500/psb_intel_display.c 	dspcntr |= DISPLAY_PLANE_ENABLE;
dspcntr           286 drivers/gpu/drm/gma500/psb_intel_display.c 	REG_WRITE(map->cntr, dspcntr);
dspcntr          3599 drivers/gpu/drm/i915/display/intel_display.c 	u32 dspcntr = 0;
dspcntr          3602 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_GAMMA_ENABLE;
dspcntr          3605 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
dspcntr          3608 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
dspcntr          3610 drivers/gpu/drm/i915/display/intel_display.c 	return dspcntr;
dspcntr          3620 drivers/gpu/drm/i915/display/intel_display.c 	u32 dspcntr;
dspcntr          3622 drivers/gpu/drm/i915/display/intel_display.c 	dspcntr = DISPLAY_PLANE_ENABLE;
dspcntr          3626 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
dspcntr          3630 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_8BPP;
dspcntr          3633 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_BGRX555;
dspcntr          3636 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_BGRX565;
dspcntr          3639 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_BGRX888;
dspcntr          3642 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_RGBX888;
dspcntr          3645 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_BGRX101010;
dspcntr          3648 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_RGBX101010;
dspcntr          3657 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_TILED;
dspcntr          3660 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_ROTATE_180;
dspcntr          3663 drivers/gpu/drm/i915/display/intel_display.c 		dspcntr |= DISPPLANE_MIRROR;
dspcntr          3665 drivers/gpu/drm/i915/display/intel_display.c 	return dspcntr;
dspcntr          3790 drivers/gpu/drm/i915/display/intel_display.c 	u32 dspcntr;
dspcntr          3792 drivers/gpu/drm/i915/display/intel_display.c 	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
dspcntr          3833 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
dspcntr          3852 drivers/gpu/drm/i915/display/intel_display.c 	u32 dspcntr;
dspcntr          3864 drivers/gpu/drm/i915/display/intel_display.c 	dspcntr = i9xx_plane_ctl_crtc(crtc_state);
dspcntr          3868 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
dspcntr           769 drivers/video/fbdev/vermilion/vermilion.c 	u32 dspcntr;
dspcntr           795 drivers/video/fbdev/vermilion/vermilion.c 	dspcntr = VML_GFX_ENABLE | VML_GFX_GAMMABYPASS;
dspcntr           809 drivers/video/fbdev/vermilion/vermilion.c 		dspcntr |= VML_GFX_ARGB1555;
dspcntr           813 drivers/video/fbdev/vermilion/vermilion.c 			dspcntr |= VML_GFX_ARGB8888 | VML_GFX_ALPHAMULT;
dspcntr           815 drivers/video/fbdev/vermilion/vermilion.c 			dspcntr |= VML_GFX_RGB0888;
dspcntr           852 drivers/video/fbdev/vermilion/vermilion.c 	VML_WRITE32(par, VML_DSPCCNTR, dspcntr);