dsisr 468 arch/powerpc/include/asm/book3s/64/mmu-hash.h unsigned long dsisr); dsisr 17 arch/powerpc/include/asm/copro.h unsigned long dsisr, vm_fault_t *flt); dsisr 92 arch/powerpc/include/asm/disassemble.h unsigned dsisr; dsisr 96 arch/powerpc/include/asm/disassemble.h dsisr = (instr & 0x03ff0000) >> 16; dsisr 100 arch/powerpc/include/asm/disassemble.h dsisr |= (instr & 0x00000006) << 14; dsisr 102 arch/powerpc/include/asm/disassemble.h dsisr |= (instr & 0x00000040) << 8; dsisr 104 arch/powerpc/include/asm/disassemble.h dsisr |= (instr & 0x00000780) << 3; dsisr 107 arch/powerpc/include/asm/disassemble.h dsisr |= (instr & 0x04000000) >> 12; dsisr 109 arch/powerpc/include/asm/disassemble.h dsisr |= (instr & 0x78000000) >> 17; dsisr 112 arch/powerpc/include/asm/disassemble.h dsisr |= (instr & 0x00000003) << 18; dsisr 115 arch/powerpc/include/asm/disassemble.h return dsisr; dsisr 179 arch/powerpc/include/asm/kvm_book3s.h unsigned long ea, unsigned long dsisr); dsisr 981 arch/powerpc/include/asm/kvm_ppc.h SHARED_WRAPPER(dsisr, 32) dsisr 22 arch/powerpc/include/asm/pnv-ocxl.h extern void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar, dsisr 24 arch/powerpc/include/asm/pnv-ocxl.h extern int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr, dsisr 46 arch/powerpc/include/asm/ptrace.h unsigned long dsisr; dsisr 221 arch/powerpc/include/asm/ptrace.h #define MAX_REG_OFFSET (offsetof(struct pt_regs, dsisr)) dsisr 29 arch/powerpc/include/asm/spu_priv1.h void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr); dsisr 99 arch/powerpc/include/asm/spu_priv1.h spu_mfc_dsisr_set (struct spu *spu, u64 dsisr) dsisr 101 arch/powerpc/include/asm/spu_priv1.h spu_priv1_ops->mfc_dsisr_set(spu, dsisr); dsisr 49 arch/powerpc/include/uapi/asm/kvm_para.h __u32 dsisr; dsisr 56 arch/powerpc/include/uapi/asm/ptrace.h unsigned long dsisr; /* on 4xx/Book-E used for ESR */ dsisr 317 arch/powerpc/kernel/asm-offsets.c STACK_PT_REGS_OFFSET(_DSISR, dsisr); dsisr 329 arch/powerpc/kernel/asm-offsets.c STACK_PT_REGS_OFFSET(_ESR, dsisr); dsisr 510 arch/powerpc/kernel/asm-offsets.c OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); dsisr 455 arch/powerpc/kernel/kvm.c kvm_patch_ins_lwz(inst, magic_var(dsisr), inst_rt); dsisr 558 arch/powerpc/kernel/kvm.c kvm_patch_ins_stw(inst, magic_var(dsisr), inst_rt); dsisr 485 arch/powerpc/kernel/mce_power.c uint64_t dsisr = regs->dsisr; dsisr 493 arch/powerpc/kernel/mce_power.c if (!(dsisr & table[i].dsisr_value)) dsisr 632 arch/powerpc/kernel/mce_power.c regs->dsisr &= 0x0000ffff; dsisr 654 arch/powerpc/kernel/mce_power.c if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000) dsisr 27 arch/powerpc/kernel/ppc32.h unsigned int dsisr; dsisr 1406 arch/powerpc/kernel/process.c pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); dsisr 1408 arch/powerpc/kernel/process.c pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); dsisr 123 arch/powerpc/kernel/ptrace.c REG_OFFSET_NAME(dsisr), dsisr 3395 arch/powerpc/kernel/ptrace.c BUILD_BUG_ON(offsetof(struct pt_regs, dsisr) != dsisr 3396 arch/powerpc/kernel/ptrace.c offsetof(struct user_pt_regs, dsisr)); dsisr 356 arch/powerpc/kernel/signal_64.c err |= __get_user(regs->dsisr, &sc->gp_regs[PT_DSISR]); dsisr 481 arch/powerpc/kernel/signal_64.c err |= __get_user(regs->dsisr, &sc->gp_regs[PT_DSISR]); dsisr 581 arch/powerpc/kernel/traps.c #define get_reason(regs) ((regs)->dsisr) dsisr 492 arch/powerpc/kvm/book3s_64_mmu_hv.c unsigned long ea, unsigned long dsisr) dsisr 513 arch/powerpc/kvm/book3s_64_mmu_hv.c return kvmppc_book3s_radix_page_fault(run, vcpu, ea, dsisr); dsisr 534 arch/powerpc/kvm/book3s_64_mmu_hv.c dsisr & DSISR_ISSTORE); dsisr 565 arch/powerpc/kvm/book3s_64_mmu_hv.c trace_kvm_page_fault_enter(vcpu, hpte, memslot, ea, dsisr); dsisr 570 arch/powerpc/kvm/book3s_64_mmu_hv.c dsisr & DSISR_ISSTORE); dsisr 588 arch/powerpc/kvm/book3s_64_mmu_hv.c writing = (dsisr & DSISR_ISSTORE) != 0; dsisr 890 arch/powerpc/kvm/book3s_64_mmu_radix.c unsigned long ea, unsigned long dsisr) dsisr 896 arch/powerpc/kvm/book3s_64_mmu_radix.c bool writing = !!(dsisr & DSISR_ISSTORE); dsisr 900 arch/powerpc/kvm/book3s_64_mmu_radix.c if (dsisr & DSISR_UNSUPP_MMU) { dsisr 904 arch/powerpc/kvm/book3s_64_mmu_radix.c if (dsisr & DSISR_BADACCESS) { dsisr 906 arch/powerpc/kvm/book3s_64_mmu_radix.c pr_err("KVM: Got radix HV page fault with DSISR=%lx\n", dsisr); dsisr 907 arch/powerpc/kvm/book3s_64_mmu_radix.c kvmppc_core_queue_data_storage(vcpu, ea, dsisr); dsisr 915 arch/powerpc/kvm/book3s_64_mmu_radix.c if (!(dsisr & DSISR_PRTABLE_FAULT)) dsisr 923 arch/powerpc/kvm/book3s_64_mmu_radix.c if (dsisr & (DSISR_PRTABLE_FAULT | DSISR_BADACCESS | dsisr 929 arch/powerpc/kvm/book3s_64_mmu_radix.c kvmppc_core_queue_data_storage(vcpu, ea, dsisr); dsisr 946 arch/powerpc/kvm/book3s_64_mmu_radix.c if (dsisr & DSISR_SET_RC) { dsisr 950 arch/powerpc/kvm/book3s_64_mmu_radix.c dsisr &= ~DSISR_SET_RC; dsisr 953 arch/powerpc/kvm/book3s_64_mmu_radix.c if (!(dsisr & (DSISR_BAD_FAULT_64S | DSISR_NOHPTE | dsisr 457 arch/powerpc/kvm/book3s_emulate.c u32 dsisr; dsisr 474 arch/powerpc/kvm/book3s_emulate.c dsisr = DSISR_ISSTORE; dsisr 476 arch/powerpc/kvm/book3s_emulate.c dsisr |= DSISR_NOHPTE; dsisr 478 arch/powerpc/kvm/book3s_emulate.c dsisr |= DSISR_PROTFAULT; dsisr 480 arch/powerpc/kvm/book3s_emulate.c kvmppc_set_dsisr(vcpu, dsisr); dsisr 481 arch/powerpc/kvm/book3s_emulate.c vcpu->arch.fault_dsisr = dsisr; dsisr 434 arch/powerpc/kvm/book3s_hv.c vcpu->arch.regs.ccr, vcpu->arch.regs.xer, vcpu->arch.shregs.dsisr); dsisr 3579 arch/powerpc/kvm/book3s_hv.c mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr); dsisr 3618 arch/powerpc/kvm/book3s_hv.c vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR); dsisr 1135 arch/powerpc/kvm/book3s_hv_nested.c unsigned long n_gpa, unsigned long dsisr, dsisr 1138 arch/powerpc/kvm/book3s_hv_nested.c u64 fault_addr, flags = dsisr & DSISR_ISSTORE; dsisr 1163 arch/powerpc/kvm/book3s_hv_nested.c if (dsisr & DSISR_ISSTORE) { dsisr 1199 arch/powerpc/kvm/book3s_hv_nested.c unsigned long dsisr) dsisr 1202 arch/powerpc/kvm/book3s_hv_nested.c bool writing = !!(dsisr & DSISR_ISSTORE); dsisr 1270 arch/powerpc/kvm/book3s_hv_nested.c unsigned long dsisr = vcpu->arch.fault_dsisr; dsisr 1275 arch/powerpc/kvm/book3s_hv_nested.c bool writing = !!(dsisr & DSISR_ISSTORE); dsisr 1288 arch/powerpc/kvm/book3s_hv_nested.c if (!(dsisr & DSISR_PRTABLE_FAULT)) dsisr 1290 arch/powerpc/kvm/book3s_hv_nested.c ret = kvmhv_translate_addr_nested(vcpu, gp, n_gpa, dsisr, &gpte); dsisr 1298 arch/powerpc/kvm/book3s_hv_nested.c (dsisr & (DSISR_PROTFAULT | DSISR_BADACCESS | DSISR_NOEXEC_OR_G | dsisr 1305 arch/powerpc/kvm/book3s_hv_nested.c if (dsisr & DSISR_SET_RC) { dsisr 1306 arch/powerpc/kvm/book3s_hv_nested.c ret = kvmhv_handle_nested_set_rc(vcpu, gp, n_gpa, gpte, dsisr); dsisr 1311 arch/powerpc/kvm/book3s_hv_nested.c dsisr &= ~DSISR_SET_RC; dsisr 1312 arch/powerpc/kvm/book3s_hv_nested.c if (!(dsisr & (DSISR_BAD_FAULT_64S | DSISR_NOHPTE | dsisr 1337 arch/powerpc/kvm/book3s_hv_nested.c if (dsisr & (DSISR_PRTABLE_FAULT | DSISR_BADACCESS)) { dsisr 1339 arch/powerpc/kvm/book3s_hv_nested.c kvmppc_core_queue_data_storage(vcpu, ea, dsisr); dsisr 76 arch/powerpc/kvm/book3s_hv_ras.c unsigned long dsisr = vcpu->arch.shregs.dsisr; dsisr 78 arch/powerpc/kvm/book3s_hv_ras.c if (dsisr & (DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI | dsisr 82 arch/powerpc/kvm/book3s_hv_ras.c dsisr &= ~(DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI | dsisr 85 arch/powerpc/kvm/book3s_hv_ras.c if (dsisr & DSISR_MC_TLB_MULTI) { dsisr 87 arch/powerpc/kvm/book3s_hv_ras.c dsisr &= ~DSISR_MC_TLB_MULTI; dsisr 90 arch/powerpc/kvm/book3s_hv_ras.c if (dsisr & 0xffffffffUL) dsisr 157 arch/powerpc/kvm/book3s_paired_singles.c u32 dsisr; dsisr 165 arch/powerpc/kvm/book3s_paired_singles.c dsisr = kvmppc_set_field(0, 33, 33, 1); dsisr 167 arch/powerpc/kvm/book3s_paired_singles.c dsisr = kvmppc_set_field(dsisr, 38, 38, 1); dsisr 168 arch/powerpc/kvm/book3s_paired_singles.c kvmppc_set_dsisr(vcpu, dsisr); dsisr 1368 arch/powerpc/kvm/book3s_pr.c u32 dsisr; dsisr 1371 arch/powerpc/kvm/book3s_pr.c dsisr = kvmppc_alignment_dsisr(vcpu, last_inst); dsisr 1374 arch/powerpc/kvm/book3s_pr.c kvmppc_set_dsisr(vcpu, dsisr); dsisr 153 arch/powerpc/kvm/powerpc.c shared->dsisr = swab32(shared->dsisr); dsisr 275 arch/powerpc/kvm/trace_hv.h unsigned long dsisr), dsisr 277 arch/powerpc/kvm/trace_hv.h TP_ARGS(vcpu, hptep, memslot, ea, dsisr), dsisr 287 arch/powerpc/kvm/trace_hv.h __field(u32, dsisr) dsisr 296 arch/powerpc/kvm/trace_hv.h __entry->dsisr = dsisr; dsisr 304 arch/powerpc/kvm/trace_hv.h __entry->ea, __entry->dsisr, dsisr 1447 arch/powerpc/mm/book3s64/hash_utils.c unsigned long dsisr) dsisr 1456 arch/powerpc/mm/book3s64/hash_utils.c if (dsisr & DSISR_NOHPTE) dsisr 1463 arch/powerpc/mm/book3s64/hash_utils.c int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr, dsisr 1474 arch/powerpc/mm/book3s64/hash_utils.c if (dsisr & DSISR_NOHPTE) dsisr 1477 arch/powerpc/mm/book3s64/hash_utils.c if (dsisr & DSISR_ISSTORE) dsisr 24 arch/powerpc/mm/copro_fault.c unsigned long dsisr, vm_fault_t *flt) dsisr 49 arch/powerpc/mm/copro_fault.c is_write = dsisr & DSISR_ISSTORE; dsisr 63 arch/powerpc/mm/copro_fault.c WARN_ON_ONCE(dsisr & DSISR_PROTFAULT); dsisr 163 arch/powerpc/perf/core-book3s.c unsigned long mmcra = regs->dsisr; dsisr 184 arch/powerpc/perf/core-book3s.c unsigned long mmcra = regs->dsisr; dsisr 222 arch/powerpc/perf/core-book3s.c return !!(regs->dsisr & sihv); dsisr 235 arch/powerpc/perf/core-book3s.c return !!(regs->dsisr & sipr); dsisr 290 arch/powerpc/perf/core-book3s.c regs->dsisr = mmcra; dsisr 346 arch/powerpc/perf/core-book3s.c unsigned long mmcra = regs->dsisr; dsisr 67 arch/powerpc/perf/perf_regs.c PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr), dsisr 69 arch/powerpc/perf/perf_regs.c PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr), dsisr 13 arch/powerpc/platforms/44x/machine_check.c unsigned long reason = regs->dsisr; dsisr 50 arch/powerpc/platforms/44x/machine_check.c unsigned long reason = regs->dsisr; dsisr 13 arch/powerpc/platforms/4xx/machine_check.c unsigned long reason = regs->dsisr; dsisr 172 arch/powerpc/platforms/cell/spu_base.c unsigned long trap, unsigned long dsisr); //XXX dsisr 173 arch/powerpc/platforms/cell/spu_base.c static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr) dsisr 177 arch/powerpc/platforms/cell/spu_base.c pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea); dsisr 183 arch/powerpc/platforms/cell/spu_base.c if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) && dsisr 189 arch/powerpc/platforms/cell/spu_base.c 0x300, dsisr); dsisr 199 arch/powerpc/platforms/cell/spu_base.c spu->class_1_dsisr = dsisr; dsisr 307 arch/powerpc/platforms/cell/spu_base.c unsigned long stat, mask, dar, dsisr; dsisr 316 arch/powerpc/platforms/cell/spu_base.c dsisr = spu_mfc_dsisr_get(spu); dsisr 322 arch/powerpc/platforms/cell/spu_base.c dar, dsisr); dsisr 328 arch/powerpc/platforms/cell/spu_base.c __spu_trap_data_map(spu, dar, dsisr); dsisr 91 arch/powerpc/platforms/cell/spu_priv1_mmio.c static void mfc_dsisr_set(struct spu *spu, u64 dsisr) dsisr 93 arch/powerpc/platforms/cell/spu_priv1_mmio.c out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); dsisr 88 arch/powerpc/platforms/cell/spufs/fault.c u64 ea, dsisr, access; dsisr 103 arch/powerpc/platforms/cell/spufs/fault.c dsisr = ctx->csa.class_1_dsisr; dsisr 105 arch/powerpc/platforms/cell/spufs/fault.c if (!(dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))) dsisr 111 arch/powerpc/platforms/cell/spufs/fault.c dsisr, ctx->state); dsisr 121 arch/powerpc/platforms/cell/spufs/fault.c access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_WRITE : 0UL; dsisr 123 arch/powerpc/platforms/cell/spufs/fault.c ret = hash_page(ea, access, 0x300, dsisr); dsisr 128 arch/powerpc/platforms/cell/spufs/fault.c ret = copro_handle_mm_fault(current->mm, ea, dsisr, &flt); dsisr 51 arch/powerpc/platforms/cell/spufs/run.c u64 dsisr; dsisr 72 arch/powerpc/platforms/cell/spufs/run.c dsisr = ctx->csa.class_1_dsisr; dsisr 73 arch/powerpc/platforms/cell/spufs/run.c if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)) dsisr 320 arch/powerpc/platforms/pasemi/setup.c unsigned long srr0, srr1, dsisr; dsisr 334 arch/powerpc/platforms/pasemi/setup.c dsisr = mfspr(SPRN_DSISR); dsisr 337 arch/powerpc/platforms/pasemi/setup.c pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); dsisr 349 arch/powerpc/platforms/pasemi/setup.c if (dsisr & 0x8000) dsisr 351 arch/powerpc/platforms/pasemi/setup.c if (dsisr & 0x4000) dsisr 353 arch/powerpc/platforms/pasemi/setup.c if (dsisr & 0x2000) { dsisr 357 arch/powerpc/platforms/pasemi/setup.c if (dsisr & 0x1000) dsisr 359 arch/powerpc/platforms/pasemi/setup.c if (dsisr & 0x800) dsisr 361 arch/powerpc/platforms/pasemi/setup.c if (dsisr & 0x400) dsisr 386 arch/powerpc/platforms/powernv/ocxl.c void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar, dsisr 389 arch/powerpc/platforms/powernv/ocxl.c iounmap(dsisr); dsisr 396 arch/powerpc/platforms/powernv/ocxl.c int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr, dsisr 425 arch/powerpc/platforms/powernv/ocxl.c *dsisr = regs[0]; dsisr 110 arch/powerpc/platforms/powernv/opal-fadump.h regs->dsisr = reg_val; dsisr 517 arch/powerpc/platforms/ps3/spu.c static void mfc_dsisr_set(struct spu *spu, u64 dsisr) dsisr 272 arch/powerpc/platforms/pseries/rtas-fadump.c regs->dsisr = (unsigned long)reg_val; dsisr 1705 arch/powerpc/xmon/xmon.c printf(" dsisr: %lx\n", fp->dsisr); dsisr 1780 arch/powerpc/xmon/xmon.c printf("dar = "REG" dsisr = %.8lx\n", fp->dar, fp->dsisr); dsisr 585 drivers/misc/cxl/cxl.h u64 dsisr; dsisr 970 drivers/misc/cxl/cxl.h int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar); dsisr 997 drivers/misc/cxl/cxl.h u64 dsisr; dsisr 1075 drivers/misc/cxl/cxl.h u64 dsisr, u64 errstat); dsisr 106 drivers/misc/cxl/fault.c ctx->fault_dsisr = ctx->dsisr; dsisr 131 drivers/misc/cxl/fault.c int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar) dsisr 153 drivers/misc/cxl/fault.c if ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) { dsisr 164 drivers/misc/cxl/fault.c if (dsisr & CXL_PSL_DSISR_An_S) dsisr 170 drivers/misc/cxl/fault.c if (dsisr & DSISR_NOHPTE) dsisr 182 drivers/misc/cxl/fault.c u64 dsisr, u64 dar) dsisr 184 drivers/misc/cxl/fault.c trace_cxl_pte_miss(ctx, dsisr, dar); dsisr 186 drivers/misc/cxl/fault.c if (cxl_handle_mm_fault(mm, dsisr, dar)) { dsisr 209 drivers/misc/cxl/fault.c static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr) dsisr 211 drivers/misc/cxl/fault.c if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS))) dsisr 217 drivers/misc/cxl/fault.c static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr) dsisr 219 drivers/misc/cxl/fault.c if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM)) dsisr 232 drivers/misc/cxl/fault.c u64 dsisr = ctx->dsisr; dsisr 237 drivers/misc/cxl/fault.c if (cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An) != dsisr || dsisr 256 drivers/misc/cxl/fault.c "DSISR: %#llx DAR: %#llx\n", ctx->pe, dsisr, dar); dsisr 272 drivers/misc/cxl/fault.c if (cxl_is_segment_miss(ctx, dsisr)) dsisr 274 drivers/misc/cxl/fault.c else if (cxl_is_page_fault(ctx, dsisr)) dsisr 275 drivers/misc/cxl/fault.c cxl_handle_page_fault(ctx, mm, dsisr, dar); dsisr 492 drivers/misc/cxl/file.c event.fault.dsisr = ctx->fault_dsisr; dsisr 55 drivers/misc/cxl/guest.c static irqreturn_t guest_handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr, dsisr 195 drivers/misc/cxl/guest.c u64 serr, afu_error, dsisr; dsisr 203 drivers/misc/cxl/guest.c dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); dsisr 206 drivers/misc/cxl/guest.c dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); dsisr 413 drivers/misc/cxl/hcalls.c info->dsisr, info->dar, info->dsr, info->reserved, dsisr 25 drivers/misc/cxl/irq.c static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar) dsisr 27 drivers/misc/cxl/irq.c ctx->dsisr = dsisr; dsisr 35 drivers/misc/cxl/irq.c u64 dsisr, dar; dsisr 37 drivers/misc/cxl/irq.c dsisr = irq_info->dsisr; dsisr 40 drivers/misc/cxl/irq.c trace_cxl_psl9_irq(ctx, irq, dsisr, dar); dsisr 42 drivers/misc/cxl/irq.c pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); dsisr 44 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL9_DSISR_An_TF) { dsisr 46 drivers/misc/cxl/irq.c return schedule_cxl_fault(ctx, dsisr, dar); dsisr 49 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL9_DSISR_An_PE) dsisr 50 drivers/misc/cxl/irq.c return cxl_ops->handle_psl_slice_error(ctx, dsisr, dsisr 52 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL9_DSISR_An_AE) { dsisr 77 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL9_DSISR_An_OC) dsisr 86 drivers/misc/cxl/irq.c u64 dsisr, dar; dsisr 88 drivers/misc/cxl/irq.c dsisr = irq_info->dsisr; dsisr 91 drivers/misc/cxl/irq.c trace_cxl_psl_irq(ctx, irq, dsisr, dar); dsisr 93 drivers/misc/cxl/irq.c pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); dsisr 95 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_DS) { dsisr 107 drivers/misc/cxl/irq.c return schedule_cxl_fault(ctx, dsisr, dar); dsisr 110 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_M) dsisr 112 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_P) dsisr 114 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_A) dsisr 116 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_S) dsisr 118 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_K) dsisr 121 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_DM) { dsisr 128 drivers/misc/cxl/irq.c return schedule_cxl_fault(ctx, dsisr, dar); dsisr 130 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_ST) dsisr 132 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_UR) dsisr 134 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_PE) dsisr 135 drivers/misc/cxl/irq.c return cxl_ops->handle_psl_slice_error(ctx, dsisr, dsisr 137 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_AE) { dsisr 163 drivers/misc/cxl/irq.c if (dsisr & CXL_PSL_DSISR_An_OC) dsisr 134 drivers/misc/cxl/native.c u64 dsisr, dar; dsisr 176 drivers/misc/cxl/native.c dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); dsisr 178 drivers/misc/cxl/native.c PSL_CNTL, dsisr); dsisr 180 drivers/misc/cxl/native.c if (dsisr & trans_fault) { dsisr 183 drivers/misc/cxl/native.c dsisr, dar); dsisr 185 drivers/misc/cxl/native.c } else if (dsisr) { dsisr 187 drivers/misc/cxl/native.c dsisr); dsisr 1092 drivers/misc/cxl/native.c info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); dsisr 1136 drivers/misc/cxl/native.c u64 dsisr, u64 errstat) dsisr 1152 drivers/misc/cxl/native.c static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr) dsisr 1154 drivers/misc/cxl/native.c if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_TRANS)) dsisr 1157 drivers/misc/cxl/native.c if ((cxl_is_power9()) && (dsisr & CXL_PSL9_DSISR_An_TF)) dsisr 1165 drivers/misc/cxl/native.c if (cxl_is_translation_fault(afu, irq_info->dsisr)) dsisr 1209 drivers/misc/cxl/native.c " with outstanding transactions?)\n", ph, irq_info.dsisr, dsisr 1218 drivers/misc/cxl/native.c u64 dsisr; dsisr 1230 drivers/misc/cxl/native.c dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); dsisr 1232 drivers/misc/cxl/native.c ((dsisr & CXL_PSL_DSISR_PENDING) == 0)) dsisr 1235 drivers/misc/cxl/native.c ((dsisr & CXL_PSL9_DSISR_PENDING) == 0)) dsisr 1245 drivers/misc/cxl/native.c " DSISR %016llx!\n", ph, dsisr); dsisr 1252 drivers/misc/cxl/native.c u64 errstat, serr, afu_error, dsisr; dsisr 1261 drivers/misc/cxl/native.c dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); dsisr 1272 drivers/misc/cxl/native.c dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); dsisr 1439 drivers/misc/cxl/native.c u64 dsisr; dsisr 1444 drivers/misc/cxl/native.c dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); dsisr 1445 drivers/misc/cxl/native.c cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); dsisr 163 drivers/misc/cxl/trace.h TP_PROTO(struct cxl_context *ctx, int irq, u64 dsisr, u64 dar), dsisr 165 drivers/misc/cxl/trace.h TP_ARGS(ctx, irq, dsisr, dar), dsisr 172 drivers/misc/cxl/trace.h __field(u64, dsisr) dsisr 181 drivers/misc/cxl/trace.h __entry->dsisr = dsisr; dsisr 190 drivers/misc/cxl/trace.h __entry->dsisr, dsisr 191 drivers/misc/cxl/trace.h dsisr_psl9_flags(__entry->dsisr), dsisr 197 drivers/misc/cxl/trace.h TP_PROTO(struct cxl_context *ctx, int irq, u64 dsisr, u64 dar), dsisr 199 drivers/misc/cxl/trace.h TP_ARGS(ctx, irq, dsisr, dar), dsisr 206 drivers/misc/cxl/trace.h __field(u64, dsisr) dsisr 215 drivers/misc/cxl/trace.h __entry->dsisr = dsisr; dsisr 224 drivers/misc/cxl/trace.h __print_flags(__entry->dsisr, "|", DSISR_FLAGS), dsisr 317 drivers/misc/cxl/trace.h TP_PROTO(struct cxl_context *ctx, u64 dsisr, u64 dar), dsisr 319 drivers/misc/cxl/trace.h TP_ARGS(ctx, dsisr, dar), dsisr 325 drivers/misc/cxl/trace.h __field(u64, dsisr) dsisr 333 drivers/misc/cxl/trace.h __entry->dsisr = dsisr; dsisr 341 drivers/misc/cxl/trace.h __print_flags(__entry->dsisr, "|", DSISR_FLAGS), dsisr 56 drivers/misc/ocxl/context.c static void xsl_fault_error(void *data, u64 addr, u64 dsisr) dsisr 62 drivers/misc/ocxl/context.c ctx->xsl_error.dsisr = dsisr; dsisr 369 drivers/misc/ocxl/file.c body.dsisr = ctx->xsl_error.dsisr; dsisr 373 drivers/misc/ocxl/file.c ctx->xsl_error.dsisr = 0; dsisr 39 drivers/misc/ocxl/link.c void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr); dsisr 65 drivers/misc/ocxl/link.c u64 dsisr; dsisr 99 drivers/misc/ocxl/link.c static void read_irq(struct spa *spa, u64 *dsisr, u64 *dar, u64 *pe) dsisr 103 drivers/misc/ocxl/link.c *dsisr = in_be64(spa->reg_dsisr); dsisr 123 drivers/misc/ocxl/link.c spa->xsl_fault.dsisr, spa->xsl_fault.dar, reg); dsisr 143 drivers/misc/ocxl/link.c rc = copro_handle_mm_fault(fault->pe_data.mm, fault->dar, fault->dsisr, dsisr 150 drivers/misc/ocxl/link.c fault->dar, fault->dsisr); dsisr 163 drivers/misc/ocxl/link.c if (fault->dsisr & SPA_XSL_S) dsisr 184 drivers/misc/ocxl/link.c u64 dsisr, dar, pe_handle; dsisr 190 drivers/misc/ocxl/link.c read_irq(spa, &dsisr, &dar, &pe_handle); dsisr 191 drivers/misc/ocxl/link.c trace_ocxl_fault(spa->spa_mem, pe_handle, dsisr, dar, -1); dsisr 203 drivers/misc/ocxl/link.c if (!(dsisr & SPA_XSL_TF)) { dsisr 204 drivers/misc/ocxl/link.c WARN(1, "Invalid xsl interrupt fault register %#llx\n", dsisr); dsisr 243 drivers/misc/ocxl/link.c spa->xsl_fault.dsisr = dsisr; dsisr 497 drivers/misc/ocxl/link.c void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr), dsisr 66 drivers/misc/ocxl/ocxl_internal.h u64 dsisr; // the value of the dsisr register dsisr 71 drivers/misc/ocxl/trace.h TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc), dsisr 72 drivers/misc/ocxl/trace.h TP_ARGS(spa, pe, dsisr, dar, tfc), dsisr 77 drivers/misc/ocxl/trace.h __field(u64, dsisr) dsisr 85 drivers/misc/ocxl/trace.h __entry->dsisr = dsisr; dsisr 93 drivers/misc/ocxl/trace.h __entry->dsisr, dsisr 100 drivers/misc/ocxl/trace.h TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc), dsisr 101 drivers/misc/ocxl/trace.h TP_ARGS(spa, pe, dsisr, dar, tfc) dsisr 105 drivers/misc/ocxl/trace.h TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc), dsisr 106 drivers/misc/ocxl/trace.h TP_ARGS(spa, pe, dsisr, dar, tfc) dsisr 307 drivers/scsi/cxlflash/ocxl_hw.c static void ocxlflash_xsl_fault(void *data, u64 addr, u64 dsisr) dsisr 313 drivers/scsi/cxlflash/ocxl_hw.c ctx->fault_dsisr = dsisr; dsisr 1078 drivers/scsi/cxlflash/ocxl_hw.c event.fault.dsisr = ctx->fault_dsisr; dsisr 471 include/misc/ocxl.h void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr), dsisr 120 include/uapi/misc/cxl.h __u64 dsisr; dsisr 23 include/uapi/misc/ocxl.h __u64 dsisr; dsisr 25 tools/perf/arch/powerpc/include/dwarf-regs-table.h REG_DWARFNUM_NAME(dsisr, 118), dsisr 72 tools/perf/arch/powerpc/util/dwarf-regs.c REG_DWARFNUM_NAME(dsisr, 118), dsisr 55 tools/perf/arch/powerpc/util/perf_regs.c SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),