dsiclk_sel 47 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u32 dsiclk_sel; /* Mux configuration (see diagram) */ dsiclk_sel 218 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ dsiclk_sel 523 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */