dsc_slice_width   363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			s.dsc_slice_width,
dsc_slice_width   159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
dsc_slice_width   191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 					uint32_t dsc_slice_width)
dsc_slice_width   202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
dsc_slice_width    93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 					uint32_t dsc_slice_width);
dsc_slice_width   279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 					uint32_t dsc_slice_width)
dsc_slice_width   285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 			DP_DSC_SLICE_WIDTH, dsc_slice_width);
dsc_slice_width   353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
dsc_slice_width    53 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 	uint32_t dsc_slice_width;
dsc_slice_width   115 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 	uint32_t dsc_slice_width;
dsc_slice_width   225 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 			uint32_t dsc_slice_width);
dsc_slice_width   273 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 			       uint32_t dsc_slice_width);