dsc_sink_caps      45 drivers/gpu/drm/amd/display/dc/dc_dsc.h 		struct dsc_dec_dpcd_caps *dsc_sink_caps);
dsc_sink_caps      51 drivers/gpu/drm/amd/display/dc/dc_dsc.h 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
dsc_sink_caps      57 drivers/gpu/drm/amd/display/dc/dc_dsc.h 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
dsc_sink_caps     197 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	const struct dsc_dec_dpcd_caps *dsc_sink_caps,
dsc_sink_caps     207 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->dsc_version = min(dsc_sink_caps->dsc_version, dsc_enc_caps->dsc_version);
dsc_sink_caps     211 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_1 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_1 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;
dsc_sink_caps     212 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_2 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_2 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;
dsc_sink_caps     213 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_4 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;
dsc_sink_caps     214 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->slice_caps.bits.NUM_SLICES_8 = dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;
dsc_sink_caps     218 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->lb_bit_depth = min(dsc_sink_caps->lb_bit_depth, dsc_enc_caps->lb_bit_depth);
dsc_sink_caps     222 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->is_block_pred_supported = dsc_sink_caps->is_block_pred_supported && dsc_enc_caps->is_block_pred_supported;
dsc_sink_caps     224 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->color_formats.raw = dsc_sink_caps->color_formats.raw & dsc_enc_caps->color_formats.raw;
dsc_sink_caps     228 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->color_depth.raw = dsc_sink_caps->color_depth.raw & dsc_enc_caps->color_depth.raw;
dsc_sink_caps     242 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	total_sink_throughput = max_slices * dsc_sink_caps->throughput_mode_0_mps;
dsc_sink_caps     244 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		total_sink_throughput = max_slices * dsc_sink_caps->throughput_mode_1_mps;
dsc_sink_caps     248 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->max_slice_width = min(dsc_sink_caps->max_slice_width, dsc_enc_caps->max_slice_width);
dsc_sink_caps     252 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->bpp_increment_div = min(dsc_sink_caps->bpp_increment_div, dsc_enc_caps->bpp_increment_div);
dsc_sink_caps     511 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
dsc_sink_caps     535 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (!dsc_sink_caps->is_dsc_supported)
dsc_sink_caps     538 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width)
dsc_sink_caps     542 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);
dsc_sink_caps     562 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps;
dsc_sink_caps     563 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps;
dsc_sink_caps     567 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps;
dsc_sink_caps     568 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps;
dsc_sink_caps     572 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps;
dsc_sink_caps     573 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps;
dsc_sink_caps     577 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 			sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps;
dsc_sink_caps     582 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps;
dsc_sink_caps     583 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps;
dsc_sink_caps     712 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data, const uint8_t *dpcd_dsc_ext_data, struct dsc_dec_dpcd_caps *dsc_sink_caps)
dsc_sink_caps     717 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->is_dsc_supported = (dpcd_dsc_basic_data[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED) != 0;
dsc_sink_caps     718 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (!dsc_sink_caps->is_dsc_supported)
dsc_sink_caps     721 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->dsc_version = dpcd_dsc_basic_data[DP_DSC_REV - DP_DSC_SUPPORT];
dsc_sink_caps     731 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->rc_buffer_size = buff_size * buff_block_size;
dsc_sink_caps     734 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->slice_caps1.raw = dpcd_dsc_basic_data[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
dsc_sink_caps     735 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (!dsc_line_buff_depth_from_dpcd(dpcd_dsc_basic_data[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT], &dsc_sink_caps->lb_bit_depth))
dsc_sink_caps     738 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->is_block_pred_supported =
dsc_sink_caps     741 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->edp_max_bits_per_pixel =
dsc_sink_caps     745 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->color_formats.raw = dpcd_dsc_basic_data[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT];
dsc_sink_caps     746 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->color_depth.raw = dpcd_dsc_basic_data[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
dsc_sink_caps     751 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		if (!dsc_throughput_from_dpcd(dpcd_throughput & DP_DSC_THROUGHPUT_MODE_0_MASK, &dsc_sink_caps->throughput_mode_0_mps))
dsc_sink_caps     755 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		if (!dsc_throughput_from_dpcd(dpcd_throughput, &dsc_sink_caps->throughput_mode_1_mps))
dsc_sink_caps     759 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->max_slice_width = dpcd_dsc_basic_data[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 320;
dsc_sink_caps     760 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->slice_caps2.raw = dpcd_dsc_basic_data[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
dsc_sink_caps     762 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (!dsc_bpp_increment_div_from_dpcd(dpcd_dsc_basic_data[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT], &dsc_sink_caps->bpp_increment_div))
dsc_sink_caps     767 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_0_mps = 0;
dsc_sink_caps     768 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_1_mps = 0;
dsc_sink_caps     769 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_max_line_width = 0;
dsc_sink_caps     773 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->branch_overall_throughput_0_mps = dpcd_dsc_ext_data[DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
dsc_sink_caps     774 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (dsc_sink_caps->branch_overall_throughput_0_mps == 0)
dsc_sink_caps     775 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_0_mps = 0;
dsc_sink_caps     776 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	else if (dsc_sink_caps->branch_overall_throughput_0_mps == 1)
dsc_sink_caps     777 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_0_mps = 680;
dsc_sink_caps     779 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_0_mps *= 50;
dsc_sink_caps     780 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_0_mps += 600;
dsc_sink_caps     783 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->branch_overall_throughput_1_mps = dpcd_dsc_ext_data[DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
dsc_sink_caps     784 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (dsc_sink_caps->branch_overall_throughput_1_mps == 0)
dsc_sink_caps     785 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_1_mps = 0;
dsc_sink_caps     786 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	else if (dsc_sink_caps->branch_overall_throughput_1_mps == 1)
dsc_sink_caps     787 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_1_mps = 680;
dsc_sink_caps     789 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_1_mps *= 50;
dsc_sink_caps     790 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		dsc_sink_caps->branch_overall_throughput_1_mps += 600;
dsc_sink_caps     793 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->branch_max_line_width = dpcd_dsc_ext_data[DP_DSC_BRANCH_MAX_LINE_WIDTH - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0] * 320;
dsc_sink_caps     794 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	ASSERT(dsc_sink_caps->branch_max_line_width == 0 || dsc_sink_caps->branch_max_line_width >= 5120);
dsc_sink_caps     808 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
dsc_sink_caps     819 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,
dsc_sink_caps     823 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		is_dsc_possible = setup_dsc_config(dsc_sink_caps,
dsc_sink_caps     836 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
dsc_sink_caps     845 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = setup_dsc_config(dsc_sink_caps,