dsc_reg_vals       32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
dsc_reg_vals      207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dsc_reg_values dsc_reg_vals;
dsc_reg_vals      213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
dsc_reg_vals      215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
dsc_reg_vals      216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_log_pps(dsc, &dsc_reg_vals.pps);
dsc_reg_vals      307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
dsc_reg_vals      338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_init_reg_values(dsc_reg_vals);
dsc_reg_vals      341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
dsc_reg_vals      342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
dsc_reg_vals      343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
dsc_reg_vals      344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
dsc_reg_vals      345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
dsc_reg_vals      346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
dsc_reg_vals      347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
dsc_reg_vals      348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
dsc_reg_vals      349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
dsc_reg_vals      350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
dsc_reg_vals      354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
dsc_reg_vals      355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
dsc_reg_vals      357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
dsc_reg_vals      358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
dsc_reg_vals      363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
dsc_reg_vals      364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
dsc_reg_vals      365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
dsc_reg_vals      367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
dsc_reg_vals      369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
dsc_reg_vals      370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
dsc_reg_vals      371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
dsc_reg_vals      372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
dsc_reg_vals      374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) {
dsc_reg_vals      379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
dsc_reg_vals      382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
dsc_reg_vals      383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
dsc_reg_vals      384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 					dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
dsc_reg_vals      385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 					dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;