dsc_mode          379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				s.dsc_mode,
dsc_mode          189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 					enum optc_dsc_mode dsc_mode,
dsc_mode          196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		OPTC_DSC_MODE, dsc_mode);
dsc_mode           91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 					enum optc_dsc_mode dsc_mode,
dsc_mode          277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 					enum optc_dsc_mode dsc_mode,
dsc_mode          284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 			DP_DSC_MODE, dsc_mode,
dsc_mode          351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
dsc_mode          352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	if (s->dsc_mode) {
dsc_mode          114 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 	uint32_t dsc_mode;  // DISABLED  0; 1 or 2 indicate enabled state.
dsc_mode          223 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 			enum optc_dsc_mode dsc_mode,
dsc_mode          271 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 			       enum optc_dsc_mode dsc_mode,