dsc_cfg 3650 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &stream->timing.dsc_cfg)) dsc_cfg 1877 drivers/gpu/drm/amd/display/dc/core/dc.c struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; dsc_cfg 1882 drivers/gpu/drm/amd/display/dc/core/dc.c stream->timing.dsc_cfg = *update->dsc_config; dsc_cfg 1886 drivers/gpu/drm/amd/display/dc/core/dc.c stream->timing.dsc_cfg = old_dsc_cfg; dsc_cfg 2921 drivers/gpu/drm/amd/display/dc/core/dc_link.c kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); dsc_cfg 394 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dsc_config dsc_cfg; dsc_cfg 399 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; dsc_cfg 400 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; dsc_cfg 401 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; dsc_cfg 402 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.color_depth = stream->timing.display_color_depth; dsc_cfg 403 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dsc_cfg 404 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg 405 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; dsc_cfg 407 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); dsc_cfg 412 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); dsc_cfg 415 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; dsc_cfg 416 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width *= opp_cnt; dsc_cfg 496 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct dsc_config dsc_cfg; dsc_cfg 500 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; dsc_cfg 501 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; dsc_cfg 502 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; dsc_cfg 503 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.color_depth = stream->timing.display_color_depth; dsc_cfg 504 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dsc_cfg 507 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); dsc_cfg 112 drivers/gpu/drm/amd/display/dc/core/dc_stream.c memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); dsc_cfg 113 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.num_slices_h = 0; dsc_cfg 114 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.num_slices_v = 0; dsc_cfg 115 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.bits_per_pixel = 128; dsc_cfg 116 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.block_pred_enable = 1; dsc_cfg 117 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.linebuf_depth = 9; dsc_cfg 118 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.version_minor = 2; dsc_cfg 119 drivers/gpu/drm/amd/display/dc/core/dc_stream.c stream->timing.dsc_cfg.ycbcr422_simple = 0; dsc_cfg 60 drivers/gpu/drm/amd/display/dc/dc_dsc.h struct dc_dsc_config *dsc_cfg); dsc_cfg 803 drivers/gpu/drm/amd/display/dc/dc_hw_types.h struct dc_dsc_config dsc_cfg; dsc_cfg 1554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c && !timing->dsc_cfg.ycbcr422_simple); dsc_cfg 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, dsc_cfg 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); dsc_cfg 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc_cfg 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); dsc_cfg 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) dsc_cfg 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (dsc_cfg->pic_width > dsc20->max_image_width) dsc_cfg 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); dsc_cfg 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc_cfg 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_config_log(dsc, dsc_cfg); dsc_cfg 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); dsc_cfg 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) dsc_cfg 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_config_log(dsc, dsc_cfg); dsc_cfg 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); dsc_cfg 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, dsc_cfg 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); dsc_cfg 314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); dsc_cfg 315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); dsc_cfg 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->pic_width); dsc_cfg 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->pic_height); dsc_cfg 318 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && dsc_cfg 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || dsc_cfg 320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c (dsc_cfg->dc_dsc_cfg.version_minor == 2 && dsc_cfg 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || dsc_cfg 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); dsc_cfg 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 dsc_cfg 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || dsc_cfg 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || dsc_cfg 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !dsc_cfg->pic_width || !dsc_cfg->pic_height || dsc_cfg 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: dsc_cfg 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || dsc_cfg 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: dsc_cfg 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || dsc_cfg 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || dsc_cfg 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { dsc_cfg 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); dsc_cfg 342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; dsc_cfg 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; dsc_cfg 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; dsc_cfg 345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; dsc_cfg 346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; dsc_cfg 347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); dsc_cfg 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; dsc_cfg 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; dsc_cfg 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; dsc_cfg 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; dsc_cfg 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); dsc_cfg 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { dsc_cfg 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); dsc_cfg 363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; dsc_cfg 1908 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; dsc_cfg 2261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dsc_config dsc_cfg; dsc_cfg 2272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left dsc_cfg 2274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top dsc_cfg 2276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; dsc_cfg 2277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.color_depth = stream->timing.display_color_depth; dsc_cfg 2278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dsc_cfg 2279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; dsc_cfg 2281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) dsc_cfg 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c && !timing->dsc_cfg.ycbcr422_simple); dsc_cfg 515 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c struct dc_dsc_config *dsc_cfg) dsc_cfg 530 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); dsc_cfg 548 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->bits_per_pixel = target_bpp; dsc_cfg 558 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->ycbcr422_simple = false; dsc_cfg 576 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->ycbcr422_simple = is_dsc_possible; dsc_cfg 674 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->num_slices_h = num_slices_h; dsc_cfg 695 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->num_slices_v = pic_height/slice_height; dsc_cfg 700 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->block_pred_enable = dsc_common_caps.is_block_pred_supported; dsc_cfg 701 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->linebuf_depth = dsc_common_caps.lb_bit_depth; dsc_cfg 702 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc_cfg->version_minor = (dsc_common_caps.dsc_version & 0xf0) >> 4; dsc_cfg 707 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); dsc_cfg 839 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c struct dc_dsc_config *dsc_cfg) dsc_cfg 848 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c timing, dsc_cfg); dsc_cfg 75 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc) dsc_cfg 79 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; dsc_cfg 80 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; dsc_cfg 81 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->initial_offset = rc->initial_fullness_offset; dsc_cfg 82 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay; dsc_cfg 83 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; dsc_cfg 84 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset; dsc_cfg 85 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->flatness_min_qp = rc->flatness_min_qp; dsc_cfg 86 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->flatness_max_qp = rc->flatness_max_qp; dsc_cfg 88 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; dsc_cfg 89 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i]; dsc_cfg 91 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; dsc_cfg 93 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_model_size = rc->rc_model_size; dsc_cfg 94 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_edge_factor = rc->rc_edge_factor; dsc_cfg 95 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_tgt_offset_high = rc->rc_tgt_offset_hi; dsc_cfg 96 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_tgt_offset_low = rc->rc_tgt_offset_lo; dsc_cfg 99 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_buf_thresh[i] = rc->rc_buf_thresh[i]; dsc_cfg 115 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c struct drm_dsc_config dsc_cfg; dsc_cfg 135 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c copy_pps_fields(&dsc_cfg, &dsc_params->pps); dsc_cfg 136 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c copy_rc_to_cfg(&dsc_cfg, &rc); dsc_cfg 138 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64; dsc_cfg 140 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c ret = drm_dsc_compute_rc_parameters(&dsc_cfg); dsc_cfg 142 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c copy_pps_fields(&dsc_params->pps, &dsc_cfg); dsc_cfg 143 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; dsc_cfg 93 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); dsc_cfg 94 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc_cfg 96 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc_cfg 70 drivers/gpu/drm/drm_dsc.c const struct drm_dsc_config *dsc_cfg) dsc_cfg 82 drivers/gpu/drm/drm_dsc.c dsc_cfg->dsc_version_minor | dsc_cfg 83 drivers/gpu/drm/drm_dsc.c dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; dsc_cfg 89 drivers/gpu/drm/drm_dsc.c dsc_cfg->line_buf_depth | dsc_cfg 90 drivers/gpu/drm/drm_dsc.c dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; dsc_cfg 94 drivers/gpu/drm/drm_dsc.c ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> dsc_cfg 96 drivers/gpu/drm/drm_dsc.c dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | dsc_cfg 97 drivers/gpu/drm/drm_dsc.c dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | dsc_cfg 98 drivers/gpu/drm/drm_dsc.c dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | dsc_cfg 99 drivers/gpu/drm/drm_dsc.c dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; dsc_cfg 103 drivers/gpu/drm/drm_dsc.c (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); dsc_cfg 113 drivers/gpu/drm/drm_dsc.c pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); dsc_cfg 116 drivers/gpu/drm/drm_dsc.c pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); dsc_cfg 119 drivers/gpu/drm/drm_dsc.c pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); dsc_cfg 122 drivers/gpu/drm/drm_dsc.c pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); dsc_cfg 125 drivers/gpu/drm/drm_dsc.c pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); dsc_cfg 129 drivers/gpu/drm/drm_dsc.c ((dsc_cfg->initial_xmit_delay & dsc_cfg 135 drivers/gpu/drm/drm_dsc.c (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); dsc_cfg 139 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->initial_dec_delay); dsc_cfg 145 drivers/gpu/drm/drm_dsc.c dsc_cfg->initial_scale_value; dsc_cfg 149 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->scale_increment_interval); dsc_cfg 153 drivers/gpu/drm/drm_dsc.c ((dsc_cfg->scale_decrement_interval & dsc_cfg 159 drivers/gpu/drm/drm_dsc.c (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); dsc_cfg 165 drivers/gpu/drm/drm_dsc.c dsc_cfg->first_line_bpg_offset; dsc_cfg 169 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->nfl_bpg_offset); dsc_cfg 173 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->slice_bpg_offset); dsc_cfg 177 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->initial_offset); dsc_cfg 180 drivers/gpu/drm/drm_dsc.c pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); dsc_cfg 183 drivers/gpu/drm/drm_dsc.c pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; dsc_cfg 186 drivers/gpu/drm/drm_dsc.c pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; dsc_cfg 197 drivers/gpu/drm/drm_dsc.c dsc_cfg->rc_quant_incr_limit0; dsc_cfg 201 drivers/gpu/drm/drm_dsc.c dsc_cfg->rc_quant_incr_limit1; dsc_cfg 210 drivers/gpu/drm/drm_dsc.c dsc_cfg->rc_buf_thresh[i]; dsc_cfg 219 drivers/gpu/drm/drm_dsc.c ((dsc_cfg->rc_range_params[i].range_min_qp << dsc_cfg 221 drivers/gpu/drm/drm_dsc.c (dsc_cfg->rc_range_params[i].range_max_qp << dsc_cfg 223 drivers/gpu/drm/drm_dsc.c (dsc_cfg->rc_range_params[i].range_bpg_offset)); dsc_cfg 229 drivers/gpu/drm/drm_dsc.c pps_payload->native_422_420 = dsc_cfg->native_422 | dsc_cfg 230 drivers/gpu/drm/drm_dsc.c dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; dsc_cfg 234 drivers/gpu/drm/drm_dsc.c dsc_cfg->second_line_bpg_offset; dsc_cfg 238 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->nsl_bpg_offset); dsc_cfg 242 drivers/gpu/drm/drm_dsc.c cpu_to_be16(dsc_cfg->second_line_offset_adj); dsc_cfg 606 include/drm/drm_dsc.h const struct drm_dsc_config *dsc_cfg);