dsc20              62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc20->base.ctx
dsc20              65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc20->dsc_regs->reg
dsc20              69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
dsc20             156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dsc20             167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dsc20             169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (dsc_cfg->pic_width > dsc20->max_image_width)
dsc20             172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
dsc20             191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dsc20             196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
dsc20             199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_log_pps(dsc, &dsc20->reg_vals.pps);
dsc20             200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_write_to_registers(dsc, &dsc20->reg_vals);
dsc20             224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dsc20             240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dsc20             519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dsc20             699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) {