dsc 75 arch/alpha/include/asm/core_titan.h titan_64 dsc; dsc 68 arch/alpha/include/asm/core_tsunami.h tsunami_64 dsc; dsc 383 arch/alpha/kernel/core_titan.c printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr); dsc 406 arch/alpha/kernel/core_tsunami.c printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr); dsc 361 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t dsc:1, dsc 466 arch/mips/mm/cerr-sb1.c struct dc_state *dsc = dc_states; dsc 467 arch/mips/mm/cerr-sb1.c while (dsc->val != 0xff) { dsc 468 arch/mips/mm/cerr-sb1.c if (dsc->val == state) dsc 470 arch/mips/mm/cerr-sb1.c dsc++; dsc 472 arch/mips/mm/cerr-sb1.c return dsc->name; dsc 1314 arch/mips/pci/pcie-octeon.c pciercx_cfg515.s.dsc = 1; dsc 1984 drivers/atm/eni.c void __iomem *dsc; dsc 1987 drivers/atm/eni.c dsc = tx->send+ENI_PRV_POS(skb)*4; dsc 1988 drivers/atm/eni.c writel((readl(dsc) & ~(MID_SEG_RATE | MID_SEG_PR)) | dsc 1990 drivers/atm/eni.c (tx->resolution << MID_SEG_RATE_SHIFT), dsc); dsc 637 drivers/atm/zatm.c u32 *dsc; dsc 653 drivers/atm/zatm.c dsc = zatm_vcc->ring+zatm_vcc->ring_curr; dsc 656 drivers/atm/zatm.c dsc[1] = 0; dsc 657 drivers/atm/zatm.c dsc[2] = skb->len; dsc 658 drivers/atm/zatm.c dsc[3] = virt_to_bus(skb->data); dsc 660 drivers/atm/zatm.c dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP | uPD98401_TXPD_SM dsc 664 drivers/atm/zatm.c EVENT("dsc (0x%lx)\n",(unsigned long) dsc,0); dsc 668 drivers/atm/zatm.c dsc = NULL; dsc 673 drivers/atm/zatm.c dsc = kmalloc(uPD98401_TXPD_SIZE * 2 + dsc 675 drivers/atm/zatm.c if (!dsc) { dsc 683 drivers/atm/zatm.c put = dsc+8; dsc 684 drivers/atm/zatm.c dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP | dsc 688 drivers/atm/zatm.c dsc[1] = 0; dsc 689 drivers/atm/zatm.c dsc[2] = ATM_SKB(skb)->iovcnt * uPD98401_TXBD_SIZE; dsc 690 drivers/atm/zatm.c dsc[3] = virt_to_bus(put); dsc 699 drivers/atm/zatm.c ZATM_PRV_DSC(skb) = dsc; dsc 99 drivers/atm/zatm.h u32 *dsc; /* pointer to skb's descriptor */ dsc 102 drivers/atm/zatm.h #define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc) dsc 344 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->ctx->logger dsc 345 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c static void dsc_optc_config_log(struct display_stream_compressor *dsc, dsc 384 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; dsc 407 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); dsc 408 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); dsc 410 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; dsc 423 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_optc_config_log(dsc, &dsc_optc_cfg); dsc 434 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_optc_config_log(dsc, &dsc_optc_cfg); dsc 456 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); dsc 458 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); dsc 464 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; dsc 469 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!dsc) dsc 488 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; dsc 492 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!pipe_ctx->stream->timing.flags.DSC || !dsc) dsc 507 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); dsc 529 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; dsc 533 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c if (!dsc) dsc 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct display_stream_compressor *dsc = pool->dscs[i]; dsc 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dsc->funcs->dsc_read_state(dsc, &s); dsc 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dsc->inst, dsc 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); dsc 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); dsc 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); dsc 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); dsc 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); dsc 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); dsc 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_disable(struct display_stream_compressor *dsc); dsc 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->ctx->logger dsc 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c void dsc2_construct(struct dcn20_dsc *dsc, dsc 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->base.ctx = ctx; dsc 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->base.inst = inst; dsc 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->base.funcs = &dcn20_dsc_funcs; dsc 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->dsc_regs = dsc_regs; dsc 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->dsc_shift = dsc_shift; dsc 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->dsc_mask = dsc_mask; dsc 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->max_image_width = 5184; dsc 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) dsc 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); dsc 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) dsc 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); dsc 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) dsc 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); dsc 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); dsc 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_config_log(dsc, dsc_cfg); dsc 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_log_pps(dsc, &dsc20->reg_vals.pps); dsc 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_write_to_registers(dsc, &dsc20->reg_vals); dsc 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) dsc 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_config_log(dsc, dsc_cfg); dsc 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_log_pps(dsc, &dsc_reg_vals.pps); dsc 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) dsc 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); dsc 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc2_disable(struct display_stream_compressor *dsc) dsc 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); dsc 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) dsc 516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) dsc 519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); dsc 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h #define TO_DCN20_DSC(dsc)\ dsc 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h container_of(dsc, struct dcn20_dsc, base) dsc 566 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h void dsc2_construct(struct dcn20_dsc *dsc, dsc 1433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.dsc) { dsc 1436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); dsc 1438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); dsc 1450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->stream_res.dsc) { dsc 1453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); dsc 1455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); dsc 1659 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c else if (pipe_ctx->stream_res.dsc) { dsc 1284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dcn20_dsc *dsc = dsc 1287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!dsc) { dsc 1292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); dsc 1293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &dsc->base; dsc 1296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c void dcn20_dsc_destroy(struct display_stream_compressor **dsc) dsc 1298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(container_of(*dsc, struct dcn20_dsc, base)); dsc 1299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dsc = NULL; dsc 1533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct display_stream_compressor **dsc, dsc 1538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ASSERT(*dsc == NULL); dsc 1539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dsc = NULL; dsc 1542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dsc = pool->dscs[pipe_idx]; dsc 1550 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dsc = pool->dscs[i]; dsc 1558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct display_stream_compressor **dsc) dsc 1563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->dscs[i] == *dsc) { dsc 1565 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dsc = NULL; dsc 1589 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i); dsc 1592 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx->stream_res.dsc) { dsc 1615 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pipe_ctx->stream_res.dsc) dsc 1616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); dsc 1740 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->stream_res.dsc = NULL; dsc 1790 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); dsc 1791 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ASSERT(next_odm_pipe->stream_res.dsc); dsc 1792 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (next_odm_pipe->stream_res.dsc == NULL) dsc 1820 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->stream_res.dsc = NULL; dsc 2281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) dsc 2407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (odm_pipe->stream_res.dsc) dsc 2408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); dsc 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h void dcn20_dsc_destroy(struct display_stream_compressor **dsc); dsc 1261 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dcn20_dsc *dsc = dsc 1264 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!dsc) { dsc 1269 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); dsc 1270 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &dsc->base; dsc 186 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c struct display_stream_compressor *dsc = dc->res_pool->dscs[0]; dsc 189 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c if (dsc) dsc 190 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); dsc 239 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct display_stream_compressor *dsc; dsc 92 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); dsc 93 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); dsc 94 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc 96 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, dsc 98 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe); dsc 99 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h void (*dsc_disable)(struct display_stream_compressor *dsc); dsc 532 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .dsc = { dsc 725 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .dsc = { dsc 93 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h struct mdp5_sub_block dsc; dsc 425 drivers/ide/ide-atapi.c u8 stat, ireason, dsc = 0; dsc 494 drivers/ide/ide-atapi.c dsc = 1; dsc 503 drivers/ide/ide-atapi.c uptodate = drive->pc_callback(drive, dsc); dsc 63 drivers/ide/ide-floppy.c static int ide_floppy_callback(ide_drive_t *drive, int dsc) dsc 326 drivers/ide/ide-tape.c static int ide_tape_callback(ide_drive_t *drive, int dsc) dsc 335 drivers/ide/ide-tape.c dsc, err); dsc 337 drivers/ide/ide-tape.c if (dsc) dsc 239 drivers/irqchip/irq-partition-percpu.c struct irq_domain *partition_get_domain(struct partition_desc *dsc) dsc 241 drivers/irqchip/irq-partition-percpu.c if (dsc) dsc 242 drivers/irqchip/irq-partition-percpu.c return dsc->domain; dsc 1509 drivers/media/platform/s5p-mfc/s5p_mfc.c .dsc = DESC_BUF_SIZE, dsc 206 drivers/media/platform/s5p-mfc/s5p_mfc_common.h unsigned int dsc; dsc 686 drivers/media/platform/s5p-mfc/s5p_mfc_common.h struct s5p_mfc_priv_buf dsc; dsc 40 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c ctx->dsc.size = buf_size->dsc; dsc 41 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->dsc); dsc 47 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); dsc 48 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c memset(ctx->dsc.virt, 0, ctx->dsc.size); dsc 57 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c s5p_mfc_release_priv_buf(ctx->dev, &ctx->dsc); dsc 350 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); dsc 351 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); dsc 775 drivers/net/ethernet/broadcom/sb1250-mac.c struct sbdmadscr *dsc; dsc 782 drivers/net/ethernet/broadcom/sb1250-mac.c dsc = d->sbdma_addptr; dsc 839 drivers/net/ethernet/broadcom/sb1250-mac.c dsc->dscr_a = virt_to_phys(sb_new->data) | dsc 842 drivers/net/ethernet/broadcom/sb1250-mac.c dsc->dscr_a = virt_to_phys(sb_new->data) | dsc 848 drivers/net/ethernet/broadcom/sb1250-mac.c dsc->dscr_b = 0; dsc 854 drivers/net/ethernet/broadcom/sb1250-mac.c d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; dsc 889 drivers/net/ethernet/broadcom/sb1250-mac.c struct sbdmadscr *dsc; dsc 897 drivers/net/ethernet/broadcom/sb1250-mac.c dsc = d->sbdma_addptr; dsc 928 drivers/net/ethernet/broadcom/sb1250-mac.c dsc->dscr_a = phys | dsc 937 drivers/net/ethernet/broadcom/sb1250-mac.c dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | dsc 944 drivers/net/ethernet/broadcom/sb1250-mac.c d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; dsc 1058 drivers/net/ethernet/broadcom/sb1250-mac.c struct sbdmadscr *dsc; dsc 1084 drivers/net/ethernet/broadcom/sb1250-mac.c dsc = d->sbdma_remptr; dsc 1085 drivers/net/ethernet/broadcom/sb1250-mac.c curidx = dsc - d->sbdma_dscrtable; dsc 1087 drivers/net/ethernet/broadcom/sb1250-mac.c prefetch(dsc); dsc 1110 drivers/net/ethernet/broadcom/sb1250-mac.c len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; dsc 1118 drivers/net/ethernet/broadcom/sb1250-mac.c if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { dsc 1149 drivers/net/ethernet/broadcom/sb1250-mac.c if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && dsc 1150 drivers/net/ethernet/broadcom/sb1250-mac.c !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { dsc 1223 drivers/net/ethernet/broadcom/sb1250-mac.c struct sbdmadscr *dsc; dsc 1263 drivers/net/ethernet/broadcom/sb1250-mac.c dsc = &(d->sbdma_dscrtable[curidx]); dsc 70 drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ dsc 71 drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_stats.c atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset)) dsc 49 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_stats.c #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ dsc 50 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_stats.c atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset)) dsc 35 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ dsc 36 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h (*(u64 *)((char *)ptr + dsc[i].offset)) dsc 37 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ dsc 38 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset)) dsc 39 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ dsc 40 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h (*(u32 *)((char *)ptr + dsc[i].offset)) dsc 41 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ dsc 42 drivers/net/ethernet/mellanox/mlx5/core/en_stats.h be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset)) dsc 1966 drivers/usb/atm/ueagle-atm.c struct cmv_dsc_e1 *dsc = &sc->cmv_dsc.e1; dsc 1979 drivers/usb/atm/ueagle-atm.c if (cmv->bFunction != dsc->function) { dsc 1982 drivers/usb/atm/ueagle-atm.c cmv->wIndex = cpu_to_le16(dsc->idx); dsc 1983 drivers/usb/atm/ueagle-atm.c put_unaligned_le32(dsc->address, dsc 1985 drivers/usb/atm/ueagle-atm.c cmv->wOffsetAddress = cpu_to_le16(dsc->offset); dsc 1998 drivers/usb/atm/ueagle-atm.c if (le16_to_cpu(cmv->wIndex) != dsc->idx || dsc 1999 drivers/usb/atm/ueagle-atm.c get_unaligned_le32(&cmv->dwSymbolicAddress) != dsc->address || dsc 2000 drivers/usb/atm/ueagle-atm.c le16_to_cpu(cmv->wOffsetAddress) != dsc->offset) dsc 2028 drivers/usb/atm/ueagle-atm.c struct cmv_dsc_e4 *dsc = &sc->cmv_dsc.e4; dsc 2037 drivers/usb/atm/ueagle-atm.c if (be16_to_cpu(cmv->wFunction) != dsc->function) dsc 2048 drivers/usb/atm/ueagle-atm.c if (be16_to_cpu(cmv->wOffset) != dsc->offset || dsc 2049 drivers/usb/atm/ueagle-atm.c be16_to_cpu(cmv->wGroup) != dsc->group || dsc 2050 drivers/usb/atm/ueagle-atm.c be16_to_cpu(cmv->wAddress) != dsc->address) dsc 28 include/linux/irqchip/irq-partition-percpu.h struct irq_domain *partition_get_domain(struct partition_desc *dsc); dsc 47 include/linux/irqchip/irq-partition-percpu.h struct irq_domain *partition_get_domain(struct partition_desc *dsc) dsc 453 sound/pci/ctxfi/ctdaio.c struct daio_desc dsc = {0}; dsc 455 sound/pci/ctxfi/ctdaio.c dsc.type = dao->daio.type; dsc 456 sound/pci/ctxfi/ctdaio.c dsc.msr = desc->msr; dsc 457 sound/pci/ctxfi/ctdaio.c dsc.passthru = desc->passthru; dsc 459 sound/pci/ctxfi/ctdaio.c return dao_rsc_init(dao, &dsc, mgr);