drm 496 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu drm 34 drivers/gpu/drm/arc/arcpgu.h int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np); drm 35 drivers/gpu/drm/arc/arcpgu.h int arcpgu_drm_sim_init(struct drm_device *drm, struct device_node *np); drm 192 drivers/gpu/drm/arc/arcpgu_crtc.c static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm) drm 194 drivers/gpu/drm/arc/arcpgu_crtc.c struct arcpgu_drm_private *arcpgu = drm->dev_private; drm 199 drivers/gpu/drm/arc/arcpgu_crtc.c plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); drm 206 drivers/gpu/drm/arc/arcpgu_crtc.c ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs, drm 219 drivers/gpu/drm/arc/arcpgu_crtc.c int arc_pgu_setup_crtc(struct drm_device *drm) drm 221 drivers/gpu/drm/arc/arcpgu_crtc.c struct arcpgu_drm_private *arcpgu = drm->dev_private; drm 225 drivers/gpu/drm/arc/arcpgu_crtc.c primary = arc_pgu_plane_init(drm); drm 229 drivers/gpu/drm/arc/arcpgu_crtc.c ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL, drm 32 drivers/gpu/drm/arc/arcpgu_drv.c static void arcpgu_setup_mode_config(struct drm_device *drm) drm 34 drivers/gpu/drm/arc/arcpgu_drv.c drm_mode_config_init(drm); drm 35 drivers/gpu/drm/arc/arcpgu_drv.c drm->mode_config.min_width = 0; drm 36 drivers/gpu/drm/arc/arcpgu_drv.c drm->mode_config.min_height = 0; drm 37 drivers/gpu/drm/arc/arcpgu_drv.c drm->mode_config.max_width = 1920; drm 38 drivers/gpu/drm/arc/arcpgu_drv.c drm->mode_config.max_height = 1080; drm 39 drivers/gpu/drm/arc/arcpgu_drv.c drm->mode_config.funcs = &arcpgu_drm_modecfg_funcs; drm 44 drivers/gpu/drm/arc/arcpgu_drv.c static int arcpgu_load(struct drm_device *drm) drm 46 drivers/gpu/drm/arc/arcpgu_drv.c struct platform_device *pdev = to_platform_device(drm->dev); drm 56 drivers/gpu/drm/arc/arcpgu_drv.c drm->dev_private = arcpgu; drm 58 drivers/gpu/drm/arc/arcpgu_drv.c arcpgu->clk = devm_clk_get(drm->dev, "pxlclk"); drm 62 drivers/gpu/drm/arc/arcpgu_drv.c arcpgu_setup_mode_config(drm); drm 69 drivers/gpu/drm/arc/arcpgu_drv.c dev_info(drm->dev, "arc_pgu ID: 0x%x\n", drm 73 drivers/gpu/drm/arc/arcpgu_drv.c ret = of_reserved_mem_device_init(drm->dev); drm 77 drivers/gpu/drm/arc/arcpgu_drv.c if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32))) drm 80 drivers/gpu/drm/arc/arcpgu_drv.c if (arc_pgu_setup_crtc(drm) < 0) drm 84 drivers/gpu/drm/arc/arcpgu_drv.c encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0); drm 86 drivers/gpu/drm/arc/arcpgu_drv.c ret = arcpgu_drm_hdmi_init(drm, encoder_node); drm 91 drivers/gpu/drm/arc/arcpgu_drv.c ret = arcpgu_drm_sim_init(drm, NULL); drm 96 drivers/gpu/drm/arc/arcpgu_drv.c drm_mode_config_reset(drm); drm 97 drivers/gpu/drm/arc/arcpgu_drv.c drm_kms_helper_poll_init(drm); drm 99 drivers/gpu/drm/arc/arcpgu_drv.c platform_set_drvdata(pdev, drm); drm 103 drivers/gpu/drm/arc/arcpgu_drv.c static int arcpgu_unload(struct drm_device *drm) drm 105 drivers/gpu/drm/arc/arcpgu_drv.c drm_kms_helper_poll_fini(drm); drm 106 drivers/gpu/drm/arc/arcpgu_drv.c drm_atomic_helper_shutdown(drm); drm 107 drivers/gpu/drm/arc/arcpgu_drv.c drm_mode_config_cleanup(drm); drm 116 drivers/gpu/drm/arc/arcpgu_drv.c struct drm_device *drm = node->minor->dev; drm 117 drivers/gpu/drm/arc/arcpgu_drv.c struct arcpgu_drm_private *arcpgu = drm->dev_private; drm 164 drivers/gpu/drm/arc/arcpgu_drv.c struct drm_device *drm; drm 167 drivers/gpu/drm/arc/arcpgu_drv.c drm = drm_dev_alloc(&arcpgu_drm_driver, &pdev->dev); drm 168 drivers/gpu/drm/arc/arcpgu_drv.c if (IS_ERR(drm)) drm 169 drivers/gpu/drm/arc/arcpgu_drv.c return PTR_ERR(drm); drm 171 drivers/gpu/drm/arc/arcpgu_drv.c ret = arcpgu_load(drm); drm 175 drivers/gpu/drm/arc/arcpgu_drv.c ret = drm_dev_register(drm, 0); drm 179 drivers/gpu/drm/arc/arcpgu_drv.c drm_fbdev_generic_setup(drm, 16); drm 184 drivers/gpu/drm/arc/arcpgu_drv.c arcpgu_unload(drm); drm 187 drivers/gpu/drm/arc/arcpgu_drv.c drm_dev_put(drm); drm 194 drivers/gpu/drm/arc/arcpgu_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 196 drivers/gpu/drm/arc/arcpgu_drv.c drm_dev_unregister(drm); drm 197 drivers/gpu/drm/arc/arcpgu_drv.c arcpgu_unload(drm); drm 198 drivers/gpu/drm/arc/arcpgu_drv.c drm_dev_put(drm); drm 18 drivers/gpu/drm/arc/arcpgu_hdmi.c int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np) drm 25 drivers/gpu/drm/arc/arcpgu_hdmi.c encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL); drm 36 drivers/gpu/drm/arc/arcpgu_hdmi.c ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs, drm 57 drivers/gpu/drm/arc/arcpgu_sim.c int arcpgu_drm_sim_init(struct drm_device *drm, struct device_node *np) drm 64 drivers/gpu/drm/arc/arcpgu_sim.c encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL); drm 71 drivers/gpu/drm/arc/arcpgu_sim.c ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs, drm 76 drivers/gpu/drm/arc/arcpgu_sim.c arcpgu_connector = devm_kzalloc(drm->dev, sizeof(*arcpgu_connector), drm 86 drivers/gpu/drm/arc/arcpgu_sim.c ret = drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, drm 89 drivers/gpu/drm/arc/arcpgu_sim.c dev_err(drm->dev, "failed to initialize drm connector\n"); drm 95 drivers/gpu/drm/arc/arcpgu_sim.c dev_err(drm->dev, "could not attach connector to encoder\n"); drm 40 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_device *drm = data; drm 41 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct komeda_dev *mdev = drm->dev_private; drm 42 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct komeda_kms_dev *kms = to_kdev(drm); drm 262 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_device *drm; drm 268 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm = &kms->base; drm 269 drivers/gpu/drm/arm/display/komeda/komeda_kms.c err = drm_dev_init(drm, &komeda_kms_driver, mdev->dev); drm 273 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->dev_private = mdev; drm 285 drivers/gpu/drm/arm/display/komeda/komeda_kms.c err = drm_vblank_init(drm, kms->n_crtcs); drm 301 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_mode_config_reset(drm); drm 303 drivers/gpu/drm/arm/display/komeda/komeda_kms.c err = devm_request_irq(drm->dev, mdev->irq, drm 305 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->driver->name, drm); drm 313 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->irq_enabled = true; drm 315 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_kms_helper_poll_init(drm); drm 317 drivers/gpu/drm/arm/display/komeda/komeda_kms.c err = drm_dev_register(drm, 0); drm 324 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_kms_helper_poll_fini(drm); drm 325 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->irq_enabled = false; drm 328 drivers/gpu/drm/arm/display/komeda/komeda_kms.c component_unbind_all(mdev->dev, drm); drm 330 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_mode_config_cleanup(drm); drm 332 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->dev_private = NULL; drm 333 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_dev_put(drm); drm 341 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_device *drm = &kms->base; drm 342 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct komeda_dev *mdev = drm->dev_private; drm 344 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_dev_unregister(drm); drm 345 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_kms_helper_poll_fini(drm); drm 346 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_atomic_helper_shutdown(drm); drm 347 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->irq_enabled = false; drm 349 drivers/gpu/drm/arm/display/komeda/komeda_kms.c component_unbind_all(mdev->dev, drm); drm 350 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_mode_config_cleanup(drm); drm 352 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm->dev_private = NULL; drm 353 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_dev_put(drm); drm 293 drivers/gpu/drm/arm/hdlcd_crtc.c static struct drm_plane *hdlcd_plane_init(struct drm_device *drm) drm 295 drivers/gpu/drm/arm/hdlcd_crtc.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 300 drivers/gpu/drm/arm/hdlcd_crtc.c plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); drm 307 drivers/gpu/drm/arm/hdlcd_crtc.c ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs, drm 320 drivers/gpu/drm/arm/hdlcd_crtc.c int hdlcd_setup_crtc(struct drm_device *drm) drm 322 drivers/gpu/drm/arm/hdlcd_crtc.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 326 drivers/gpu/drm/arm/hdlcd_crtc.c primary = hdlcd_plane_init(drm); drm 330 drivers/gpu/drm/arm/hdlcd_crtc.c ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL, drm 41 drivers/gpu/drm/arm/hdlcd_drv.c static int hdlcd_load(struct drm_device *drm, unsigned long flags) drm 43 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 44 drivers/gpu/drm/arm/hdlcd_drv.c struct platform_device *pdev = to_platform_device(drm->dev); drm 49 drivers/gpu/drm/arm/hdlcd_drv.c hdlcd->clk = devm_clk_get(drm->dev, "pxlclk"); drm 61 drivers/gpu/drm/arm/hdlcd_drv.c hdlcd->mmio = devm_ioremap_resource(drm->dev, res); drm 79 drivers/gpu/drm/arm/hdlcd_drv.c ret = of_reserved_mem_device_init(drm->dev); drm 83 drivers/gpu/drm/arm/hdlcd_drv.c ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); drm 87 drivers/gpu/drm/arm/hdlcd_drv.c ret = hdlcd_setup_crtc(drm); drm 93 drivers/gpu/drm/arm/hdlcd_drv.c ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); drm 104 drivers/gpu/drm/arm/hdlcd_drv.c of_reserved_mem_device_release(drm->dev); drm 115 drivers/gpu/drm/arm/hdlcd_drv.c static void hdlcd_setup_mode_config(struct drm_device *drm) drm 117 drivers/gpu/drm/arm/hdlcd_drv.c drm_mode_config_init(drm); drm 118 drivers/gpu/drm/arm/hdlcd_drv.c drm->mode_config.min_width = 0; drm 119 drivers/gpu/drm/arm/hdlcd_drv.c drm->mode_config.min_height = 0; drm 120 drivers/gpu/drm/arm/hdlcd_drv.c drm->mode_config.max_width = HDLCD_MAX_XRES; drm 121 drivers/gpu/drm/arm/hdlcd_drv.c drm->mode_config.max_height = HDLCD_MAX_YRES; drm 122 drivers/gpu/drm/arm/hdlcd_drv.c drm->mode_config.funcs = &hdlcd_mode_config_funcs; drm 127 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm = arg; drm 128 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 156 drivers/gpu/drm/arm/hdlcd_drv.c static void hdlcd_irq_preinstall(struct drm_device *drm) drm 158 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 164 drivers/gpu/drm/arm/hdlcd_drv.c static int hdlcd_irq_postinstall(struct drm_device *drm) drm 167 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 178 drivers/gpu/drm/arm/hdlcd_drv.c static void hdlcd_irq_uninstall(struct drm_device *drm) drm 180 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 199 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm = node->minor->dev; drm 200 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 212 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm = node->minor->dev; drm 213 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 266 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm; drm 274 drivers/gpu/drm/arm/hdlcd_drv.c drm = drm_dev_alloc(&hdlcd_driver, dev); drm 275 drivers/gpu/drm/arm/hdlcd_drv.c if (IS_ERR(drm)) drm 276 drivers/gpu/drm/arm/hdlcd_drv.c return PTR_ERR(drm); drm 278 drivers/gpu/drm/arm/hdlcd_drv.c drm->dev_private = hdlcd; drm 279 drivers/gpu/drm/arm/hdlcd_drv.c dev_set_drvdata(dev, drm); drm 281 drivers/gpu/drm/arm/hdlcd_drv.c hdlcd_setup_mode_config(drm); drm 282 drivers/gpu/drm/arm/hdlcd_drv.c ret = hdlcd_load(drm, 0); drm 289 drivers/gpu/drm/arm/hdlcd_drv.c ret = component_bind_all(dev, drm); drm 301 drivers/gpu/drm/arm/hdlcd_drv.c ret = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 307 drivers/gpu/drm/arm/hdlcd_drv.c drm_mode_config_reset(drm); drm 308 drivers/gpu/drm/arm/hdlcd_drv.c drm_kms_helper_poll_init(drm); drm 310 drivers/gpu/drm/arm/hdlcd_drv.c ret = drm_dev_register(drm, 0); drm 314 drivers/gpu/drm/arm/hdlcd_drv.c drm_fbdev_generic_setup(drm, 32); drm 319 drivers/gpu/drm/arm/hdlcd_drv.c drm_kms_helper_poll_fini(drm); drm 321 drivers/gpu/drm/arm/hdlcd_drv.c pm_runtime_disable(drm->dev); drm 323 drivers/gpu/drm/arm/hdlcd_drv.c drm_atomic_helper_shutdown(drm); drm 324 drivers/gpu/drm/arm/hdlcd_drv.c component_unbind_all(dev, drm); drm 328 drivers/gpu/drm/arm/hdlcd_drv.c drm_irq_uninstall(drm); drm 329 drivers/gpu/drm/arm/hdlcd_drv.c of_reserved_mem_device_release(drm->dev); drm 331 drivers/gpu/drm/arm/hdlcd_drv.c drm_mode_config_cleanup(drm); drm 333 drivers/gpu/drm/arm/hdlcd_drv.c drm_dev_put(drm); drm 340 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 341 drivers/gpu/drm/arm/hdlcd_drv.c struct hdlcd_drm_private *hdlcd = drm->dev_private; drm 343 drivers/gpu/drm/arm/hdlcd_drv.c drm_dev_unregister(drm); drm 344 drivers/gpu/drm/arm/hdlcd_drv.c drm_kms_helper_poll_fini(drm); drm 345 drivers/gpu/drm/arm/hdlcd_drv.c component_unbind_all(dev, drm); drm 350 drivers/gpu/drm/arm/hdlcd_drv.c drm_irq_uninstall(drm); drm 351 drivers/gpu/drm/arm/hdlcd_drv.c drm_atomic_helper_shutdown(drm); drm 356 drivers/gpu/drm/arm/hdlcd_drv.c drm_mode_config_cleanup(drm); drm 357 drivers/gpu/drm/arm/hdlcd_drv.c drm->dev_private = NULL; drm 359 drivers/gpu/drm/arm/hdlcd_drv.c drm_dev_put(drm); drm 403 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 405 drivers/gpu/drm/arm/hdlcd_drv.c return drm_mode_config_helper_suspend(drm); drm 410 drivers/gpu/drm/arm/hdlcd_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 412 drivers/gpu/drm/arm/hdlcd_drv.c drm_mode_config_helper_resume(drm); drm 520 drivers/gpu/drm/arm/malidp_crtc.c int malidp_crtc_init(struct drm_device *drm) drm 522 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_drm *malidp = drm->dev_private; drm 526 drivers/gpu/drm/arm/malidp_crtc.c ret = malidp_de_planes_init(drm); drm 532 drivers/gpu/drm/arm/malidp_crtc.c drm_for_each_plane(plane, drm) { drm 544 drivers/gpu/drm/arm/malidp_crtc.c ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL, drm 169 drivers/gpu/drm/arm/malidp_drv.c static int malidp_set_and_wait_config_valid(struct drm_device *drm) drm 171 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 191 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = state->dev; drm 192 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 208 drivers/gpu/drm/arm/malidp_drv.c if (malidp_set_and_wait_config_valid(drm) < 0) { drm 214 drivers/gpu/drm/arm/malidp_drv.c if (!malidp_set_and_wait_config_valid(drm)) drm 222 drivers/gpu/drm/arm/malidp_drv.c spin_lock_irq(&drm->event_lock); drm 225 drivers/gpu/drm/arm/malidp_drv.c spin_unlock_irq(&drm->event_lock); drm 232 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = state->dev; drm 233 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 238 drivers/gpu/drm/arm/malidp_drv.c pm_runtime_get_sync(drm->dev); drm 247 drivers/gpu/drm/arm/malidp_drv.c drm_atomic_helper_commit_modeset_disables(drm, state); drm 255 drivers/gpu/drm/arm/malidp_drv.c drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY); drm 257 drivers/gpu/drm/arm/malidp_drv.c malidp_mw_atomic_commit(drm, state); drm 259 drivers/gpu/drm/arm/malidp_drv.c drm_atomic_helper_commit_modeset_enables(drm, state); drm 263 drivers/gpu/drm/arm/malidp_drv.c pm_runtime_put(drm->dev); drm 265 drivers/gpu/drm/arm/malidp_drv.c drm_atomic_helper_cleanup_planes(drm, state); drm 389 drivers/gpu/drm/arm/malidp_drv.c static int malidp_init(struct drm_device *drm) drm 392 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 395 drivers/gpu/drm/arm/malidp_drv.c drm_mode_config_init(drm); drm 397 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.min_width = hwdev->min_line_size; drm 398 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.min_height = hwdev->min_line_size; drm 399 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.max_width = hwdev->max_line_size; drm 400 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.max_height = hwdev->max_line_size; drm 401 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.funcs = &malidp_mode_config_funcs; drm 402 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.helper_private = &malidp_mode_config_helpers; drm 403 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.allow_fb_modifiers = true; drm 405 drivers/gpu/drm/arm/malidp_drv.c ret = malidp_crtc_init(drm); drm 409 drivers/gpu/drm/arm/malidp_drv.c ret = malidp_mw_connector_init(drm); drm 416 drivers/gpu/drm/arm/malidp_drv.c drm_mode_config_cleanup(drm); drm 420 drivers/gpu/drm/arm/malidp_drv.c static void malidp_fini(struct drm_device *drm) drm 422 drivers/gpu/drm/arm/malidp_drv.c drm_mode_config_cleanup(drm); drm 428 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(&pdev->dev); drm 429 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 444 drivers/gpu/drm/arm/malidp_drv.c ret = malidp_de_irq_init(drm, irq_de); drm 448 drivers/gpu/drm/arm/malidp_drv.c ret = malidp_se_irq_init(drm, irq_se); drm 460 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm, drm 463 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 469 drivers/gpu/drm/arm/malidp_drv.c return drm_gem_cma_dumb_create_internal(file_priv, drm, args); drm 508 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = m->private; drm 509 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 531 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = m->private; drm 532 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 662 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 663 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 689 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 690 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 708 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 709 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 725 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm; drm 773 drivers/gpu/drm/arm/malidp_drv.c drm = drm_dev_alloc(&malidp_driver, dev); drm 774 drivers/gpu/drm/arm/malidp_drv.c if (IS_ERR(drm)) { drm 775 drivers/gpu/drm/arm/malidp_drv.c ret = PTR_ERR(drm); drm 779 drivers/gpu/drm/arm/malidp_drv.c drm->dev_private = malidp; drm 780 drivers/gpu/drm/arm/malidp_drv.c dev_set_drvdata(dev, drm); drm 835 drivers/gpu/drm/arm/malidp_drv.c ret = malidp_init(drm); drm 846 drivers/gpu/drm/arm/malidp_drv.c ret = component_bind_all(dev, drm); drm 855 drivers/gpu/drm/arm/malidp_drv.c WARN_ON(drm->mode_config.num_encoder > 2); drm 856 drivers/gpu/drm/arm/malidp_drv.c list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) { drm 858 drivers/gpu/drm/arm/malidp_drv.c (1 << drm->mode_config.num_encoder) - 1; drm 865 drivers/gpu/drm/arm/malidp_drv.c drm->irq_enabled = true; drm 867 drivers/gpu/drm/arm/malidp_drv.c ret = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 875 drivers/gpu/drm/arm/malidp_drv.c drm_mode_config_reset(drm); drm 877 drivers/gpu/drm/arm/malidp_drv.c drm_kms_helper_poll_init(drm); drm 879 drivers/gpu/drm/arm/malidp_drv.c ret = drm_dev_register(drm, 0); drm 883 drivers/gpu/drm/arm/malidp_drv.c drm_fbdev_generic_setup(drm, 32); drm 888 drivers/gpu/drm/arm/malidp_drv.c drm_kms_helper_poll_fini(drm); drm 893 drivers/gpu/drm/arm/malidp_drv.c drm->irq_enabled = false; drm 895 drivers/gpu/drm/arm/malidp_drv.c drm_atomic_helper_shutdown(drm); drm 896 drivers/gpu/drm/arm/malidp_drv.c component_unbind_all(dev, drm); drm 902 drivers/gpu/drm/arm/malidp_drv.c malidp_fini(drm); drm 909 drivers/gpu/drm/arm/malidp_drv.c drm->dev_private = NULL; drm 911 drivers/gpu/drm/arm/malidp_drv.c drm_dev_put(drm); drm 920 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 921 drivers/gpu/drm/arm/malidp_drv.c struct malidp_drm *malidp = drm->dev_private; drm 924 drivers/gpu/drm/arm/malidp_drv.c drm_dev_unregister(drm); drm 925 drivers/gpu/drm/arm/malidp_drv.c drm_kms_helper_poll_fini(drm); drm 930 drivers/gpu/drm/arm/malidp_drv.c drm->irq_enabled = false; drm 931 drivers/gpu/drm/arm/malidp_drv.c drm_atomic_helper_shutdown(drm); drm 932 drivers/gpu/drm/arm/malidp_drv.c component_unbind_all(dev, drm); drm 936 drivers/gpu/drm/arm/malidp_drv.c malidp_fini(drm); drm 942 drivers/gpu/drm/arm/malidp_drv.c drm->dev_private = NULL; drm 944 drivers/gpu/drm/arm/malidp_drv.c drm_dev_put(drm); drm 988 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 990 drivers/gpu/drm/arm/malidp_drv.c return drm_mode_config_helper_suspend(drm); drm 995 drivers/gpu/drm/arm/malidp_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 997 drivers/gpu/drm/arm/malidp_drv.c drm_mode_config_helper_resume(drm); drm 87 drivers/gpu/drm/arm/malidp_drv.h int malidp_de_planes_init(struct drm_device *drm); drm 88 drivers/gpu/drm/arm/malidp_drv.h int malidp_crtc_init(struct drm_device *drm); drm 93 drivers/gpu/drm/arm/malidp_drv.h bool malidp_format_mod_supported(struct drm_device *drm, drm 1161 drivers/gpu/drm/arm/malidp_hw.c struct drm_device *drm = arg; drm 1162 drivers/gpu/drm/arm/malidp_hw.c struct malidp_drm *malidp = drm->dev_private; drm 1187 drivers/gpu/drm/arm/malidp_hw.c spin_lock(&drm->event_lock); drm 1190 drivers/gpu/drm/arm/malidp_hw.c spin_unlock(&drm->event_lock); drm 1219 drivers/gpu/drm/arm/malidp_hw.c struct drm_device *drm = arg; drm 1220 drivers/gpu/drm/arm/malidp_hw.c struct malidp_drm *malidp = drm->dev_private; drm 1244 drivers/gpu/drm/arm/malidp_hw.c int malidp_de_irq_init(struct drm_device *drm, int irq) drm 1246 drivers/gpu/drm/arm/malidp_hw.c struct malidp_drm *malidp = drm->dev_private; drm 1256 drivers/gpu/drm/arm/malidp_hw.c ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq, drm 1258 drivers/gpu/drm/arm/malidp_hw.c IRQF_SHARED, "malidp-de", drm); drm 1279 drivers/gpu/drm/arm/malidp_hw.c struct drm_device *drm = arg; drm 1280 drivers/gpu/drm/arm/malidp_hw.c struct malidp_drm *malidp = drm->dev_private; drm 1355 drivers/gpu/drm/arm/malidp_hw.c int malidp_se_irq_init(struct drm_device *drm, int irq) drm 1357 drivers/gpu/drm/arm/malidp_hw.c struct malidp_drm *malidp = drm->dev_private; drm 1365 drivers/gpu/drm/arm/malidp_hw.c ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq, drm 1367 drivers/gpu/drm/arm/malidp_hw.c IRQF_SHARED, "malidp-se", drm); drm 316 drivers/gpu/drm/arm/malidp_hw.h int malidp_de_irq_init(struct drm_device *drm, int irq); drm 320 drivers/gpu/drm/arm/malidp_hw.h int malidp_se_irq_init(struct drm_device *drm, int irq); drm 209 drivers/gpu/drm/arm/malidp_mw.c int malidp_mw_connector_init(struct drm_device *drm) drm 211 drivers/gpu/drm/arm/malidp_mw.c struct malidp_drm *malidp = drm->dev_private; drm 226 drivers/gpu/drm/arm/malidp_mw.c ret = drm_writeback_connector_init(drm, &malidp->mw_connector, drm 237 drivers/gpu/drm/arm/malidp_mw.c void malidp_mw_atomic_commit(struct drm_device *drm, drm 240 drivers/gpu/drm/arm/malidp_mw.c struct malidp_drm *malidp = drm->dev_private; drm 254 drivers/gpu/drm/arm/malidp_mw.c DRM_DEV_DEBUG_DRIVER(drm->dev, drm 269 drivers/gpu/drm/arm/malidp_mw.c DRM_DEV_DEBUG_DRIVER(drm->dev, "Disable memwrite\n"); drm 11 drivers/gpu/drm/arm/malidp_mw.h int malidp_mw_connector_init(struct drm_device *drm); drm 12 drivers/gpu/drm/arm/malidp_mw.h void malidp_mw_atomic_commit(struct drm_device *drm, drm 148 drivers/gpu/drm/arm/malidp_planes.c bool malidp_format_mod_supported(struct drm_device *drm, drm 153 drivers/gpu/drm/arm/malidp_planes.c struct malidp_drm *malidp = drm->dev_private; drm 925 drivers/gpu/drm/arm/malidp_planes.c int malidp_de_planes_init(struct drm_device *drm) drm 927 drivers/gpu/drm/arm/malidp_planes.c struct malidp_drm *malidp = drm->dev_private; drm 931 drivers/gpu/drm/arm/malidp_planes.c unsigned long crtcs = 1 << drm->mode_config.num_crtc; drm 986 drivers/gpu/drm/arm/malidp_planes.c ret = drm_universal_plane_init(drm, &plane->base, crtcs, drm 900 drivers/gpu/drm/armada/armada_crtc.c static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, drm 904 drivers/gpu/drm/armada/armada_crtc.c struct armada_private *priv = drm->dev_private; drm 920 drivers/gpu/drm/armada/armada_crtc.c if (dev != drm->dev) drm 925 drivers/gpu/drm/armada/armada_crtc.c dcrtc->num = drm->mode_config.num_crtc; drm 969 drivers/gpu/drm/armada/armada_crtc.c ret = armada_drm_primary_plane_init(drm, primary); drm 975 drivers/gpu/drm/armada/armada_crtc.c ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL, drm 988 drivers/gpu/drm/armada/armada_crtc.c return armada_overlay_plane_create(drm, 1 << dcrtc->num); drm 1002 drivers/gpu/drm/armada/armada_crtc.c struct drm_device *drm = data; drm 1040 drivers/gpu/drm/armada/armada_crtc.c return armada_drm_crtc_create(drm, dev, res, irq, variant, port); drm 57 drivers/gpu/drm/armada/armada_drm.h struct drm_device drm; drm 97 drivers/gpu/drm/armada/armada_drv.c BUILD_BUG_ON(offsetof(struct armada_private, drm) != 0); drm 99 drivers/gpu/drm/armada/armada_drv.c ret = drm_dev_init(&priv->drm, &armada_drm_driver, dev); drm 118 drivers/gpu/drm/armada/armada_drv.c priv->drm.dev_private = priv; drm 120 drivers/gpu/drm/armada/armada_drv.c dev_set_drvdata(dev, &priv->drm); drm 123 drivers/gpu/drm/armada/armada_drv.c drm_mode_config_init(&priv->drm); drm 124 drivers/gpu/drm/armada/armada_drv.c priv->drm.mode_config.min_width = 320; drm 125 drivers/gpu/drm/armada/armada_drv.c priv->drm.mode_config.min_height = 200; drm 131 drivers/gpu/drm/armada/armada_drv.c priv->drm.mode_config.max_width = 1920; drm 132 drivers/gpu/drm/armada/armada_drv.c priv->drm.mode_config.max_height = 2048; drm 134 drivers/gpu/drm/armada/armada_drv.c priv->drm.mode_config.preferred_depth = 24; drm 135 drivers/gpu/drm/armada/armada_drv.c priv->drm.mode_config.funcs = &armada_drm_mode_config_funcs; drm 139 drivers/gpu/drm/armada/armada_drv.c ret = component_bind_all(dev, &priv->drm); drm 143 drivers/gpu/drm/armada/armada_drv.c ret = drm_vblank_init(&priv->drm, priv->drm.mode_config.num_crtc); drm 147 drivers/gpu/drm/armada/armada_drv.c priv->drm.irq_enabled = true; drm 149 drivers/gpu/drm/armada/armada_drv.c drm_mode_config_reset(&priv->drm); drm 151 drivers/gpu/drm/armada/armada_drv.c ret = armada_fbdev_init(&priv->drm); drm 155 drivers/gpu/drm/armada/armada_drv.c drm_kms_helper_poll_init(&priv->drm); drm 157 drivers/gpu/drm/armada/armada_drv.c ret = drm_dev_register(&priv->drm, 0); drm 162 drivers/gpu/drm/armada/armada_drv.c armada_drm_debugfs_init(priv->drm.primary); drm 168 drivers/gpu/drm/armada/armada_drv.c drm_kms_helper_poll_fini(&priv->drm); drm 169 drivers/gpu/drm/armada/armada_drv.c armada_fbdev_fini(&priv->drm); drm 171 drivers/gpu/drm/armada/armada_drv.c component_unbind_all(dev, &priv->drm); drm 173 drivers/gpu/drm/armada/armada_drv.c drm_mode_config_cleanup(&priv->drm); drm 175 drivers/gpu/drm/armada/armada_drv.c drm_dev_put(&priv->drm); drm 181 drivers/gpu/drm/armada/armada_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 182 drivers/gpu/drm/armada/armada_drv.c struct armada_private *priv = drm->dev_private; drm 184 drivers/gpu/drm/armada/armada_drv.c drm_kms_helper_poll_fini(&priv->drm); drm 185 drivers/gpu/drm/armada/armada_drv.c armada_fbdev_fini(&priv->drm); drm 187 drivers/gpu/drm/armada/armada_drv.c drm_dev_unregister(&priv->drm); drm 189 drivers/gpu/drm/armada/armada_drv.c drm_atomic_helper_shutdown(&priv->drm); drm 191 drivers/gpu/drm/armada/armada_drv.c component_unbind_all(dev, &priv->drm); drm 193 drivers/gpu/drm/armada/armada_drv.c drm_mode_config_cleanup(&priv->drm); drm 196 drivers/gpu/drm/armada/armada_drv.c drm_dev_put(&priv->drm); drm 29 drivers/gpu/drm/armada/armada_fb.c #define FMT(drm, fmt, mod) \ drm 30 drivers/gpu/drm/armada/armada_fb.c case DRM_FORMAT_##drm: \ drm 315 drivers/gpu/drm/armada/armada_plane.c int armada_drm_primary_plane_init(struct drm_device *drm, drm 322 drivers/gpu/drm/armada/armada_plane.c ret = drm_universal_plane_init(drm, primary, 0, drm 35 drivers/gpu/drm/armada/armada_plane.h int armada_drm_primary_plane_init(struct drm_device *drm, drm 89 drivers/gpu/drm/armada/armada_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/armada drm 18 drivers/gpu/drm/aspeed/aspeed_gfx.h int aspeed_gfx_create_pipe(struct drm_device *drm); drm 19 drivers/gpu/drm/aspeed/aspeed_gfx.h int aspeed_gfx_create_output(struct drm_device *drm); drm 29 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c struct drm_device *drm = crtc->dev; drm 38 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c dev_dbg(drm->dev, "Setting up RGB565 mode\n"); drm 43 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c dev_dbg(drm->dev, "Setting up XRGB8888 mode\n"); drm 48 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c dev_err(drm->dev, "Unhandled pixel format %08x\n", format); drm 232 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c int aspeed_gfx_create_pipe(struct drm_device *drm) drm 234 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c struct aspeed_gfx *priv = drm->dev_private; drm 236 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c return drm_simple_display_pipe_init(drm, &priv->pipe, &aspeed_gfx_funcs, drm 66 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c static void aspeed_gfx_setup_mode_config(struct drm_device *drm) drm 68 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_mode_config_init(drm); drm 70 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->mode_config.min_width = 0; drm 71 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->mode_config.min_height = 0; drm 72 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->mode_config.max_width = 800; drm 73 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->mode_config.max_height = 600; drm 74 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->mode_config.funcs = &aspeed_gfx_mode_config_funcs; drm 79 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c struct drm_device *drm = data; drm 80 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c struct aspeed_gfx *priv = drm->dev_private; drm 96 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c static int aspeed_gfx_load(struct drm_device *drm) drm 98 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c struct platform_device *pdev = to_platform_device(drm->dev); drm 106 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->dev_private = priv; drm 109 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c priv->base = devm_ioremap_resource(drm->dev, res); drm 119 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = of_reserved_mem_device_init(drm->dev); drm 126 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); drm 140 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c priv->clk = devm_clk_get(drm->dev, NULL); drm 152 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c aspeed_gfx_setup_mode_config(drm); drm 154 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = drm_vblank_init(drm, 1); drm 156 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c dev_err(drm->dev, "Failed to initialise vblank\n"); drm 160 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = aspeed_gfx_create_output(drm); drm 162 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c dev_err(drm->dev, "Failed to create outputs\n"); drm 166 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = aspeed_gfx_create_pipe(drm); drm 168 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c dev_err(drm->dev, "Cannot setup simple display pipe\n"); drm 172 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = devm_request_irq(drm->dev, platform_get_irq(pdev, 0), drm 173 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c aspeed_gfx_irq_handler, 0, "aspeed gfx", drm); drm 175 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c dev_err(drm->dev, "Failed to install IRQ handler\n"); drm 179 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_mode_config_reset(drm); drm 181 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_fbdev_generic_setup(drm, 32); drm 186 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c static void aspeed_gfx_unload(struct drm_device *drm) drm 188 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_kms_helper_poll_fini(drm); drm 189 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_mode_config_cleanup(drm); drm 191 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm->dev_private = NULL; drm 219 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c struct drm_device *drm; drm 222 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm = drm_dev_alloc(&aspeed_gfx_driver, &pdev->dev); drm 223 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c if (IS_ERR(drm)) drm 224 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c return PTR_ERR(drm); drm 226 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = aspeed_gfx_load(drm); drm 230 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c ret = drm_dev_register(drm, 0); drm 237 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c aspeed_gfx_unload(drm); drm 239 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_dev_put(drm); drm 246 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 248 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_dev_unregister(drm); drm 249 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c aspeed_gfx_unload(drm); drm 250 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c drm_dev_put(drm); drm 29 drivers/gpu/drm/aspeed/aspeed_gfx_out.c int aspeed_gfx_create_output(struct drm_device *drm) drm 31 drivers/gpu/drm/aspeed/aspeed_gfx_out.c struct aspeed_gfx *priv = drm->dev_private; drm 38 drivers/gpu/drm/aspeed/aspeed_gfx_out.c ret = drm_connector_init(drm, &priv->connector, drm 404 drivers/gpu/drm/bridge/sii902x.c struct drm_device *drm = bridge->dev; drm 410 drivers/gpu/drm/bridge/sii902x.c if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { drm 416 drivers/gpu/drm/bridge/sii902x.c ret = drm_connector_init(drm, &sii902x->connector, drm 354 drivers/gpu/drm/bridge/tc358764.c struct drm_device *drm = bridge->dev; drm 358 drivers/gpu/drm/bridge/tc358764.c ret = drm_connector_init(drm, &ctx->connector, drm 371 drivers/gpu/drm/bridge/tc358764.c drm_fb_helper_add_one_connector(drm->fb_helper, &ctx->connector); drm 380 drivers/gpu/drm/bridge/tc358764.c struct drm_device *drm = bridge->dev; drm 383 drivers/gpu/drm/bridge/tc358764.c drm_fb_helper_remove_one_connector(drm->fb_helper, &ctx->connector); drm 1390 drivers/gpu/drm/bridge/tc358767.c struct drm_device *drm = bridge->dev; drm 1395 drivers/gpu/drm/bridge/tc358767.c ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, drm 49 drivers/gpu/drm/drm_gem_cma_helper.c __drm_gem_cma_create(struct drm_device *drm, size_t size) drm 55 drivers/gpu/drm/drm_gem_cma_helper.c if (drm->driver->gem_create_object) drm 56 drivers/gpu/drm/drm_gem_cma_helper.c gem_obj = drm->driver->gem_create_object(drm, size); drm 63 drivers/gpu/drm/drm_gem_cma_helper.c ret = drm_gem_object_init(drm, gem_obj, size); drm 93 drivers/gpu/drm/drm_gem_cma_helper.c struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm, drm 101 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj = __drm_gem_cma_create(drm, size); drm 105 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj->vaddr = dma_alloc_wc(drm->dev, size, &cma_obj->paddr, drm 108 drivers/gpu/drm/drm_gem_cma_helper.c dev_dbg(drm->dev, "failed to allocate buffer with size %zu\n", drm 140 drivers/gpu/drm/drm_gem_cma_helper.c struct drm_device *drm, size_t size, drm 147 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj = drm_gem_cma_create(drm, size); drm 212 drivers/gpu/drm/drm_gem_cma_helper.c struct drm_device *drm, drm 224 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, args->size, drm 249 drivers/gpu/drm/drm_gem_cma_helper.c struct drm_device *drm, drm 257 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, args->size, drm 344 drivers/gpu/drm/drm_mipi_dbi.c if (!drm_dev_enter(&dbidev->drm, &idx)) drm 357 drivers/gpu/drm/drm_mipi_dbi.c struct drm_device *drm = &dbidev->drm; drm 358 drivers/gpu/drm/drm_mipi_dbi.c u16 height = drm->mode_config.min_height; drm 359 drivers/gpu/drm/drm_mipi_dbi.c u16 width = drm->mode_config.min_width; drm 364 drivers/gpu/drm/drm_mipi_dbi.c if (!drm_dev_enter(drm, &idx)) drm 506 drivers/gpu/drm/drm_mipi_dbi.c struct drm_device *drm = &dbidev->drm; drm 512 drivers/gpu/drm/drm_mipi_dbi.c dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL); drm 524 drivers/gpu/drm/drm_mipi_dbi.c ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs, drm 529 drivers/gpu/drm/drm_mipi_dbi.c ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count, drm 536 drivers/gpu/drm/drm_mipi_dbi.c drm->mode_config.funcs = &mipi_dbi_mode_config_funcs; drm 537 drivers/gpu/drm/drm_mipi_dbi.c drm->mode_config.min_width = dbidev->mode.hdisplay; drm 538 drivers/gpu/drm/drm_mipi_dbi.c drm->mode_config.max_width = dbidev->mode.hdisplay; drm 539 drivers/gpu/drm/drm_mipi_dbi.c drm->mode_config.min_height = dbidev->mode.vdisplay; drm 540 drivers/gpu/drm/drm_mipi_dbi.c drm->mode_config.max_height = dbidev->mode.vdisplay; drm 572 drivers/gpu/drm/drm_mipi_dbi.c dbidev->drm.mode_config.preferred_depth = 16; drm 588 drivers/gpu/drm/drm_mipi_dbi.c void mipi_dbi_release(struct drm_device *drm) drm 590 drivers/gpu/drm/drm_mipi_dbi.c struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(drm); drm 594 drivers/gpu/drm/drm_mipi_dbi.c drm_mode_config_cleanup(drm); drm 595 drivers/gpu/drm/drm_mipi_dbi.c drm_dev_fini(drm); drm 652 drivers/gpu/drm/drm_mipi_dbi.c struct device *dev = dbidev->drm.dev; drm 1192 drivers/gpu/drm/drm_mipi_dbi.c if (!drm_dev_enter(&dbidev->drm, &idx)) drm 1249 drivers/gpu/drm/drm_mipi_dbi.c if (!drm_dev_enter(&dbidev->drm, &idx)) drm 111 drivers/gpu/drm/drm_panel.c panel->drm = connector->dev; drm 130 drivers/gpu/drm/drm_panel.c panel->drm = NULL; drm 12 drivers/gpu/drm/drm_trace.h #define TRACE_SYSTEM drm drm 67 drivers/gpu/drm/drm_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm drm 537 drivers/gpu/drm/etnaviv/etnaviv_drv.c struct drm_device *drm; drm 540 drivers/gpu/drm/etnaviv/etnaviv_drv.c drm = drm_dev_alloc(&etnaviv_drm_driver, dev); drm 541 drivers/gpu/drm/etnaviv/etnaviv_drv.c if (IS_ERR(drm)) drm 542 drivers/gpu/drm/etnaviv/etnaviv_drv.c return PTR_ERR(drm); drm 550 drivers/gpu/drm/etnaviv/etnaviv_drv.c drm->dev_private = priv; drm 559 drivers/gpu/drm/etnaviv/etnaviv_drv.c priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(drm->dev); drm 561 drivers/gpu/drm/etnaviv/etnaviv_drv.c dev_err(drm->dev, "Failed to create cmdbuf suballocator\n"); drm 566 drivers/gpu/drm/etnaviv/etnaviv_drv.c dev_set_drvdata(dev, drm); drm 568 drivers/gpu/drm/etnaviv/etnaviv_drv.c ret = component_bind_all(dev, drm); drm 572 drivers/gpu/drm/etnaviv/etnaviv_drv.c load_gpu(drm); drm 574 drivers/gpu/drm/etnaviv/etnaviv_drv.c ret = drm_dev_register(drm, 0); drm 581 drivers/gpu/drm/etnaviv/etnaviv_drv.c component_unbind_all(dev, drm); drm 587 drivers/gpu/drm/etnaviv/etnaviv_drv.c drm_dev_put(drm); drm 594 drivers/gpu/drm/etnaviv/etnaviv_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 595 drivers/gpu/drm/etnaviv/etnaviv_drv.c struct etnaviv_drm_private *priv = drm->dev_private; drm 597 drivers/gpu/drm/etnaviv/etnaviv_drv.c drm_dev_unregister(drm); drm 599 drivers/gpu/drm/etnaviv/etnaviv_drv.c component_unbind_all(dev, drm); drm 605 drivers/gpu/drm/etnaviv/etnaviv_drv.c drm->dev_private = NULL; drm 608 drivers/gpu/drm/etnaviv/etnaviv_drv.c drm_dev_put(drm); drm 45 drivers/gpu/drm/etnaviv/etnaviv_gpu.c struct etnaviv_drm_private *priv = gpu->drm->dev_private; drm 710 drivers/gpu/drm/etnaviv/etnaviv_gpu.c struct etnaviv_drm_private *priv = gpu->drm->dev_private; drm 1608 drivers/gpu/drm/etnaviv/etnaviv_gpu.c struct drm_device *drm = data; drm 1609 drivers/gpu/drm/etnaviv/etnaviv_gpu.c struct etnaviv_drm_private *priv = drm->dev_private; drm 1639 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu->drm = drm; drm 1692 drivers/gpu/drm/etnaviv/etnaviv_gpu.c gpu->drm = NULL; drm 1826 drivers/gpu/drm/etnaviv/etnaviv_gpu.c if (gpu->drm && gpu->initialized) { drm 95 drivers/gpu/drm/etnaviv/etnaviv_gpu.h struct drm_device *drm; drm 438 drivers/gpu/drm/etnaviv/etnaviv_mmu.c struct etnaviv_drm_private *priv = gpu->drm->dev_private; drm 440 drivers/gpu/drm/etnaviv/etnaviv_mmu.c struct device *dev = gpu->drm->dev; drm 498 drivers/gpu/drm/etnaviv/etnaviv_mmu.c struct etnaviv_drm_private *priv = gpu->drm->dev_private; drm 121 drivers/gpu/drm/exynos/exynos_drm_dma.c int exynos_drm_register_dma(struct drm_device *drm, struct device *dev, drm 124 drivers/gpu/drm/exynos/exynos_drm_dma.c struct exynos_drm_private *priv = drm->dev_private; drm 149 drivers/gpu/drm/exynos/exynos_drm_dma.c return drm_iommu_attach_device(drm, dev, dma_priv); drm 152 drivers/gpu/drm/exynos/exynos_drm_dma.c void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev, drm 156 drivers/gpu/drm/exynos/exynos_drm_dma.c drm_iommu_detach_device(drm, dev, dma_priv); drm 159 drivers/gpu/drm/exynos/exynos_drm_dma.c void exynos_drm_cleanup_dma(struct drm_device *drm) drm 161 drivers/gpu/drm/exynos/exynos_drm_dma.c struct exynos_drm_private *priv = drm->dev_private; drm 271 drivers/gpu/drm/exynos/exynos_drm_drv.c struct drm_device *drm; drm 275 drivers/gpu/drm/exynos/exynos_drm_drv.c drm = drm_dev_alloc(&exynos_drm_driver, dev); drm 276 drivers/gpu/drm/exynos/exynos_drm_drv.c if (IS_ERR(drm)) drm 277 drivers/gpu/drm/exynos/exynos_drm_drv.c return PTR_ERR(drm); drm 288 drivers/gpu/drm/exynos/exynos_drm_drv.c dev_set_drvdata(dev, drm); drm 289 drivers/gpu/drm/exynos/exynos_drm_drv.c drm->dev_private = (void *)private; drm 291 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_mode_config_init(drm); drm 293 drivers/gpu/drm/exynos/exynos_drm_drv.c exynos_drm_mode_config_init(drm); drm 298 drivers/gpu/drm/exynos/exynos_drm_drv.c list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) drm 301 drivers/gpu/drm/exynos/exynos_drm_drv.c list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) drm 305 drivers/gpu/drm/exynos/exynos_drm_drv.c ret = component_bind_all(drm->dev, drm); drm 309 drivers/gpu/drm/exynos/exynos_drm_drv.c ret = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 313 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_mode_config_reset(drm); drm 323 drivers/gpu/drm/exynos/exynos_drm_drv.c drm->irq_enabled = true; drm 326 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_kms_helper_poll_init(drm); drm 328 drivers/gpu/drm/exynos/exynos_drm_drv.c ret = exynos_drm_fbdev_init(drm); drm 333 drivers/gpu/drm/exynos/exynos_drm_drv.c ret = drm_dev_register(drm, 0); drm 340 drivers/gpu/drm/exynos/exynos_drm_drv.c exynos_drm_fbdev_fini(drm); drm 342 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_kms_helper_poll_fini(drm); drm 344 drivers/gpu/drm/exynos/exynos_drm_drv.c component_unbind_all(drm->dev, drm); drm 346 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_mode_config_cleanup(drm); drm 347 drivers/gpu/drm/exynos/exynos_drm_drv.c exynos_drm_cleanup_dma(drm); drm 350 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_dev_put(drm); drm 357 drivers/gpu/drm/exynos/exynos_drm_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 359 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_dev_unregister(drm); drm 361 drivers/gpu/drm/exynos/exynos_drm_drv.c exynos_drm_fbdev_fini(drm); drm 362 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_kms_helper_poll_fini(drm); drm 364 drivers/gpu/drm/exynos/exynos_drm_drv.c component_unbind_all(drm->dev, drm); drm 365 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_mode_config_cleanup(drm); drm 366 drivers/gpu/drm/exynos/exynos_drm_drv.c exynos_drm_cleanup_dma(drm); drm 368 drivers/gpu/drm/exynos/exynos_drm_drv.c kfree(drm->dev_private); drm 369 drivers/gpu/drm/exynos/exynos_drm_drv.c drm->dev_private = NULL; drm 372 drivers/gpu/drm/exynos/exynos_drm_drv.c drm_dev_put(drm); drm 226 drivers/gpu/drm/exynos/exynos_drm_drv.h int exynos_drm_register_dma(struct drm_device *drm, struct device *dev, drm 228 drivers/gpu/drm/exynos/exynos_drm_drv.h void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev, drm 230 drivers/gpu/drm/exynos/exynos_drm_drv.h void exynos_drm_cleanup_dma(struct drm_device *drm); drm 1476 drivers/gpu/drm/exynos/exynos_drm_dsi.c struct drm_device *drm = encoder->dev; drm 1481 drivers/gpu/drm/exynos/exynos_drm_dsi.c ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs, drm 1492 drivers/gpu/drm/exynos/exynos_drm_dsi.c if (!drm->registered) drm 1496 drivers/gpu/drm/exynos/exynos_drm_dsi.c drm_fb_helper_add_one_connector(drm->fb_helper, connector); drm 1517 drivers/gpu/drm/exynos/exynos_drm_dsi.c struct drm_device *drm = encoder->dev; drm 1557 drivers/gpu/drm/exynos/exynos_drm_dsi.c mutex_lock(&drm->mode_config.mutex); drm 1562 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = drm 1565 drivers/gpu/drm/exynos/exynos_drm_dsi.c mutex_unlock(&drm->mode_config.mutex); drm 1567 drivers/gpu/drm/exynos/exynos_drm_dsi.c if (drm->mode_config.poll_enabled) drm 1568 drivers/gpu/drm/exynos/exynos_drm_dsi.c drm_kms_helper_hotplug_event(drm); drm 1577 drivers/gpu/drm/exynos/exynos_drm_dsi.c struct drm_device *drm = dsi->encoder.dev; drm 1580 drivers/gpu/drm/exynos/exynos_drm_dsi.c mutex_lock(&drm->mode_config.mutex); drm 1585 drivers/gpu/drm/exynos/exynos_drm_dsi.c mutex_unlock(&drm->mode_config.mutex); drm 1592 drivers/gpu/drm/exynos/exynos_drm_dsi.c if (drm->mode_config.poll_enabled) drm 1593 drivers/gpu/drm/exynos/exynos_drm_dsi.c drm_kms_helper_hotplug_event(drm); drm 174 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c fsl_dcu_drm_init_planes(fsl_dev->drm); drm 176 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm); drm 180 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL, drm 173 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c ret = drm_mode_config_helper_suspend(fsl_dev->drm); drm 200 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c fsl_dcu_drm_init_planes(fsl_dev->drm); drm 203 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm_mode_config_helper_resume(fsl_dev->drm); drm 242 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c struct drm_device *drm; drm 316 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm = drm_dev_alloc(driver, dev); drm 317 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c if (IS_ERR(drm)) { drm 318 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c ret = PTR_ERR(drm); drm 323 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c fsl_dev->drm = drm; drm 325 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm->dev_private = fsl_dev; drm 328 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c ret = drm_dev_register(drm, 0); drm 332 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm_fbdev_generic_setup(drm, legacyfb_depth); drm 337 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm_dev_put(drm); drm 349 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm_dev_unregister(fsl_dev->drm); drm 350 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c drm_dev_put(fsl_dev->drm); drm 189 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h struct drm_device *drm; drm 26 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c drm_mode_config_init(fsl_dev->drm); drm 28 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c fsl_dev->drm->mode_config.min_width = 0; drm 29 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c fsl_dev->drm->mode_config.min_height = 0; drm 30 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c fsl_dev->drm->mode_config.max_width = 2031; drm 31 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c fsl_dev->drm->mode_config.max_height = 2047; drm 32 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c fsl_dev->drm->mode_config.funcs = &fsl_dcu_drm_mode_config_funcs; drm 46 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c drm_mode_config_reset(fsl_dev->drm); drm 47 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c drm_kms_helper_poll_init(fsl_dev->drm); drm 52 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c drm_mode_config_cleanup(fsl_dev->drm); drm 40 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c ret = drm_encoder_init(fsl_dev->drm, encoder, &encoder_funcs, drm 96 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c ret = drm_connector_init(fsl_dev->drm, connector, drm 1331 drivers/gpu/drm/i2c/tda998x_drv.c struct drm_device *drm) drm 1345 drivers/gpu/drm/i2c/tda998x_drv.c ret = drm_connector_init(drm, connector, &tda998x_connector_funcs, drm 2003 drivers/gpu/drm/i2c/tda998x_drv.c static int tda998x_encoder_init(struct device *dev, struct drm_device *drm) drm 2010 drivers/gpu/drm/i2c/tda998x_drv.c crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); drm 2020 drivers/gpu/drm/i2c/tda998x_drv.c ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, drm 2039 drivers/gpu/drm/i2c/tda998x_drv.c struct drm_device *drm = data; drm 2041 drivers/gpu/drm/i2c/tda998x_drv.c return tda998x_encoder_init(dev, drm); drm 1548 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_device *dev = &dev_priv->drm; drm 375 drivers/gpu/drm/i915/display/intel_atomic.c plane = drm_plane_from_index(&dev_priv->drm, i); drm 808 drivers/gpu/drm/i915/display/intel_audio.c state = drm_atomic_state_alloc(&dev_priv->drm); drm 824 drivers/gpu/drm/i915/display/intel_audio.c ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, drm 1056 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_lock_all(&dev_priv->drm); drm 1063 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_unlock_all(&dev_priv->drm); drm 1074 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_lock_all(&dev_priv->drm); drm 1078 drivers/gpu/drm/i915/display/intel_audio.c drm_modeset_unlock_all(&dev_priv->drm); drm 1108 drivers/gpu/drm/i915/display/intel_audio.c ret = component_add_typed(dev_priv->drm.dev, drm 1132 drivers/gpu/drm/i915/display/intel_audio.c component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); drm 1841 drivers/gpu/drm/i915/display/intel_bios.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 436 drivers/gpu/drm/i915/display/intel_bw.c drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj, drm 95 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 137 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 161 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 254 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 302 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 335 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 379 drivers/gpu/drm/i915/display/intel_cdclk.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1091 drivers/gpu/drm/i915/display/intel_color.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { drm 993 drivers/gpu/drm/i915/display/intel_crt.c drm_connector_init(&dev_priv->drm, &intel_connector->base, drm 996 drivers/gpu/drm/i915/display/intel_crt.c drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, drm 2879 drivers/gpu/drm/i915/display/intel_ddi.c for_each_intel_encoder(&dev_priv->drm, other_encoder) { drm 3953 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->infoframes.drm); drm 4090 drivers/gpu/drm/i915/display/intel_ddi.c ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, drm 4314 drivers/gpu/drm/i915/display/intel_ddi.c drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, drm 1291 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) drm 2164 drivers/gpu/drm/i915/display/intel_display.c lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); drm 3137 drivers/gpu/drm/i915/display/intel_display.c drm_for_each_plane_mask(plane, &dev_priv->drm, drm 4267 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = &dev_priv->drm; drm 4324 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = &dev_priv->drm; drm 4956 drivers/gpu/drm/i915/display/intel_display.c drm_for_each_crtc(crtc, &dev_priv->drm) { drm 6806 drivers/gpu/drm/i915/display/intel_display.c drm_for_each_encoder_mask(encoder, &dev_priv->drm, drm 7050 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { drm 8897 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 9323 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 11723 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { drm 11981 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); drm 12490 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); drm 12492 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); drm 12496 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); drm 12498 drivers/gpu/drm/i915/display/intel_display.c hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); drm 12843 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_INFOFRAME(drm); drm 13047 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 13412 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 13432 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 13913 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_helper_cleanup_planes(&i915->drm, state); drm 14418 drivers/gpu/drm/i915/display/intel_display.c ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); drm 14426 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 14492 drivers/gpu/drm/i915/display/intel_display.c mutex_lock(&dev_priv->drm.struct_mutex); drm 14494 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 14760 drivers/gpu/drm/i915/display/intel_display.c ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); drm 14797 drivers/gpu/drm/i915/display/intel_display.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 14907 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, drm 14913 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, drm 14987 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, drm 15167 drivers/gpu/drm/i915/display/intel_display.c ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, drm 15537 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 15545 drivers/gpu/drm/i915/display/intel_display.c drm_helper_move_panel_connectors_to_head(&dev_priv->drm); drm 15631 drivers/gpu/drm/i915/display/intel_display.c if (!drm_any_plane_has_format(&dev_priv->drm, drm 15677 drivers/gpu/drm/i915/display/intel_display.c drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); drm 15715 drivers/gpu/drm/i915/display/intel_display.c ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); drm 15946 drivers/gpu/drm/i915/display/intel_display.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 16385 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 16633 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane(&dev_priv->drm, plane) { drm 16652 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 16819 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { drm 16843 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 16980 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 16994 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 286 drivers/gpu/drm/i915/display/intel_display_power.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 544 drivers/gpu/drm/i915/display/intel_display_power.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 1206 drivers/gpu/drm/i915/display/intel_display_power.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 1228 drivers/gpu/drm/i915/display/intel_display_power.c if (!dev_priv->drm.dev->power.is_suspended) drm 4246 drivers/gpu/drm/i915/display/intel_display_power.c struct drm_device *dev = &dev_priv->drm; drm 956 drivers/gpu/drm/i915/display/intel_display_types.h union hdmi_infoframe drm; drm 1510 drivers/gpu/drm/i915/display/intel_display_types.h drm_wait_one_vblank(&dev_priv->drm, pipe); drm 805 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_dp(&dev_priv->drm, encoder) { drm 998 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_dp(&dev_priv->drm, encoder) { drm 3523 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_dp(&dev_priv->drm, encoder) { drm 4809 drivers/gpu/drm/i915/display/intel_dp.c ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, drm 4984 drivers/gpu/drm/i915/display/intel_dp.c drm_kms_helper_hotplug_event(&dev_priv->drm); drm 5358 drivers/gpu/drm/i915/display/intel_dp.c WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); drm 7003 drivers/gpu/drm/i915/display/intel_dp.c struct drm_device *dev = &dev_priv->drm; drm 7275 drivers/gpu/drm/i915/display/intel_dp.c if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, drm 7346 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 7366 drivers/gpu/drm/i915/display/intel_dp.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 674 drivers/gpu/drm/i915/display/intel_dp_mst.c ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, drm 320 drivers/gpu/drm/i915/display/intel_dsi_vbt.c gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, drm 501 drivers/gpu/drm/i915/display/intel_dvo.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, drm 514 drivers/gpu/drm/i915/display/intel_dvo.c drm_connector_init(&dev_priv->drm, connector, drm 521 drivers/gpu/drm/i915/display/intel_dvo.c drm_connector_init(&dev_priv->drm, connector, drm 1262 drivers/gpu/drm/i915/display/intel_fbc.c for_each_intel_crtc(&dev_priv->drm, crtc) drm 171 drivers/gpu/drm/i915/display/intel_fbdev.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 437 drivers/gpu/drm/i915/display/intel_fbdev.c fbdev_suspend_work)->drm, drm 299 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, drm 344 drivers/gpu/drm/i915/display/intel_fifo_underrun.c ibx_set_fifo_underrun_reporting(&dev_priv->drm, drm 348 drivers/gpu/drm/i915/display/intel_fifo_underrun.c cpt_set_fifo_underrun_reporting(&dev_priv->drm, drm 423 drivers/gpu/drm/i915/display/intel_fifo_underrun.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 450 drivers/gpu/drm/i915/display/intel_fifo_underrun.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 834 drivers/gpu/drm/i915/display/intel_gmbus.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1799 drivers/gpu/drm/i915/display/intel_hdcp.c ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops, drm 1932 drivers/gpu/drm/i915/display/intel_hdcp.c component_del(dev_priv->drm.dev, &i915_hdcp_component_ops); drm 806 drivers/gpu/drm/i915/display/intel_hdmi.c struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; drm 1223 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.drm); drm 3179 drivers/gpu/drm/i915/display/intel_hdmi.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, drm 187 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; drm 236 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; drm 323 drivers/gpu/drm/i915/display/intel_hotplug.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 363 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; drm 470 drivers/gpu/drm/i915/display/intel_hotplug.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 602 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = &dev_priv->drm; drm 81 drivers/gpu/drm/i915/display/intel_lpe_audio.c struct drm_device *dev = &dev_priv->drm; drm 756 drivers/gpu/drm/i915/display/intel_lvds.c for_each_intel_encoder(&dev_priv->drm, encoder) { drm 814 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_device *dev = &dev_priv->drm; drm 274 drivers/gpu/drm/i915/display/intel_opregion.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 449 drivers/gpu/drm/i915/display/intel_opregion.c struct drm_device *dev = &dev_priv->drm; drm 724 drivers/gpu/drm/i915/display/intel_opregion.c drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); drm 770 drivers/gpu/drm/i915/display/intel_opregion.c drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); drm 868 drivers/gpu/drm/i915/display/intel_opregion.c ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); drm 898 drivers/gpu/drm/i915/display/intel_opregion.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 201 drivers/gpu/drm/i915/display/intel_overlay.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 442 drivers/gpu/drm/i915/display/intel_overlay.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 754 drivers/gpu/drm/i915/display/intel_overlay.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 755 drivers/gpu/drm/i915/display/intel_overlay.c WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); drm 855 drivers/gpu/drm/i915/display/intel_overlay.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 856 drivers/gpu/drm/i915/display/intel_overlay.c WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); drm 1306 drivers/gpu/drm/i915/display/intel_overlay.c mutex_lock(&i915->drm.struct_mutex); drm 1335 drivers/gpu/drm/i915/display/intel_overlay.c mutex_unlock(&i915->drm.struct_mutex); drm 1341 drivers/gpu/drm/i915/display/intel_overlay.c mutex_unlock(&i915->drm.struct_mutex); drm 95 drivers/gpu/drm/i915/display/intel_panel.c downclock_mode = drm_mode_duplicate(&dev_priv->drm, best_mode); drm 121 drivers/gpu/drm/i915/display/intel_panel.c fixed_mode = drm_mode_duplicate(&dev_priv->drm, scan); drm 135 drivers/gpu/drm/i915/display/intel_panel.c fixed_mode = drm_mode_duplicate(&dev_priv->drm, scan); drm 158 drivers/gpu/drm/i915/display/intel_panel.c fixed_mode = drm_mode_duplicate(&dev_priv->drm, drm 563 drivers/gpu/drm/i915/display/intel_panel.c pci_read_config_byte(dev_priv->drm.pdev, LBPC, &lbpc); drm 636 drivers/gpu/drm/i915/display/intel_panel.c pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); drm 859 drivers/gpu/drm/i915/display/intel_panel.c if (dev_priv->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) { drm 77 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_device *dev = &dev_priv->drm; drm 297 drivers/gpu/drm/i915/display/intel_pipe_crc.c state = drm_atomic_state_alloc(&dev_priv->drm); drm 1002 drivers/gpu/drm/i915/display/intel_psr.c struct drm_device *dev = &dev_priv->drm; drm 153 drivers/gpu/drm/i915/display/intel_quirks.c struct pci_dev *d = i915->drm.pdev; drm 3216 drivers/gpu/drm/i915/display/intel_sdvo.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 3264 drivers/gpu/drm/i915/display/intel_sdvo.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, drm 2488 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, drm 2613 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, drm 1864 drivers/gpu/drm/i915/display/intel_tv.c struct drm_device *dev = &dev_priv->drm; drm 1814 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_device *dev = &dev_priv->drm; drm 177 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c mutex_lock(&i915->drm.struct_mutex); drm 233 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c mutex_unlock(&i915->drm.struct_mutex); drm 312 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&ctx->i915->drm.struct_mutex); drm 341 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&i915->drm.struct_mutex); drm 352 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&i915->drm.struct_mutex); drm 367 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 369 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 527 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 659 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&i915->drm.struct_mutex); drm 724 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 726 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 879 drivers/gpu/drm/i915/gem/i915_gem_context.c lockdep_assert_held(&i915->drm.struct_mutex); drm 945 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex); drm 950 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_unlock(&ctx->i915->drm.struct_mutex); drm 1070 drivers/gpu/drm/i915/gem/i915_gem_context.c err = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex); drm 1100 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_unlock(&ctx->i915->drm.struct_mutex); drm 1193 drivers/gpu/drm/i915/gem/i915_gem_context.c ret = mutex_lock_interruptible(&i915->drm.struct_mutex); drm 1199 drivers/gpu/drm/i915/gem/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 392 drivers/gpu/drm/i915/gem/i915_gem_domain.c ret = mutex_lock_interruptible(&i915->drm.struct_mutex); drm 401 drivers/gpu/drm/i915/gem/i915_gem_domain.c mutex_unlock(&i915->drm.struct_mutex); drm 1682 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c struct drm_device *dev = &eb->i915->drm; drm 2182 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c err = mutex_lock_interruptible(&eb->i915->drm.struct_mutex); drm 2187 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c mutex_unlock(&eb->i915->drm.struct_mutex); drm 2198 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c mutex_lock(&eb->i915->drm.struct_mutex); drm 2200 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c mutex_unlock(&eb->i915->drm.struct_mutex); drm 188 drivers/gpu/drm/i915/gem/i915_gem_internal.c drm_gem_private_object_init(&i915->drm, &obj->base, size); drm 162 drivers/gpu/drm/i915/gem/i915_gem_object.c mutex_lock(&i915->drm.struct_mutex); drm 172 drivers/gpu/drm/i915/gem/i915_gem_object.c mutex_unlock(&i915->drm.struct_mutex); drm 35 drivers/gpu/drm/i915/gem/i915_gem_pm.c lockdep_assert_held(&i915->drm.struct_mutex); drm 52 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_lock(&i915->drm.struct_mutex); drm 65 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_unlock(&i915->drm.struct_mutex); drm 74 drivers/gpu/drm/i915/gem/i915_gem_pm.c if (mutex_trylock(&i915->drm.struct_mutex)) { drm 76 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_unlock(&i915->drm.struct_mutex); drm 118 drivers/gpu/drm/i915/gem/i915_gem_pm.c dev_err(gt->i915->drm.dev, drm 150 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_lock(&i915->drm.struct_mutex); drm 163 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_unlock(&i915->drm.struct_mutex); drm 241 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_lock(&i915->drm.struct_mutex); drm 263 drivers/gpu/drm/i915/gem/i915_gem_pm.c mutex_unlock(&i915->drm.struct_mutex); drm 268 drivers/gpu/drm/i915/gem/i915_gem_pm.c dev_err(i915->drm.dev, drm 173 drivers/gpu/drm/i915/gem/i915_gem_shmem.c dev_warn(&i915->drm.pdev->dev, drm 444 drivers/gpu/drm/i915/gem/i915_gem_shmem.c drm_gem_private_object_init(&i915->drm, obj, size); drm 23 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c struct mutex *m = &i915->drm.struct_mutex; drm 50 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c mutex_unlock(&i915->drm.struct_mutex); drm 492 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c if (!lockdep_is_held_type(&i915->drm.struct_mutex, -1)) { drm 493 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c mutex_acquire(&i915->drm.struct_mutex.dep_map, drm 508 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c mutex_acquire(&i915->drm.struct_mutex.dep_map, drm 514 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c mutex_release(&i915->drm.struct_mutex.dep_map, 0, _RET_IP_); drm 519 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c mutex_release(&i915->drm.struct_mutex.dep_map, 0, _RET_IP_); drm 122 drivers/gpu/drm/i915/gem/i915_gem_stolen.c r = devm_request_mem_region(dev_priv->drm.dev, dsm->start, drm 135 drivers/gpu/drm/i915/gem/i915_gem_stolen.c r = devm_request_mem_region(dev_priv->drm.dev, dsm->start + 1, drm 366 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_notice(dev_priv->drm.dev, drm 373 drivers/gpu/drm/i915/gem/i915_gem_stolen.c dev_notice(dev_priv->drm.dev, drm 558 drivers/gpu/drm/i915/gem/i915_gem_stolen.c drm_gem_private_object_init(&dev_priv->drm, &obj->base, stolen->size); drm 624 drivers/gpu/drm/i915/gem/i915_gem_stolen.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 215 drivers/gpu/drm/i915/gem/i915_gem_tiling.c lockdep_assert_held(&i915->drm.struct_mutex); drm 133 drivers/gpu/drm/i915/gem/i915_gem_userptr.c unlock = &mn->mm->i915->drm.struct_mutex; drm 113 drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c drm_gem_private_object_init(&i915->drm, &obj->base, dma_size); drm 168 drivers/gpu/drm/i915/gem/selftests/huge_pages.c drm_gem_private_object_init(&i915->drm, &obj->base, size); drm 317 drivers/gpu/drm/i915/gem/selftests/huge_pages.c drm_gem_private_object_init(&i915->drm, &obj->base, size); drm 1620 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1646 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1647 drivers/gpu/drm/i915/gem/selftests/huge_pages.c drm_dev_put(&dev_priv->drm); drm 1679 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mutex_lock(&i915->drm.struct_mutex); drm 1695 drivers/gpu/drm/i915/gem/selftests/huge_pages.c mutex_unlock(&i915->drm.struct_mutex); drm 302 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c mutex_lock(&i915->drm.struct_mutex); drm 382 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c mutex_unlock(&i915->drm.struct_mutex); drm 55 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 154 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 385 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 447 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 481 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 565 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 567 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 573 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 948 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 1004 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 1064 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 1143 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 1390 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 1461 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 1509 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_lock(&i915->drm.struct_mutex); drm 1589 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c mutex_unlock(&i915->drm.struct_mutex); drm 1609 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c drm_dev_put(&i915->drm); drm 55 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c import = i915_gem_prime_import(&i915->drm, dmabuf); drm 92 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c obj = to_intel_bo(i915_gem_prime_import(&i915->drm, dmabuf)); drm 100 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c if (obj->base.dev != &i915->drm) { drm 183 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c obj = to_intel_bo(i915_gem_prime_import(&i915->drm, dmabuf)); drm 376 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c drm_dev_put(&i915->drm); drm 208 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c mutex_lock(&i915->drm.struct_mutex); drm 321 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c mutex_unlock(&i915->drm.struct_mutex); drm 400 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c mutex_lock(&i915->drm.struct_mutex); drm 402 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c mutex_unlock(&i915->drm.struct_mutex); drm 408 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c __acquires(&i915->drm.vma_offset_manager->vm_lock) drm 410 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c write_lock(&i915->drm.vma_offset_manager->vm_lock); drm 414 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c __releases(&i915->drm.vma_offset_manager->vm_lock) drm 416 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c write_unlock(&i915->drm.vma_offset_manager->vm_lock); drm 422 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c struct drm_mm *mm = &i915->drm.vma_offset_manager->vm_addr_space_mm; drm 493 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c mutex_lock(&i915->drm.struct_mutex); drm 495 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c mutex_unlock(&i915->drm.struct_mutex); drm 88 drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c drm_dev_put(&i915->drm); drm 68 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c mutex_lock(&i915->drm.struct_mutex); drm 70 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c mutex_unlock(&i915->drm.struct_mutex); drm 169 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c mutex_lock(&i915->drm.struct_mutex); drm 171 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c mutex_unlock(&i915->drm.struct_mutex); drm 28 drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c mutex_lock(&i915->drm.struct_mutex); drm 30 drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c mutex_unlock(&i915->drm.struct_mutex); drm 78 drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c drm_dev_put(&i915->drm); drm 85 drivers/gpu/drm/i915/gem/selftests/mock_context.c lockdep_assert_held(&i915->drm.struct_mutex); drm 1054 drivers/gpu/drm/i915/gt/intel_engine_cs.c synchronize_hardirq(engine->i915->drm.pdev->irq); drm 161 drivers/gpu/drm/i915/gt/intel_gt_pm.c dev_err(gt->i915->drm.dev, drm 314 drivers/gpu/drm/i915/gt/intel_hangcheck.c dev_err(gt->i915->drm.dev, drm 1747 drivers/gpu/drm/i915/gt/intel_lrc.c dev_err_once(engine->i915->drm.dev, drm 149 drivers/gpu/drm/i915/gt/intel_reset.c struct pci_dev *pdev = gt->i915->drm.pdev; drm 178 drivers/gpu/drm/i915/gt/intel_reset.c struct pci_dev *pdev = gt->i915->drm.pdev; drm 188 drivers/gpu/drm/i915/gt/intel_reset.c struct pci_dev *pdev = gt->i915->drm.pdev; drm 642 drivers/gpu/drm/i915/gt/intel_reset.c unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping, drm 938 drivers/gpu/drm/i915/gt/intel_reset.c dev_notice(gt->i915->drm.dev, drm 946 drivers/gpu/drm/i915/gt/intel_reset.c dev_err(gt->i915->drm.dev, "GPU reset not supported\n"); drm 956 drivers/gpu/drm/i915/gt/intel_reset.c dev_err(gt->i915->drm.dev, "Failed to reset chip\n"); drm 1043 drivers/gpu/drm/i915/gt/intel_reset.c dev_notice(engine->i915->drm.dev, drm 1084 drivers/gpu/drm/i915/gt/intel_reset.c struct kobject *kobj = >->i915->drm.primary->kdev->kobj; drm 1255 drivers/gpu/drm/i915/gt/intel_reset.c if (mutex_is_locked(>->i915->drm.struct_mutex)) drm 1282 drivers/gpu/drm/i915/gt/intel_reset.c dev_err(w->gt->i915->drm.dev, drm 156 drivers/gpu/drm/i915/gt/selftest_context.c mutex_lock(>->i915->drm.struct_mutex); drm 203 drivers/gpu/drm/i915/gt/selftest_context.c mutex_unlock(>->i915->drm.struct_mutex); drm 306 drivers/gpu/drm/i915/gt/selftest_context.c mutex_lock(>->i915->drm.struct_mutex); drm 325 drivers/gpu/drm/i915/gt/selftest_context.c mutex_unlock(>->i915->drm.struct_mutex); drm 419 drivers/gpu/drm/i915/gt/selftest_context.c mutex_lock(>->i915->drm.struct_mutex); drm 438 drivers/gpu/drm/i915/gt/selftest_context.c mutex_unlock(>->i915->drm.struct_mutex); drm 312 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 359 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 386 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 388 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 398 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 420 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 438 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 440 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 468 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 470 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 497 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 510 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 541 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 543 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 566 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 568 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 596 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 600 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 606 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 609 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 659 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 661 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 728 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(&engine->i915->drm.struct_mutex); drm 730 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(&engine->i915->drm.struct_mutex); drm 744 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(&engine->i915->drm.struct_mutex); drm 747 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(&engine->i915->drm.struct_mutex); drm 758 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(&engine->i915->drm.struct_mutex); drm 798 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 800 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 858 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 862 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 868 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 871 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 896 drivers/gpu/drm/i915/gt/selftest_hangcheck.c drm_info_printer(gt->i915->drm.dev); drm 916 drivers/gpu/drm/i915/gt/selftest_hangcheck.c drm_info_printer(gt->i915->drm.dev); drm 980 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 982 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 991 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 993 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1064 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1079 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 1112 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1136 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(&i915->drm.struct_mutex); drm 1138 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(&i915->drm.struct_mutex); drm 1151 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(&i915->drm.struct_mutex); drm 1176 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(&i915->drm.struct_mutex); drm 1199 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1265 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1268 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 1291 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 1315 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1323 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1350 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1352 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1406 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1465 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 1529 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1556 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1572 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct drm_printer p = drm_info_printer(gt->i915->drm.dev); drm 1584 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1593 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1606 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1699 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1721 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 1761 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_lock(>->i915->drm.struct_mutex); drm 1763 drivers/gpu/drm/i915/gt/selftest_hangcheck.c mutex_unlock(>->i915->drm.struct_mutex); drm 35 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 78 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 243 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 297 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 319 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 447 drivers/gpu/drm/i915/gt/selftest_lrc.c struct drm_printer p = drm_info_printer(i915->drm.dev); drm 480 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 518 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 604 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 622 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 710 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 766 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 846 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 885 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 962 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 1041 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 1133 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 1162 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 1240 drivers/gpu/drm/i915/gt/selftest_lrc.c drm_info_printer(i915->drm.dev); drm 1256 drivers/gpu/drm/i915/gt/selftest_lrc.c drm_info_printer(i915->drm.dev); drm 1279 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 1306 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 1404 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 1492 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&smoke->i915->drm.struct_mutex); drm 1496 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&smoke->i915->drm.struct_mutex); drm 1517 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&smoke->i915->drm.struct_mutex); drm 1551 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&smoke->i915->drm.struct_mutex); drm 1610 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&smoke.i915->drm.struct_mutex); drm 1665 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&smoke.i915->drm.struct_mutex); drm 1808 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 1845 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 1955 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 1976 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 2133 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_lock(&i915->drm.struct_mutex); drm 2163 drivers/gpu/drm/i915/gt/selftest_lrc.c mutex_unlock(&i915->drm.struct_mutex); drm 139 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_lock(&state.i915->drm.struct_mutex); drm 152 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_unlock(&state.i915->drm.struct_mutex); drm 155 drivers/gpu/drm/i915/gt/selftest_timeline.c drm_dev_put(&state.i915->drm); drm 452 drivers/gpu/drm/i915/gt/selftest_timeline.c lockdep_assert_held(&tl->gt->i915->drm.struct_mutex); /* lazy rq refs */ drm 518 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_lock(&i915->drm.struct_mutex); drm 563 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_unlock(&i915->drm.struct_mutex); drm 594 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_lock(&i915->drm.struct_mutex); drm 639 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_unlock(&i915->drm.struct_mutex); drm 661 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_lock(&i915->drm.struct_mutex); drm 758 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_unlock(&i915->drm.struct_mutex); drm 778 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_lock(&i915->drm.struct_mutex); drm 828 drivers/gpu/drm/i915/gt/selftest_timeline.c mutex_unlock(&i915->drm.struct_mutex); drm 697 drivers/gpu/drm/i915/gt/selftest_workarounds.c mutex_unlock(&i915->drm.struct_mutex); drm 699 drivers/gpu/drm/i915/gt/selftest_workarounds.c mutex_lock(&i915->drm.struct_mutex); drm 721 drivers/gpu/drm/i915/gt/selftest_workarounds.c mutex_unlock(&i915->drm.struct_mutex); drm 723 drivers/gpu/drm/i915/gt/selftest_workarounds.c mutex_lock(&i915->drm.struct_mutex); drm 1254 drivers/gpu/drm/i915/gt/selftest_workarounds.c mutex_lock(&i915->drm.struct_mutex); drm 1256 drivers/gpu/drm/i915/gt/selftest_workarounds.c mutex_unlock(&i915->drm.struct_mutex); drm 305 drivers/gpu/drm/i915/gt/uc/intel_guc.c DRM_DEV_DEBUG_DRIVER(gt->i915->drm.dev, "failed with %d\n", ret); drm 195 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev, drm 389 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c dev_priv->drm.primary->debugfs_root, drm 526 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c mutex_lock(&dev_priv->drm.struct_mutex); drm 544 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 102 drivers/gpu/drm/i915/gt/uc/intel_huc.c DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "failed with %d\n", err); drm 45 drivers/gpu/drm/i915/gt/uc/intel_uc.c DRM_DEV_DEBUG_DRIVER(i915->drm.dev, drm 63 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_info(i915->drm.dev, drm 69 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_info(i915->drm.dev, drm 75 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_info(i915->drm.dev, drm 81 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_info(i915->drm.dev, drm 491 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n", drm 498 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n", drm 519 drivers/gpu/drm/i915/gt/uc/intel_uc.c dev_notice(i915->drm.dev, "GuC is uninitialized\n"); drm 29 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c DRM_DEV_DEBUG_DRIVER(__uc_fw_to_gt(uc_fw)->i915->drm.dev, drm 262 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c struct device *dev = i915->drm.dev; drm 478 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c dev_err(gt->i915->drm.dev, "DMA for %s fw failed, DMA_CTRL=%u\n", drm 119 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_lock(&dev_priv->drm.struct_mutex); drm 193 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 211 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_lock(&dev_priv->drm.struct_mutex); drm 302 drivers/gpu/drm/i915/gt/uc/selftest_guc.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 64 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->drm.struct_mutex); drm 71 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 101 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->drm.struct_mutex); drm 103 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 111 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_lock(&dev_priv->drm.struct_mutex); drm 114 drivers/gpu/drm/i915/gvt/aperture_gm.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 394 drivers/gpu/drm/i915/gvt/cfg_space.c pci_resource_len(gvt->dev_priv->drm.pdev, 0); drm 396 drivers/gpu/drm/i915/gvt/cfg_space.c pci_resource_len(gvt->dev_priv->drm.pdev, 2); drm 223 drivers/gpu/drm/i915/gvt/debugfs.c struct drm_minor *minor = gvt->dev_priv->drm.primary; drm 363 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_device *dev = &vgpu->gvt->dev_priv->drm; drm 469 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_device *dev = &vgpu->gvt->dev_priv->drm; drm 81 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = gvt->dev_priv->drm.pdev; drm 132 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = gvt->dev_priv->drm.pdev; drm 157 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 212 drivers/gpu/drm/i915/gvt/firmware.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 247 drivers/gpu/drm/i915/gvt/firmware.c ret = request_firmware(&fw, path, &dev_priv->drm.pdev->dev); drm 737 drivers/gpu/drm/i915/gvt/gtt.c struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev; drm 822 drivers/gpu/drm/i915/gvt/gtt.c struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev; drm 2356 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; drm 2413 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; drm 2685 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &gvt->dev_priv->drm.pdev->dev; drm 2734 drivers/gpu/drm/i915/gvt/gtt.c struct device *dev = &gvt->dev_priv->drm.pdev->dev; drm 55 drivers/gpu/drm/i915/gvt/gvt.c &gvt->dev_priv->drm.pdev->dev); drm 194 drivers/gpu/drm/i915/gvt/gvt.c struct pci_dev *pdev = gvt->dev_priv->drm.pdev; drm 382 drivers/gpu/drm/i915/gvt/gvt.c intel_gvt_host.dev = &dev_priv->drm.pdev->dev; drm 1240 drivers/gpu/drm/i915/gvt/handlers.c struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; drm 190 drivers/gpu/drm/i915/gvt/kvmgt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; drm 213 drivers/gpu/drm/i915/gvt/kvmgt.c struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; drm 395 drivers/gpu/drm/i915/gvt/scheduler.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 425 drivers/gpu/drm/i915/gvt/scheduler.c lockdep_assert_held(&dev_priv->drm.struct_mutex); drm 597 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&dev_priv->drm.struct_mutex); drm 617 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 701 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&dev_priv->drm.struct_mutex); drm 736 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1243 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&i915->drm.struct_mutex); drm 1299 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&i915->drm.struct_mutex); drm 1313 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&i915->drm.struct_mutex); drm 1604 drivers/gpu/drm/i915/gvt/scheduler.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1606 drivers/gpu/drm/i915/gvt/scheduler.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 15 drivers/gpu/drm/i915/i915_active.c #define BKL(ref) (&(ref)->i915->drm.struct_mutex) drm 455 drivers/gpu/drm/i915/i915_active.c i915_active_request_raw(active, &rq->i915->drm.struct_mutex); drm 366 drivers/gpu/drm/i915/i915_debugfs.c ret = mutex_lock_interruptible(&i915->drm.struct_mutex); drm 371 drivers/gpu/drm/i915/i915_debugfs.c mutex_unlock(&i915->drm.struct_mutex); drm 1482 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 1512 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 1568 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2314 drivers/gpu/drm/i915/i915_debugfs.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 2327 drivers/gpu/drm/i915/i915_debugfs.c atomic_read(&dev_priv->drm.dev->power.usage_count)); drm 2436 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2463 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2646 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2720 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2827 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2956 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 2967 drivers/gpu/drm/i915/i915_debugfs.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 3070 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3094 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3184 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3234 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3278 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3310 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3427 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 3620 drivers/gpu/drm/i915/i915_debugfs.c ret = mutex_lock_interruptible(&i915->drm.struct_mutex); drm 3645 drivers/gpu/drm/i915/i915_debugfs.c mutex_unlock(&i915->drm.struct_mutex); drm 4165 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 4239 drivers/gpu/drm/i915/i915_debugfs.c struct drm_device *dev = &dev_priv->drm; drm 4368 drivers/gpu/drm/i915/i915_debugfs.c struct drm_minor *minor = dev_priv->drm.primary; drm 147 drivers/gpu/drm/i915/i915_drv.c int domain = pci_domain_nr(dev_priv->drm.pdev->bus); drm 301 drivers/gpu/drm/i915/i915_drv.c i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING; drm 305 drivers/gpu/drm/i915/i915_drv.c i915->drm.switch_power_state = DRM_SWITCH_POWER_ON; drm 308 drivers/gpu/drm/i915/i915_drv.c i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING; drm 310 drivers/gpu/drm/i915/i915_drv.c i915->drm.switch_power_state = DRM_SWITCH_POWER_OFF; drm 323 drivers/gpu/drm/i915/i915_drv.c return i915 && i915->drm.open_count == 0; drm 335 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 342 drivers/gpu/drm/i915/i915_drv.c ret = drm_vblank_init(&dev_priv->drm, drm 425 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1194 drivers/gpu/drm/i915/i915_drv.c dev_info(dev_priv->drm.dev, drm 1207 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1377 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1396 drivers/gpu/drm/i915/i915_drv.c struct drm_device *dev = &dev_priv->drm; drm 1466 drivers/gpu/drm/i915/i915_drv.c drm_kms_helper_poll_fini(&dev_priv->drm); drm 1476 drivers/gpu/drm/i915/i915_drv.c drm_dev_unplug(&dev_priv->drm); drm 1519 drivers/gpu/drm/i915/i915_drv.c err = drm_dev_init(&i915->drm, &driver, &pdev->dev); drm 1525 drivers/gpu/drm/i915/i915_drv.c i915->drm.dev_private = i915; drm 1527 drivers/gpu/drm/i915/i915_drv.c i915->drm.pdev = pdev; drm 1542 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = i915->drm.pdev; drm 1544 drivers/gpu/drm/i915/i915_drv.c drm_dev_fini(&i915->drm); drm 1575 drivers/gpu/drm/i915/i915_drv.c dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; drm 1597 drivers/gpu/drm/i915/i915_drv.c ret = i915_driver_modeset_probe(&dev_priv->drm); drm 1630 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = i915->drm.pdev; drm 1648 drivers/gpu/drm/i915/i915_drv.c drm_atomic_helper_shutdown(&i915->drm); drm 1652 drivers/gpu/drm/i915/i915_drv.c intel_modeset_driver_remove(&i915->drm); drm 1744 drivers/gpu/drm/i915/i915_drv.c struct drm_device *dev = &dev_priv->drm; drm 1785 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1842 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 1902 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 1905 drivers/gpu/drm/i915/i915_drv.c error = i915_drm_suspend(&i915->drm); drm 1909 drivers/gpu/drm/i915/i915_drv.c return i915_drm_suspend_late(&i915->drm, false); drm 1926 drivers/gpu/drm/i915/i915_drv.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1929 drivers/gpu/drm/i915/i915_drv.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1990 drivers/gpu/drm/i915/i915_drv.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 2068 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2071 drivers/gpu/drm/i915/i915_drv.c ret = i915_drm_resume_early(&i915->drm); drm 2075 drivers/gpu/drm/i915/i915_drv.c return i915_drm_resume(&i915->drm); drm 2087 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2090 drivers/gpu/drm/i915/i915_drv.c return i915_drm_prepare(&i915->drm); drm 2102 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2105 drivers/gpu/drm/i915/i915_drv.c return i915_drm_suspend(&i915->drm); drm 2121 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2124 drivers/gpu/drm/i915/i915_drv.c return i915_drm_suspend_late(&i915->drm, false); drm 2131 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2134 drivers/gpu/drm/i915/i915_drv.c return i915_drm_suspend_late(&i915->drm, true); drm 2141 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2144 drivers/gpu/drm/i915/i915_drv.c return i915_drm_resume_early(&i915->drm); drm 2151 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) drm 2154 drivers/gpu/drm/i915/i915_drv.c return i915_drm_resume(&i915->drm); drm 2163 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { drm 2164 drivers/gpu/drm/i915/i915_drv.c ret = i915_drm_suspend(&i915->drm); drm 2181 drivers/gpu/drm/i915/i915_drv.c if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { drm 2182 drivers/gpu/drm/i915/i915_drv.c ret = i915_drm_suspend_late(&i915->drm, true); drm 1283 drivers/gpu/drm/i915/i915_drv.h struct drm_device drm; drm 1778 drivers/gpu/drm/i915/i915_drv.h return container_of(dev, struct drm_i915_private, drm); drm 1843 drivers/gpu/drm/i915/i915_drv.h #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) drm 341 drivers/gpu/drm/i915/i915_gem.c ret = mutex_lock_interruptible(&i915->drm.struct_mutex); drm 362 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 417 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 426 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 534 drivers/gpu/drm/i915/i915_gem.c ret = mutex_lock_interruptible(&i915->drm.struct_mutex); drm 572 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 637 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 648 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 950 drivers/gpu/drm/i915/i915_gem.c lockdep_assert_held(&i915->drm.struct_mutex); drm 1304 drivers/gpu/drm/i915/i915_gem.c dev_notice(i915->drm.dev, drm 1447 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1522 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1533 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1541 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1558 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1567 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1586 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1617 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1620 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1627 drivers/gpu/drm/i915/i915_gem.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1631 drivers/gpu/drm/i915/i915_gem.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 107 drivers/gpu/drm/i915/i915_gem_evict.c lockdep_assert_held(&vm->i915->drm.struct_mutex); drm 272 drivers/gpu/drm/i915/i915_gem_evict.c lockdep_assert_held(&vm->i915->drm.struct_mutex); drm 378 drivers/gpu/drm/i915/i915_gem_evict.c lockdep_assert_held(&vm->i915->drm.struct_mutex); drm 507 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_lock(&vm->i915->drm.struct_mutex); drm 514 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_unlock(&vm->i915->drm.struct_mutex); drm 1436 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->vm.dma = &i915->drm.pdev->dev; drm 1794 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 1796 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 2531 drivers/gpu/drm/i915/i915_gem_gtt.c struct device *kdev = &dev_priv->drm.pdev->dev; drm 2622 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 2634 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 2759 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 2776 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 2840 drivers/gpu/drm/i915/i915_gem_gtt.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 2984 drivers/gpu/drm/i915/i915_gem_gtt.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 3042 drivers/gpu/drm/i915/i915_gem_gtt.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 3109 drivers/gpu/drm/i915/i915_gem_gtt.c ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); drm 3135 drivers/gpu/drm/i915/i915_gem_gtt.c dev_notice(dev_priv->drm.dev, drm 3148 drivers/gpu/drm/i915/i915_gem_gtt.c ggtt->vm.dma = &i915->drm.pdev->dev; drm 3197 drivers/gpu/drm/i915/i915_gem_gtt.c dev_info(i915->drm.dev, "VT-d active for gfx access\n"); drm 3207 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 3232 drivers/gpu/drm/i915/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 3731 drivers/gpu/drm/i915/i915_gem_gtt.c lockdep_assert_held(&vm->i915->drm.struct_mutex); drm 25 drivers/gpu/drm/i915/i915_getparam.c value = i915->drm.pdev->device; drm 28 drivers/gpu/drm/i915/i915_getparam.c value = i915->drm.pdev->revision; drm 615 drivers/gpu/drm/i915/i915_gpu_error.c struct pci_dev *pdev = i915->drm.pdev; drm 1752 drivers/gpu/drm/i915/i915_gpu_error.c dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg)); drm 1776 drivers/gpu/drm/i915/i915_gpu_error.c i915->drm.primary->index); drm 763 drivers/gpu/drm/i915/i915_irq.c struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; drm 1291 drivers/gpu/drm/i915/i915_irq.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1327 drivers/gpu/drm/i915/i915_irq.c kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, drm 1347 drivers/gpu/drm/i915/i915_irq.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1788 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 1806 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 1830 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 1856 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 2414 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 2467 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 2756 drivers/gpu/drm/i915/i915_irq.c drm_handle_vblank(&dev_priv->drm, pipe); drm 3368 drivers/gpu/drm/i915/i915_irq.c for_each_intel_encoder(&dev_priv->drm, encoder) drm 4319 drivers/gpu/drm/i915/i915_irq.c struct drm_device *dev = &dev_priv->drm; drm 4503 drivers/gpu/drm/i915/i915_irq.c int irq = dev_priv->drm.pdev->irq; drm 4513 drivers/gpu/drm/i915/i915_irq.c dev_priv->drm.irq_enabled = true; drm 4520 drivers/gpu/drm/i915/i915_irq.c dev_priv->drm.irq_enabled = false; drm 4538 drivers/gpu/drm/i915/i915_irq.c int irq = dev_priv->drm.pdev->irq; drm 4546 drivers/gpu/drm/i915/i915_irq.c if (!dev_priv->drm.irq_enabled) drm 4549 drivers/gpu/drm/i915/i915_irq.c dev_priv->drm.irq_enabled = false; drm 4598 drivers/gpu/drm/i915/i915_irq.c synchronize_irq(i915->drm.pdev->irq); drm 889 drivers/gpu/drm/i915/i915_pci.c drm_dev_put(&i915->drm); drm 1212 drivers/gpu/drm/i915/i915_perf.c err = i915_mutex_lock_interruptible(&i915->drm); drm 1232 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&i915->drm.struct_mutex); drm 1341 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1343 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1352 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&i915->drm.struct_mutex); drm 1357 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&i915->drm.struct_mutex); drm 1372 drivers/gpu/drm/i915/i915_perf.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1375 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1513 drivers/gpu/drm/i915/i915_perf.c ret = i915_mutex_lock_interruptible(&dev_priv->drm); drm 1560 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1894 drivers/gpu/drm/i915/i915_perf.c lockdep_assert_held(&i915->drm.struct_mutex); drm 2257 drivers/gpu/drm/i915/i915_perf.c ret = i915_mutex_lock_interruptible(&dev_priv->drm); drm 2270 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 2283 drivers/gpu/drm/i915/i915_perf.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 2661 drivers/gpu/drm/i915/i915_perf.c drm_dev_put(&dev_priv->drm); drm 2801 drivers/gpu/drm/i915/i915_perf.c drm_dev_get(&dev_priv->drm); drm 3046 drivers/gpu/drm/i915/i915_perf.c &dev_priv->drm.primary->kdev->kobj); drm 286 drivers/gpu/drm/i915/i915_pmu.c struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq); drm 1056 drivers/gpu/drm/i915/i915_pmu.c dev_info(i915->drm.dev, "PMU not supported for this GPU."); drm 65 drivers/gpu/drm/i915/i915_suspend.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 68 drivers/gpu/drm/i915/i915_suspend.c mutex_lock(&dev_priv->drm.struct_mutex); drm 103 drivers/gpu/drm/i915/i915_suspend.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 110 drivers/gpu/drm/i915/i915_suspend.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 113 drivers/gpu/drm/i915/i915_suspend.c mutex_lock(&dev_priv->drm.struct_mutex); drm 148 drivers/gpu/drm/i915/i915_suspend.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 166 drivers/gpu/drm/i915/i915_sysfs.c struct drm_device *dev = &dev_priv->drm; drm 201 drivers/gpu/drm/i915/i915_sysfs.c struct drm_device *dev = &dev_priv->drm; drm 576 drivers/gpu/drm/i915/i915_sysfs.c struct device *kdev = dev_priv->drm.primary->kdev; drm 625 drivers/gpu/drm/i915/i915_sysfs.c struct device *kdev = dev_priv->drm.primary->kdev; drm 35 drivers/gpu/drm/i915/i915_trace.h for_each_intel_crtc(&dev_priv->drm, it__) { drm 62 drivers/gpu/drm/i915/i915_trace.h for_each_intel_crtc(&dev_priv->drm, it__) { drm 158 drivers/gpu/drm/i915/i915_trace.h for_each_intel_crtc(&dev_priv->drm, crtc) { drm 445 drivers/gpu/drm/i915/i915_trace.h __entry->dev = i915->drm.primary->index; drm 605 drivers/gpu/drm/i915/i915_trace.h __entry->dev = vm->i915->drm.primary->index; drm 631 drivers/gpu/drm/i915/i915_trace.h __entry->dev = vm->i915->drm.primary->index; drm 655 drivers/gpu/drm/i915/i915_trace.h __entry->dev = vm->i915->drm.primary->index; drm 677 drivers/gpu/drm/i915/i915_trace.h __entry->dev = rq->i915->drm.primary->index; drm 706 drivers/gpu/drm/i915/i915_trace.h __entry->dev = rq->i915->drm.primary->index; drm 751 drivers/gpu/drm/i915/i915_trace.h __entry->dev = rq->i915->drm.primary->index; drm 782 drivers/gpu/drm/i915/i915_trace.h __entry->dev = rq->i915->drm.primary->index; drm 847 drivers/gpu/drm/i915/i915_trace.h __entry->dev = rq->i915->drm.primary->index; drm 931 drivers/gpu/drm/i915/i915_trace.h __entry->dev = vm->i915->drm.primary->index; drm 966 drivers/gpu/drm/i915/i915_trace.h __entry->dev = ctx->i915->drm.primary->index; drm 990 drivers/gpu/drm/i915/i915_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915 drm 19 drivers/gpu/drm/i915/i915_utils.c struct device *kdev = dev_priv->drm.dev; drm 62 drivers/gpu/drm/i915/i915_vgpu.c struct pci_dev *pdev = dev_priv->drm.pdev; drm 355 drivers/gpu/drm/i915/i915_vma.c lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); drm 404 drivers/gpu/drm/i915/i915_vma.c lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); drm 718 drivers/gpu/drm/i915/i915_vma.c lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); drm 823 drivers/gpu/drm/i915/i915_vma.c lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); drm 876 drivers/gpu/drm/i915/i915_vma.c unmap_mapping_range(vma->vm->i915->drm.anon_inode->i_mapping, drm 937 drivers/gpu/drm/i915/i915_vma.c lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); drm 632 drivers/gpu/drm/i915/intel_csr.c request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev); drm 644 drivers/gpu/drm/i915/intel_csr.c dev_notice(dev_priv->drm.dev, drm 648 drivers/gpu/drm/i915/intel_csr.c dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s", drm 850 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 1507 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 1529 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 2114 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 2133 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 3263 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, intel_crtc) { drm 3409 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, intel_crtc) { drm 5288 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { drm 5360 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { drm 5376 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { drm 5572 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { drm 5687 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 5813 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 5995 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 6077 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane(&dev_priv->drm, plane) { drm 6112 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 6171 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 6230 drivers/gpu/drm/i915/intel_pm.c for_each_intel_plane(&dev_priv->drm, plane) { drm 6258 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) { drm 6295 drivers/gpu/drm/i915/intel_pm.c for_each_intel_crtc(&dev_priv->drm, crtc) drm 8322 drivers/gpu/drm/i915/intel_pm.c if (!kref_get_unless_zero(&i915->drm.ref)) drm 8353 drivers/gpu/drm/i915/intel_pm.c drm_dev_put(&i915->drm); drm 8376 drivers/gpu/drm/i915/intel_pm.c drm_dev_put(&i915->drm); drm 8400 drivers/gpu/drm/i915/intel_pm.c drm_dev_put(&i915->drm); drm 8421 drivers/gpu/drm/i915/intel_pm.c drm_dev_put(&i915->drm); drm 8446 drivers/gpu/drm/i915/intel_pm.c drm_dev_put(&i915->drm); drm 8659 drivers/gpu/drm/i915/intel_pm.c pm_runtime_get(&dev_priv->drm.pdev->dev); drm 8705 drivers/gpu/drm/i915/intel_pm.c pm_runtime_put(&dev_priv->drm.pdev->dev); drm 612 drivers/gpu/drm/i915/intel_runtime_pm.c struct pci_dev *pdev = i915->drm.pdev; drm 666 drivers/gpu/drm/i915/intel_uncore.c dev_info(uncore->i915->drm.dev, drm 1603 drivers/gpu/drm/i915/intel_uncore.c struct pci_dev *pdev = i915->drm.pdev; drm 1632 drivers/gpu/drm/i915/intel_uncore.c struct pci_dev *pdev = uncore->i915->drm.pdev; drm 89 drivers/gpu/drm/i915/intel_wopcm.c DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "WOPCM: %uK\n", wopcm->size / 1024); drm 115 drivers/gpu/drm/i915/intel_wopcm.c dev_err(i915->drm.dev, drm 134 drivers/gpu/drm/i915/intel_wopcm.c dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", drm 169 drivers/gpu/drm/i915/intel_wopcm.c dev_err(i915->drm.dev, drm 178 drivers/gpu/drm/i915/intel_wopcm.c dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", drm 186 drivers/gpu/drm/i915/intel_wopcm.c dev_err(i915->drm.dev, "WOPCM: no space for %s: %uK < %uK\n", drm 245 drivers/gpu/drm/i915/intel_wopcm.c DRM_DEV_DEBUG_DRIVER(i915->drm.dev, drm 269 drivers/gpu/drm/i915/intel_wopcm.c DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "Calculated GuC WOPCM [%uK, %uK)\n", drm 154 drivers/gpu/drm/i915/selftests/i915_active.c mutex_lock(&i915->drm.struct_mutex); drm 176 drivers/gpu/drm/i915/selftests/i915_active.c mutex_unlock(&i915->drm.struct_mutex); drm 190 drivers/gpu/drm/i915/selftests/i915_active.c mutex_lock(&i915->drm.struct_mutex); drm 212 drivers/gpu/drm/i915/selftests/i915_active.c mutex_unlock(&i915->drm.struct_mutex); drm 122 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 125 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 143 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 147 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 162 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 164 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 182 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 186 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 201 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_lock(&i915->drm.struct_mutex); drm 203 drivers/gpu/drm/i915/selftests/i915_gem.c mutex_unlock(&i915->drm.struct_mutex); drm 130 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_unlock(&i915->drm.struct_mutex); drm 134 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_lock(&i915->drm.struct_mutex); drm 411 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_lock(&i915->drm.struct_mutex); drm 448 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_unlock(&i915->drm.struct_mutex); drm 463 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_lock(&i915->drm.struct_mutex); drm 500 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_unlock(&i915->drm.struct_mutex); drm 511 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_lock(&i915->drm.struct_mutex); drm 526 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_unlock(&i915->drm.struct_mutex); drm 548 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_lock(&i915->drm.struct_mutex); drm 552 drivers/gpu/drm/i915/selftests/i915_gem_evict.c mutex_unlock(&i915->drm.struct_mutex); drm 554 drivers/gpu/drm/i915/selftests/i915_gem_evict.c drm_dev_put(&i915->drm); drm 43 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 47 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 128 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c drm_gem_private_object_init(&i915->drm, &obj->base, size); drm 1011 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_lock(&dev_priv->drm.struct_mutex); drm 1024 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_unlock(&dev_priv->drm.struct_mutex); drm 1088 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 1109 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 1151 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 1226 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 1692 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_lock(&i915->drm.struct_mutex); drm 1695 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c mutex_unlock(&i915->drm.struct_mutex); drm 1702 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c drm_dev_put(&i915->drm); drm 48 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 57 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 70 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 130 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 143 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 156 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 185 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 188 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 200 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 236 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 251 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 258 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 285 drivers/gpu/drm/i915/selftests/i915_request.c struct mutex * const BKL = &t->engine->i915->drm.struct_mutex; drm 460 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&t.engine->i915->drm.struct_mutex); drm 468 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&t.engine->i915->drm.struct_mutex); drm 498 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&t.engine->i915->drm.struct_mutex); drm 505 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&t.engine->i915->drm.struct_mutex); drm 533 drivers/gpu/drm/i915/selftests/i915_request.c drm_dev_put(&i915->drm); drm 552 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 612 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 695 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 757 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 848 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 931 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 952 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 1061 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 1152 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 1171 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 1186 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 1194 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 1222 drivers/gpu/drm/i915/selftests/i915_request.c mutex_lock(&i915->drm.struct_mutex); drm 1225 drivers/gpu/drm/i915/selftests/i915_request.c mutex_unlock(&i915->drm.struct_mutex); drm 43 drivers/gpu/drm/i915/selftests/i915_selftest.c pr_info("%s: %s() - ok!\n", i915->drm.driver->name, __func__); drm 266 drivers/gpu/drm/i915/selftests/i915_selftest.c mutex_lock(&i915->drm.struct_mutex); drm 269 drivers/gpu/drm/i915/selftests/i915_selftest.c mutex_unlock(&i915->drm.struct_mutex); drm 287 drivers/gpu/drm/i915/selftests/i915_selftest.c mutex_lock(>->i915->drm.struct_mutex); drm 290 drivers/gpu/drm/i915/selftests/i915_selftest.c mutex_unlock(>->i915->drm.struct_mutex); drm 834 drivers/gpu/drm/i915/selftests/i915_vma.c mutex_lock(&i915->drm.struct_mutex); drm 837 drivers/gpu/drm/i915/selftests/i915_vma.c mutex_unlock(&i915->drm.struct_mutex); drm 844 drivers/gpu/drm/i915/selftests/i915_vma.c drm_dev_put(&i915->drm); drm 882 drivers/gpu/drm/i915/selftests/i915_vma.c mutex_lock(&i915->drm.struct_mutex); drm 979 drivers/gpu/drm/i915/selftests/i915_vma.c mutex_unlock(&i915->drm.struct_mutex); drm 22 drivers/gpu/drm/i915/selftests/igt_live_test.c lockdep_assert_held(&i915->drm.struct_mutex); drm 53 drivers/gpu/drm/i915/selftests/igt_live_test.c lockdep_assert_held(&i915->drm.struct_mutex); drm 40 drivers/gpu/drm/i915/selftests/mock_drm.c inode->i_rdev = i915->drm.primary->index; drm 44 drivers/gpu/drm/i915/selftests/mock_gem_device.c lockdep_assert_held(&i915->drm.struct_mutex); drm 58 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_lock(&i915->drm.struct_mutex); drm 60 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_unlock(&i915->drm.struct_mutex); drm 65 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_lock(&i915->drm.struct_mutex); drm 69 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_unlock(&i915->drm.struct_mutex); drm 76 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_lock(&i915->drm.struct_mutex); drm 78 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_unlock(&i915->drm.struct_mutex); drm 84 drivers/gpu/drm/i915/selftests/mock_gem_device.c drm_mode_config_cleanup(&i915->drm); drm 86 drivers/gpu/drm/i915/selftests/mock_gem_device.c drm_dev_fini(&i915->drm); drm 87 drivers/gpu/drm/i915/selftests/mock_gem_device.c put_device(&i915->drm.pdev->dev); drm 161 drivers/gpu/drm/i915/selftests/mock_gem_device.c err = drm_dev_init(&i915->drm, &mock_driver, &pdev->dev); drm 166 drivers/gpu/drm/i915/selftests/mock_gem_device.c i915->drm.pdev = pdev; drm 167 drivers/gpu/drm/i915/selftests/mock_gem_device.c i915->drm.dev_private = i915; drm 172 drivers/gpu/drm/i915/selftests/mock_gem_device.c drm_mode_config_init(&i915->drm); drm 199 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_lock(&i915->drm.struct_mutex); drm 217 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_unlock(&i915->drm.struct_mutex); drm 228 drivers/gpu/drm/i915/selftests/mock_gem_device.c mutex_unlock(&i915->drm.struct_mutex); drm 232 drivers/gpu/drm/i915/selftests/mock_gem_device.c drm_mode_config_cleanup(&i915->drm); drm 233 drivers/gpu/drm/i915/selftests/mock_gem_device.c drm_dev_fini(&i915->drm); drm 207 drivers/gpu/drm/imx/dw_hdmi-imx.c struct drm_device *drm = data; drm 224 drivers/gpu/drm/imx/dw_hdmi-imx.c encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); drm 239 drivers/gpu/drm/imx/dw_hdmi-imx.c drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, drm 126 drivers/gpu/drm/imx/imx-drm-core.c int imx_drm_encoder_parse_of(struct drm_device *drm, drm 129 drivers/gpu/drm/imx/imx-drm-core.c uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np); drm 199 drivers/gpu/drm/imx/imx-drm-core.c struct drm_device *drm; drm 202 drivers/gpu/drm/imx/imx-drm-core.c drm = drm_dev_alloc(&imx_drm_driver, dev); drm 203 drivers/gpu/drm/imx/imx-drm-core.c if (IS_ERR(drm)) drm 204 drivers/gpu/drm/imx/imx-drm-core.c return PTR_ERR(drm); drm 215 drivers/gpu/drm/imx/imx-drm-core.c drm->irq_enabled = true; drm 222 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.min_width = 1; drm 223 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.min_height = 1; drm 224 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.max_width = 4096; drm 225 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.max_height = 4096; drm 226 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.funcs = &imx_drm_mode_config_funcs; drm 227 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.helper_private = &imx_drm_mode_config_helpers; drm 228 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.allow_fb_modifiers = true; drm 229 drivers/gpu/drm/imx/imx-drm-core.c drm->mode_config.normalize_zpos = true; drm 231 drivers/gpu/drm/imx/imx-drm-core.c drm_mode_config_init(drm); drm 233 drivers/gpu/drm/imx/imx-drm-core.c ret = drm_vblank_init(drm, MAX_CRTC); drm 237 drivers/gpu/drm/imx/imx-drm-core.c dev_set_drvdata(dev, drm); drm 240 drivers/gpu/drm/imx/imx-drm-core.c ret = component_bind_all(dev, drm); drm 244 drivers/gpu/drm/imx/imx-drm-core.c drm_mode_config_reset(drm); drm 256 drivers/gpu/drm/imx/imx-drm-core.c drm_kms_helper_poll_init(drm); drm 258 drivers/gpu/drm/imx/imx-drm-core.c ret = drm_dev_register(drm, 0); drm 262 drivers/gpu/drm/imx/imx-drm-core.c drm_fbdev_generic_setup(drm, legacyfb_depth); drm 267 drivers/gpu/drm/imx/imx-drm-core.c drm_kms_helper_poll_fini(drm); drm 268 drivers/gpu/drm/imx/imx-drm-core.c component_unbind_all(drm->dev, drm); drm 270 drivers/gpu/drm/imx/imx-drm-core.c drm_mode_config_cleanup(drm); drm 271 drivers/gpu/drm/imx/imx-drm-core.c drm_dev_put(drm); drm 278 drivers/gpu/drm/imx/imx-drm-core.c struct drm_device *drm = dev_get_drvdata(dev); drm 280 drivers/gpu/drm/imx/imx-drm-core.c drm_dev_unregister(drm); drm 282 drivers/gpu/drm/imx/imx-drm-core.c drm_kms_helper_poll_fini(drm); drm 284 drivers/gpu/drm/imx/imx-drm-core.c drm_mode_config_cleanup(drm); drm 286 drivers/gpu/drm/imx/imx-drm-core.c component_unbind_all(drm->dev, drm); drm 289 drivers/gpu/drm/imx/imx-drm-core.c drm_dev_put(drm); drm 33 drivers/gpu/drm/imx/imx-drm.h void imx_drm_mode_config_init(struct drm_device *drm); drm 37 drivers/gpu/drm/imx/imx-drm.h int imx_drm_encoder_parse_of(struct drm_device *drm, drm 421 drivers/gpu/drm/imx/imx-ldb.c static int imx_ldb_register(struct drm_device *drm, drm 428 drivers/gpu/drm/imx/imx-ldb.c ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child); drm 443 drivers/gpu/drm/imx/imx-ldb.c drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs, drm 462 drivers/gpu/drm/imx/imx-ldb.c drm_connector_init_with_ddc(drm, &imx_ldb_ch->connector, drm 586 drivers/gpu/drm/imx/imx-ldb.c struct drm_device *drm = data; drm 699 drivers/gpu/drm/imx/imx-ldb.c ret = imx_ldb_register(drm, channel); drm 469 drivers/gpu/drm/imx/imx-tve.c static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) drm 477 drivers/gpu/drm/imx/imx-tve.c ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node); drm 482 drivers/gpu/drm/imx/imx-tve.c drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs, drm 487 drivers/gpu/drm/imx/imx-tve.c drm_connector_init_with_ddc(drm, &tve->connector, drm 539 drivers/gpu/drm/imx/imx-tve.c struct drm_device *drm = data; drm 658 drivers/gpu/drm/imx/imx-tve.c ret = imx_tve_register(drm, tve); drm 360 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_client_platformdata *pdata, struct drm_device *drm) drm 376 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0, drm 385 drivers/gpu/drm/imx/ipuv3-crtc.c drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL, drm 397 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1], drm 439 drivers/gpu/drm/imx/ipuv3-crtc.c struct drm_device *drm = data; drm 449 drivers/gpu/drm/imx/ipuv3-crtc.c ret = ipu_crtc_init(ipu_crtc, pdata, drm); drm 151 drivers/gpu/drm/imx/parallel-display.c static int imx_pd_register(struct drm_device *drm, drm 157 drivers/gpu/drm/imx/parallel-display.c ret = imx_drm_encoder_parse_of(drm, encoder, imxpd->dev->of_node); drm 169 drivers/gpu/drm/imx/parallel-display.c drm_encoder_init(drm, encoder, &imx_pd_encoder_funcs, drm 175 drivers/gpu/drm/imx/parallel-display.c drm_connector_init(drm, &imxpd->connector, drm 199 drivers/gpu/drm/imx/parallel-display.c struct drm_device *drm = data; drm 235 drivers/gpu/drm/imx/parallel-display.c ret = imx_pd_register(drm, imxpd); drm 158 drivers/gpu/drm/ingenic/ingenic-drm.c struct drm_device drm; drm 204 drivers/gpu/drm/ingenic/ingenic-drm.c static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) drm 206 drivers/gpu/drm/ingenic/ingenic-drm.c return container_of(drm, struct ingenic_drm, drm); drm 484 drivers/gpu/drm/ingenic/ingenic-drm.c static void ingenic_drm_release(struct drm_device *drm) drm 486 drivers/gpu/drm/ingenic/ingenic-drm.c struct ingenic_drm *priv = drm_device_get_priv(drm); drm 488 drivers/gpu/drm/ingenic/ingenic-drm.c drm_mode_config_cleanup(drm); drm 489 drivers/gpu/drm/ingenic/ingenic-drm.c drm_dev_fini(drm); drm 608 drivers/gpu/drm/ingenic/ingenic-drm.c struct drm_device *drm; drm 624 drivers/gpu/drm/ingenic/ingenic-drm.c drm = &priv->drm; drm 625 drivers/gpu/drm/ingenic/ingenic-drm.c drm->dev_private = priv; drm 629 drivers/gpu/drm/ingenic/ingenic-drm.c ret = devm_drm_dev_init(dev, drm, &ingenic_drm_driver_data); drm 635 drivers/gpu/drm/ingenic/ingenic-drm.c drm_mode_config_init(drm); drm 636 drivers/gpu/drm/ingenic/ingenic-drm.c drm->mode_config.min_width = 0; drm 637 drivers/gpu/drm/ingenic/ingenic-drm.c drm->mode_config.min_height = 0; drm 638 drivers/gpu/drm/ingenic/ingenic-drm.c drm->mode_config.max_width = 800; drm 639 drivers/gpu/drm/ingenic/ingenic-drm.c drm->mode_config.max_height = 600; drm 640 drivers/gpu/drm/ingenic/ingenic-drm.c drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; drm 701 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_universal_plane_init(drm, &priv->primary, drm 713 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->primary, drm 725 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_encoder_init(drm, &priv->encoder, &ingenic_drm_encoder_funcs, drm 738 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_irq_install(drm, irq); drm 744 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_vblank_init(drm, 1); drm 750 drivers/gpu/drm/ingenic/ingenic-drm.c drm_mode_config_reset(drm); drm 780 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_dev_register(drm, 0); drm 786 drivers/gpu/drm/ingenic/ingenic-drm.c ret = drm_fbdev_generic_setup(drm, 32); drm 808 drivers/gpu/drm/ingenic/ingenic-drm.c drm_dev_unregister(&priv->drm); drm 809 drivers/gpu/drm/ingenic/ingenic-drm.c drm_atomic_helper_shutdown(&priv->drm); drm 818 drivers/gpu/drm/mcde/mcde_display.c struct drm_device *drm = crtc->dev; drm 819 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; drm 833 drivers/gpu/drm/mcde/mcde_display.c dev_info(drm->dev, "enable MCDE, %d x %d format %s\n", drm 838 drivers/gpu/drm/mcde/mcde_display.c dev_err(drm->dev, "no DSI master attached!\n"); drm 842 drivers/gpu/drm/mcde/mcde_display.c dev_info(drm->dev, "output in %s mode, format %dbpp\n", drm 848 drivers/gpu/drm/mcde/mcde_display.c dev_info(drm->dev, "overlay CPP %d bytes, DSI CPP %d bytes\n", drm 872 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(drm->dev, "FIFO watermark after flooring: %d bytes\n", drm 874 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(drm->dev, "Packet divisor: %d bytes\n", pkt_div); drm 882 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(drm->dev, "DSI packet size: %d * %d bytes per line\n", drm 884 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(drm->dev, "Overlay frame size: %u bytes\n", drm 887 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(drm->dev, "Overlay line stride: %u bytes\n", drm 891 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(drm->dev, "Formatter frame size: %u bytes\n", formatter_frame); drm 941 drivers/gpu/drm/mcde/mcde_display.c dev_info(drm->dev, "MCDE display is enabled\n"); drm 947 drivers/gpu/drm/mcde/mcde_display.c struct drm_device *drm = crtc->dev; drm 948 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; drm 956 drivers/gpu/drm/mcde/mcde_display.c dev_info(drm->dev, "MCDE display is disabled\n"); drm 1010 drivers/gpu/drm/mcde/mcde_display.c struct drm_device *drm = crtc->dev; drm 1011 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; drm 1067 drivers/gpu/drm/mcde/mcde_display.c struct drm_device *drm = crtc->dev; drm 1068 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; drm 1086 drivers/gpu/drm/mcde/mcde_display.c struct drm_device *drm = crtc->dev; drm 1087 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; drm 1103 drivers/gpu/drm/mcde/mcde_display.c int mcde_display_init(struct drm_device *drm) drm 1105 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; drm 1132 drivers/gpu/drm/mcde/mcde_display.c ret = drm_simple_display_pipe_init(drm, &mcde->pipe, drm 13 drivers/gpu/drm/mcde/mcde_drm.h struct drm_device drm; drm 42 drivers/gpu/drm/mcde/mcde_drm.h int mcde_display_init(struct drm_device *drm); drm 162 drivers/gpu/drm/mcde/mcde_drv.c static int mcde_modeset_init(struct drm_device *drm) drm 165 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = drm->dev_private; drm 169 drivers/gpu/drm/mcde/mcde_drv.c dev_err(drm->dev, "no display output bridge yet\n"); drm 173 drivers/gpu/drm/mcde/mcde_drv.c mode_config = &drm->mode_config; drm 189 drivers/gpu/drm/mcde/mcde_drv.c ret = drm_vblank_init(drm, 1); drm 191 drivers/gpu/drm/mcde/mcde_drv.c dev_err(drm->dev, "failed to init vblank\n"); drm 196 drivers/gpu/drm/mcde/mcde_drv.c ret = mcde_display_init(drm); drm 198 drivers/gpu/drm/mcde/mcde_drv.c dev_err(drm->dev, "failed to init display\n"); drm 212 drivers/gpu/drm/mcde/mcde_drv.c dev_err(drm->dev, "failed to attach display output bridge\n"); drm 216 drivers/gpu/drm/mcde/mcde_drv.c drm_mode_config_reset(drm); drm 217 drivers/gpu/drm/mcde/mcde_drv.c drm_kms_helper_poll_init(drm); drm 218 drivers/gpu/drm/mcde/mcde_drv.c drm_fbdev_generic_setup(drm, 32); drm 223 drivers/gpu/drm/mcde/mcde_drv.c drm_mode_config_cleanup(drm); drm 227 drivers/gpu/drm/mcde/mcde_drv.c static void mcde_release(struct drm_device *drm) drm 229 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = drm->dev_private; drm 231 drivers/gpu/drm/mcde/mcde_drv.c drm_mode_config_cleanup(drm); drm 232 drivers/gpu/drm/mcde/mcde_drv.c drm_dev_fini(drm); drm 266 drivers/gpu/drm/mcde/mcde_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 269 drivers/gpu/drm/mcde/mcde_drv.c drm_mode_config_init(drm); drm 271 drivers/gpu/drm/mcde/mcde_drv.c ret = component_bind_all(drm->dev, drm); drm 277 drivers/gpu/drm/mcde/mcde_drv.c ret = mcde_modeset_init(drm); drm 281 drivers/gpu/drm/mcde/mcde_drv.c ret = drm_dev_register(drm, 0); drm 288 drivers/gpu/drm/mcde/mcde_drv.c component_unbind_all(drm->dev, drm); drm 294 drivers/gpu/drm/mcde/mcde_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 296 drivers/gpu/drm/mcde/mcde_drv.c drm_dev_unregister(drm); drm 297 drivers/gpu/drm/mcde/mcde_drv.c drm_atomic_helper_shutdown(drm); drm 298 drivers/gpu/drm/mcde/mcde_drv.c component_unbind_all(drm->dev, drm); drm 318 drivers/gpu/drm/mcde/mcde_drv.c struct drm_device *drm; drm 333 drivers/gpu/drm/mcde/mcde_drv.c ret = drm_dev_init(&mcde->drm, &mcde_drm_driver, dev); drm 338 drivers/gpu/drm/mcde/mcde_drv.c drm = &mcde->drm; drm 339 drivers/gpu/drm/mcde/mcde_drv.c drm->dev_private = mcde; drm 340 drivers/gpu/drm/mcde/mcde_drv.c platform_set_drvdata(pdev, drm); drm 346 drivers/gpu/drm/mcde/mcde_drv.c drm->dev_private = mcde; drm 510 drivers/gpu/drm/mcde/mcde_drv.c drm_dev_put(drm); drm 517 drivers/gpu/drm/mcde/mcde_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 518 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = drm->dev_private; drm 524 drivers/gpu/drm/mcde/mcde_drv.c drm_dev_put(drm); drm 847 drivers/gpu/drm/mcde/mcde_dsi.c struct drm_device *drm = bridge->dev; drm 853 drivers/gpu/drm/mcde/mcde_dsi.c if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { drm 858 drivers/gpu/drm/mcde/mcde_dsi.c ret = drm_connector_init(drm, &d->connector, drm 889 drivers/gpu/drm/mcde/mcde_dsi.c struct drm_device *drm = data; drm 890 drivers/gpu/drm/mcde/mcde_dsi.c struct mcde *mcde = drm->dev_private; drm 300 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_device *drm = mtk_crtc->base.dev; drm 322 drivers/gpu/drm/mediatek/mtk_drm_crtc.c pm_runtime_put(drm->dev); drm 497 drivers/gpu/drm/mediatek/mtk_drm_crtc.c static int mtk_drm_crtc_init(struct drm_device *drm, drm 512 drivers/gpu/drm/mediatek/mtk_drm_crtc.c ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, drm 318 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp) drm 320 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c struct mtk_drm_private *private = drm->dev_private; drm 329 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp) drm 331 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c struct mtk_drm_private *private = drm->dev_private; drm 166 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); drm 167 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); drm 49 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct drm_device *drm = private->drm; drm 51 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_wait_for_fences(drm, state, false); drm 67 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_commit_modeset_disables(drm, state); drm 68 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_commit_modeset_enables(drm, state); drm 69 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_commit_planes(drm, state, drm 72 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_wait_for_vblanks(drm, state); drm 74 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_cleanup_planes(drm, state); drm 86 drivers/gpu/drm/mediatek/mtk_drm_drv.c static int mtk_atomic_commit(struct drm_device *drm, drm 90 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct mtk_drm_private *private = drm->dev_private; drm 93 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = drm_atomic_helper_prepare_planes(drm, state); drm 103 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_cleanup_planes(drm, state); drm 206 drivers/gpu/drm/mediatek/mtk_drm_drv.c static int mtk_drm_kms_init(struct drm_device *drm) drm 208 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct mtk_drm_private *private = drm->dev_private; drm 219 drivers/gpu/drm/mediatek/mtk_drm_drv.c dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", drm 226 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_mode_config_init(drm); drm 228 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->mode_config.min_width = 64; drm 229 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->mode_config.min_height = 64; drm 236 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->mode_config.max_width = 4096; drm 237 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->mode_config.max_height = 4096; drm 238 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->mode_config.funcs = &mtk_drm_mode_config_funcs; drm 240 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = component_bind_all(drm->dev, drm); drm 249 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = mtk_drm_crtc_create(drm, private->data->main_path, drm 254 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = mtk_drm_crtc_create(drm, private->data->ext_path, drm 259 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = mtk_drm_crtc_create(drm, private->data->third_path, drm 270 drivers/gpu/drm/mediatek/mtk_drm_drv.c dev_err(drm->dev, "Need at least one OVL device\n"); drm 284 drivers/gpu/drm/mediatek/mtk_drm_drv.c devm_kzalloc(drm->dev, sizeof(*dma_dev->dma_parms), drm 303 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->irq_enabled = true; drm 304 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = drm_vblank_init(drm, MAX_CRTC); drm 308 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_kms_helper_poll_init(drm); drm 309 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_mode_config_reset(drm); drm 317 drivers/gpu/drm/mediatek/mtk_drm_drv.c component_unbind_all(drm->dev, drm); drm 319 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_mode_config_cleanup(drm); drm 324 drivers/gpu/drm/mediatek/mtk_drm_drv.c static void mtk_drm_kms_deinit(struct drm_device *drm) drm 326 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct mtk_drm_private *private = drm->dev_private; drm 328 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_kms_helper_poll_fini(drm); drm 329 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_atomic_helper_shutdown(drm); drm 334 drivers/gpu/drm/mediatek/mtk_drm_drv.c component_unbind_all(drm->dev, drm); drm 335 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_mode_config_cleanup(drm); drm 393 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct drm_device *drm; drm 396 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm = drm_dev_alloc(&mtk_drm_driver, dev); drm 397 drivers/gpu/drm/mediatek/mtk_drm_drv.c if (IS_ERR(drm)) drm 398 drivers/gpu/drm/mediatek/mtk_drm_drv.c return PTR_ERR(drm); drm 400 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm->dev_private = private; drm 401 drivers/gpu/drm/mediatek/mtk_drm_drv.c private->drm = drm; drm 403 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = mtk_drm_kms_init(drm); drm 407 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = drm_dev_register(drm, 0); drm 411 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = drm_fbdev_generic_setup(drm, 32); drm 418 drivers/gpu/drm/mediatek/mtk_drm_drv.c mtk_drm_kms_deinit(drm); drm 420 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_dev_put(drm); drm 428 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_dev_unregister(private->drm); drm 429 drivers/gpu/drm/mediatek/mtk_drm_drv.c mtk_drm_kms_deinit(private->drm); drm 430 drivers/gpu/drm/mediatek/mtk_drm_drv.c drm_dev_put(private->drm); drm 432 drivers/gpu/drm/mediatek/mtk_drm_drv.c private->drm = NULL; drm 620 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct drm_device *drm = private->drm; drm 623 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = drm_mode_config_helper_suspend(drm); drm 632 drivers/gpu/drm/mediatek/mtk_drm_drv.c struct drm_device *drm = private->drm; drm 635 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = drm_mode_config_helper_resume(drm); drm 35 drivers/gpu/drm/mediatek/mtk_drm_drv.h struct drm_device *drm; drm 773 drivers/gpu/drm/mediatek/mtk_dsi.c static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi) drm 777 drivers/gpu/drm/mediatek/mtk_dsi.c ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs, drm 804 drivers/gpu/drm/mediatek/mtk_dsi.c static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi) drm 808 drivers/gpu/drm/mediatek/mtk_dsi.c ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs, drm 831 drivers/gpu/drm/mediatek/mtk_dsi.c ret = mtk_dsi_create_connector(drm, dsi); drm 1042 drivers/gpu/drm/mediatek/mtk_dsi.c struct drm_device *drm = data; drm 1045 drivers/gpu/drm/mediatek/mtk_dsi.c ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp); drm 1058 drivers/gpu/drm/mediatek/mtk_dsi.c ret = mtk_dsi_create_conn_enc(drm, dsi); drm 1069 drivers/gpu/drm/mediatek/mtk_dsi.c mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); drm 1076 drivers/gpu/drm/mediatek/mtk_dsi.c struct drm_device *drm = data; drm 1081 drivers/gpu/drm/mediatek/mtk_dsi.c mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); drm 548 drivers/gpu/drm/meson/meson_crtc.c spin_lock_irqsave(&priv->drm->event_lock, flags); drm 554 drivers/gpu/drm/meson/meson_crtc.c spin_unlock_irqrestore(&priv->drm->event_lock, flags); drm 563 drivers/gpu/drm/meson/meson_crtc.c meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc), drm 570 drivers/gpu/drm/meson/meson_crtc.c ret = drm_crtc_init_with_planes(priv->drm, crtc, drm 574 drivers/gpu/drm/meson/meson_crtc.c dev_err(priv->drm->dev, "Failed to init CRTC\n"); drm 188 drivers/gpu/drm/meson/meson_drv.c struct drm_device *drm; drm 199 drivers/gpu/drm/meson/meson_drv.c drm = drm_dev_alloc(&meson_driver, dev); drm 200 drivers/gpu/drm/meson/meson_drv.c if (IS_ERR(drm)) drm 201 drivers/gpu/drm/meson/meson_drv.c return PTR_ERR(drm); drm 208 drivers/gpu/drm/meson/meson_drv.c drm->dev_private = priv; drm 209 drivers/gpu/drm/meson/meson_drv.c priv->drm = drm; drm 273 drivers/gpu/drm/meson/meson_drv.c ret = drm_vblank_init(drm, 1); drm 280 drivers/gpu/drm/meson/meson_drv.c drm_mode_config_init(drm); drm 281 drivers/gpu/drm/meson/meson_drv.c drm->mode_config.max_width = 3840; drm 282 drivers/gpu/drm/meson/meson_drv.c drm->mode_config.max_height = 2160; drm 283 drivers/gpu/drm/meson/meson_drv.c drm->mode_config.funcs = &meson_mode_config_funcs; drm 284 drivers/gpu/drm/meson/meson_drv.c drm->mode_config.helper_private = &meson_mode_config_helpers; drm 300 drivers/gpu/drm/meson/meson_drv.c ret = component_bind_all(drm->dev, drm); drm 302 drivers/gpu/drm/meson/meson_drv.c dev_err(drm->dev, "Couldn't bind all components\n"); drm 319 drivers/gpu/drm/meson/meson_drv.c ret = drm_irq_install(drm, priv->vsync_irq); drm 323 drivers/gpu/drm/meson/meson_drv.c drm_mode_config_reset(drm); drm 325 drivers/gpu/drm/meson/meson_drv.c drm_kms_helper_poll_init(drm); drm 329 drivers/gpu/drm/meson/meson_drv.c ret = drm_dev_register(drm, 0); drm 333 drivers/gpu/drm/meson/meson_drv.c drm_fbdev_generic_setup(drm, 32); drm 338 drivers/gpu/drm/meson/meson_drv.c drm_irq_uninstall(drm); drm 340 drivers/gpu/drm/meson/meson_drv.c drm_dev_put(drm); drm 353 drivers/gpu/drm/meson/meson_drv.c struct drm_device *drm = priv->drm; drm 362 drivers/gpu/drm/meson/meson_drv.c drm_dev_unregister(drm); drm 363 drivers/gpu/drm/meson/meson_drv.c drm_irq_uninstall(drm); drm 364 drivers/gpu/drm/meson/meson_drv.c drm_kms_helper_poll_fini(drm); drm 365 drivers/gpu/drm/meson/meson_drv.c drm_mode_config_cleanup(drm); drm 366 drivers/gpu/drm/meson/meson_drv.c drm_dev_put(drm); drm 40 drivers/gpu/drm/meson/meson_drv.h struct drm_device *drm; drm 811 drivers/gpu/drm/meson/meson_dw_hdmi.c struct drm_device *drm = data; drm 812 drivers/gpu/drm/meson/meson_dw_hdmi.c struct meson_drm *priv = drm->dev_private; drm 822 drivers/gpu/drm/meson/meson_dw_hdmi.c dev_info(drm->dev, "HDMI Output connector not available\n"); drm 917 drivers/gpu/drm/meson/meson_dw_hdmi.c ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs, drm 351 drivers/gpu/drm/meson/meson_overlay.c spin_lock_irqsave(&priv->drm->event_lock, flags); drm 500 drivers/gpu/drm/meson/meson_overlay.c spin_unlock_irqrestore(&priv->drm->event_lock, flags); drm 561 drivers/gpu/drm/meson/meson_overlay.c meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay), drm 569 drivers/gpu/drm/meson/meson_overlay.c drm_universal_plane_init(priv->drm, plane, 0xFF, drm 127 drivers/gpu/drm/meson/meson_plane.c spin_lock_irqsave(&priv->drm->event_lock, flags); drm 320 drivers/gpu/drm/meson/meson_plane.c spin_unlock_irqrestore(&priv->drm->event_lock, flags); drm 371 drivers/gpu/drm/meson/meson_plane.c meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), drm 379 drivers/gpu/drm/meson/meson_plane.c drm_universal_plane_init(priv->drm, plane, 0xFF, drm 243 drivers/gpu/drm/meson/meson_venc_cvbs.c struct drm_device *drm = priv->drm; drm 250 drivers/gpu/drm/meson/meson_venc_cvbs.c dev_info(drm->dev, "CVBS Output connector not available\n"); drm 268 drivers/gpu/drm/meson/meson_venc_cvbs.c ret = drm_connector_init(drm, connector, &meson_cvbs_connector_funcs, drm 281 drivers/gpu/drm/meson/meson_venc_cvbs.c ret = drm_encoder_init(drm, encoder, &meson_venc_cvbs_encoder_funcs, drm 324 drivers/gpu/drm/msm/adreno/a5xx_power.c struct drm_device *drm = gpu->dev; drm 358 drivers/gpu/drm/msm/adreno/a5xx_power.c ptr = msm_gem_kernel_new_locked(drm, bosize, drm 320 drivers/gpu/drm/msm/adreno/adreno_device.c struct drm_device *drm = dev_get_drvdata(master); drm 321 drivers/gpu/drm/msm/adreno/adreno_device.c struct msm_drm_private *priv = drm->dev_private; drm 330 drivers/gpu/drm/msm/adreno/adreno_device.c set_gpu_pdev(drm, to_platform_device(dev)); drm 335 drivers/gpu/drm/msm/adreno/adreno_device.c dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", drm 346 drivers/gpu/drm/msm/adreno/adreno_device.c gpu = info->init(drm); drm 348 drivers/gpu/drm/msm/adreno/adreno_device.c dev_warn(drm->dev, "failed to load adreno gpu\n"); drm 211 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct drm_device *drm = adreno_gpu->base.dev; drm 227 drivers/gpu/drm/msm/adreno/adreno_gpu.c ret = request_firmware_direct(&fw, newname, drm->dev); drm 229 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", drm 234 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", drm 247 drivers/gpu/drm/msm/adreno/adreno_gpu.c ret = request_firmware_direct(&fw, fwname, drm->dev); drm 249 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", drm 254 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", drm 268 drivers/gpu/drm/msm/adreno/adreno_gpu.c ret = request_firmware(&fw, newname, drm->dev); drm 270 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", drm 275 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", drm 282 drivers/gpu/drm/msm/adreno/adreno_gpu.c DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); drm 896 drivers/gpu/drm/msm/adreno/adreno_gpu.c int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, drm 927 drivers/gpu/drm/msm/adreno/adreno_gpu.c return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, drm 239 drivers/gpu/drm/msm/adreno/adreno_gpu.h int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, drm 106 drivers/gpu/drm/msm/dsi/dsi.c struct drm_device *drm = dev_get_drvdata(master); drm 107 drivers/gpu/drm/msm/dsi/dsi.c struct msm_drm_private *priv = drm->dev_private; drm 129 drivers/gpu/drm/msm/dsi/dsi.c struct drm_device *drm = dev_get_drvdata(master); drm 130 drivers/gpu/drm/msm/dsi/dsi.c struct msm_drm_private *priv = drm->dev_private; drm 69 drivers/gpu/drm/msm/edp/edp.c struct drm_device *drm = dev_get_drvdata(master); drm 70 drivers/gpu/drm/msm/edp/edp.c struct msm_drm_private *priv = drm->dev_private; drm 84 drivers/gpu/drm/msm/edp/edp.c struct drm_device *drm = dev_get_drvdata(master); drm 85 drivers/gpu/drm/msm/edp/edp.c struct msm_drm_private *priv = drm->dev_private; drm 535 drivers/gpu/drm/msm/hdmi/hdmi.c struct drm_device *drm = dev_get_drvdata(master); drm 536 drivers/gpu/drm/msm/hdmi/hdmi.c struct msm_drm_private *priv = drm->dev_private; drm 607 drivers/gpu/drm/msm/hdmi/hdmi.c struct drm_device *drm = dev_get_drvdata(master); drm 608 drivers/gpu/drm/msm/hdmi/hdmi.c struct msm_drm_private *priv = drm->dev_private; drm 109 drivers/gpu/drm/msm/msm_atomic_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/msm drm 414 drivers/gpu/drm/msm/msm_drv.h int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); drm 417 drivers/gpu/drm/msm/msm_drv.h int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, drm 419 drivers/gpu/drm/msm/msm_drv.h int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, drm 851 drivers/gpu/drm/msm/msm_gpu.c int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, drm 862 drivers/gpu/drm/msm/msm_gpu.c gpu->dev = drm; drm 887 drivers/gpu/drm/msm/msm_gpu.c DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret); drm 894 drivers/gpu/drm/msm/msm_gpu.c DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); drm 927 drivers/gpu/drm/msm/msm_gpu.c DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); drm 933 drivers/gpu/drm/msm/msm_gpu.c memptrs = msm_gem_kernel_new(drm, drm 940 drivers/gpu/drm/msm/msm_gpu.c DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); drm 947 drivers/gpu/drm/msm/msm_gpu.c DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", drm 958 drivers/gpu/drm/msm/msm_gpu.c DRM_DEV_ERROR(drm->dev, drm 278 drivers/gpu/drm/msm/msm_gpu.h int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, drm 89 drivers/gpu/drm/msm/msm_gpu_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/msm drm 56 drivers/gpu/drm/msm/msm_submitqueue.c int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, drm 59 drivers/gpu/drm/msm/msm_submitqueue.c struct msm_drm_private *priv = drm->dev_private; drm 94 drivers/gpu/drm/msm/msm_submitqueue.c int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx) drm 96 drivers/gpu/drm/msm/msm_submitqueue.c struct msm_drm_private *priv = drm->dev_private; drm 113 drivers/gpu/drm/msm/msm_submitqueue.c return msm_submitqueue_create(drm, ctx, default_prio, 0, NULL); drm 136 drivers/gpu/drm/msm/msm_submitqueue.c int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, drm 49 drivers/gpu/drm/mxsfb/mxsfb_crtc.c struct drm_device *drm = crtc->dev; drm 68 drivers/gpu/drm/mxsfb/mxsfb_crtc.c dev_dbg(drm->dev, "Setting up RGB565 mode\n"); drm 73 drivers/gpu/drm/mxsfb/mxsfb_crtc.c dev_dbg(drm->dev, "Setting up XRGB8888 mode\n"); drm 79 drivers/gpu/drm/mxsfb/mxsfb_crtc.c dev_err(drm->dev, "Unhandled pixel format %08x\n", format); drm 92 drivers/gpu/drm/mxsfb/mxsfb_crtc.c struct drm_device *drm = crtc->dev; drm 113 drivers/gpu/drm/mxsfb/mxsfb_crtc.c dev_err(drm->dev, "Unknown media bus format %d\n", bus_format); drm 105 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm = pipe->plane.dev; drm 107 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_get_sync(drm->dev); drm 116 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm = pipe->plane.dev; drm 123 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_put_sync(drm->dev); drm 125 drivers/gpu/drm/mxsfb/mxsfb_drv.c spin_lock_irq(&drm->event_lock); drm 131 drivers/gpu/drm/mxsfb/mxsfb_drv.c spin_unlock_irq(&drm->event_lock); drm 175 drivers/gpu/drm/mxsfb/mxsfb_drv.c static int mxsfb_load(struct drm_device *drm, unsigned long flags) drm 177 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct platform_device *pdev = to_platform_device(drm->dev); drm 186 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->dev_private = mxsfb; drm 190 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb->base = devm_ioremap_resource(drm->dev, res); drm 194 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb->clk = devm_clk_get(drm->dev, NULL); drm 198 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb->clk_axi = devm_clk_get(drm->dev, "axi"); drm 202 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb->clk_disp_axi = devm_clk_get(drm->dev, "disp_axi"); drm 206 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); drm 210 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_enable(drm->dev); drm 212 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 214 drivers/gpu/drm/mxsfb/mxsfb_drv.c dev_err(drm->dev, "Failed to initialise vblank\n"); drm 219 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_mode_config_init(drm); drm 221 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = mxsfb_create_output(drm); drm 223 drivers/gpu/drm/mxsfb/mxsfb_drv.c dev_err(drm->dev, "Failed to create outputs\n"); drm 227 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = drm_simple_display_pipe_init(drm, &mxsfb->pipe, &mxsfb_funcs, drm 231 drivers/gpu/drm/mxsfb/mxsfb_drv.c dev_err(drm->dev, "Cannot setup simple display pipe\n"); drm 237 drivers/gpu/drm/mxsfb/mxsfb_drv.c dev_err(drm->dev, "Cannot connect panel\n"); drm 241 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->mode_config.min_width = MXSFB_MIN_XRES; drm 242 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->mode_config.min_height = MXSFB_MIN_YRES; drm 243 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->mode_config.max_width = MXSFB_MAX_XRES; drm 244 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->mode_config.max_height = MXSFB_MAX_YRES; drm 245 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->mode_config.funcs = &mxsfb_mode_config_funcs; drm 246 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->mode_config.helper_private = &mxsfb_mode_config_helpers; drm 248 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_mode_config_reset(drm); drm 250 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_get_sync(drm->dev); drm 251 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); drm 252 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_put_sync(drm->dev); drm 255 drivers/gpu/drm/mxsfb/mxsfb_drv.c dev_err(drm->dev, "Failed to install IRQ handler\n"); drm 259 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_kms_helper_poll_init(drm); drm 261 drivers/gpu/drm/mxsfb/mxsfb_drv.c platform_set_drvdata(pdev, drm); drm 263 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_helper_hpd_irq_event(drm); drm 270 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_disable(drm->dev); drm 275 drivers/gpu/drm/mxsfb/mxsfb_drv.c static void mxsfb_unload(struct drm_device *drm) drm 277 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_kms_helper_poll_fini(drm); drm 278 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_mode_config_cleanup(drm); drm 280 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_get_sync(drm->dev); drm 281 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_irq_uninstall(drm); drm 282 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_put_sync(drm->dev); drm 284 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm->dev_private = NULL; drm 286 drivers/gpu/drm/mxsfb/mxsfb_drv.c pm_runtime_disable(drm->dev); drm 289 drivers/gpu/drm/mxsfb/mxsfb_drv.c static void mxsfb_irq_preinstall(struct drm_device *drm) drm 291 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct mxsfb_drm_private *mxsfb = drm->dev_private; drm 298 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm = data; drm 299 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct mxsfb_drm_private *mxsfb = drm->dev_private; drm 359 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm; drm 370 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm = drm_dev_alloc(&mxsfb_driver, &pdev->dev); drm 371 drivers/gpu/drm/mxsfb/mxsfb_drv.c if (IS_ERR(drm)) drm 372 drivers/gpu/drm/mxsfb/mxsfb_drv.c return PTR_ERR(drm); drm 374 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = mxsfb_load(drm, 0); drm 378 drivers/gpu/drm/mxsfb/mxsfb_drv.c ret = drm_dev_register(drm, 0); drm 382 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_fbdev_generic_setup(drm, 32); drm 387 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb_unload(drm); drm 389 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_dev_put(drm); drm 396 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 398 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_dev_unregister(drm); drm 399 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb_unload(drm); drm 400 drivers/gpu/drm/mxsfb/mxsfb_drv.c drm_dev_put(drm); drm 408 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 410 drivers/gpu/drm/mxsfb/mxsfb_drv.c return drm_mode_config_helper_suspend(drm); drm 415 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 417 drivers/gpu/drm/mxsfb/mxsfb_drv.c return drm_mode_config_helper_resume(drm); drm 76 drivers/gpu/drm/mxsfb/mxsfb_out.c int mxsfb_create_output(struct drm_device *drm) drm 78 drivers/gpu/drm/mxsfb/mxsfb_out.c struct mxsfb_drm_private *mxsfb = drm->dev_private; drm 82 drivers/gpu/drm/mxsfb/mxsfb_out.c ret = drm_of_find_panel_or_bridge(drm->dev->of_node, 0, 0, &panel, NULL); drm 90 drivers/gpu/drm/mxsfb/mxsfb_out.c ret = drm_connector_init(drm, &mxsfb->connector, drm 198 drivers/gpu/drm/nouveau/dispnv04/arb.c struct nouveau_drm *drm = nouveau_drm(dev); drm 230 drivers/gpu/drm/nouveau/dispnv04/arb.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) drm 255 drivers/gpu/drm/nouveau/dispnv04/arb.c struct nouveau_drm *drm = nouveau_drm(dev); drm 257 drivers/gpu/drm/nouveau/dispnv04/arb.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) drm 115 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 116 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nvkm_bios *bios = nvxx_bios(&drm->client.device); drm 117 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nvkm_clk *clk = nvxx_clk(&drm->client.device); drm 141 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) drm 151 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 154 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.chipset < 0x41) drm 160 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", drm 163 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", drm 174 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 178 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, drm 273 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) drm 459 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 508 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.chipset >= 0x11) drm 549 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) drm 555 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 559 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) drm 562 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) drm 568 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { drm 580 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) drm 589 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.chipset >= 0x11) drm 637 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 640 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); drm 652 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 699 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 713 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { drm 823 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 829 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "index %d\n", nv_crtc->index); drm 833 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "No FB bound\n"); drm 888 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { drm 911 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(crtc->dev); drm 912 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct drm_device *dev = drm->dev; drm 967 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 969 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.chipset == 0x11) { drm 986 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(crtc->dev); drm 987 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct drm_device *dev = drm->dev; drm 1010 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (drm->client.device.info.chipset >= 0x11) drm 1046 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = chan->drm; drm 1047 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct drm_device *dev = drm->dev; drm 1054 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_ERROR(drm, "unexpected pageflip\n"); drm 1080 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = cli->drm; drm 1081 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_channel *chan = drm->channel; drm 1085 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), drm 1102 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = chan->drm; drm 1103 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct drm_device *dev = drm->dev; drm 1145 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1156 drivers/gpu/drm/nouveau/dispnv04/crtc.c chan = drm->channel; drm 41 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct nouveau_drm *drm = nouveau_drm(dev); drm 58 drivers/gpu/drm/nouveau/dispnv04/cursor.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 67 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(dev); drm 68 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nvif_object *device = &drm->client.device.object; drm 82 drivers/gpu/drm/nouveau/dispnv04/dac.c if (nvif_msec(&drm->client.device, 10, drm 88 drivers/gpu/drm/nouveau/dispnv04/dac.c if (nvif_msec(&drm->client.device, 10, drm 94 drivers/gpu/drm/nouveau/dispnv04/dac.c if (nvif_msec(&drm->client.device, 10, drm 136 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(dev); drm 227 drivers/gpu/drm/nouveau/dispnv04/dac.c NV_DEBUG(drm, "Load detected on head A\n"); drm 237 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(dev); drm 239 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); drm 250 drivers/gpu/drm/nouveau/dispnv04/dac.c if (drm->vbios.tvdactestval) drm 251 drivers/gpu/drm/nouveau/dispnv04/dac.c testval = drm->vbios.tvdactestval; drm 255 drivers/gpu/drm/nouveau/dispnv04/dac.c if (drm->vbios.dactestval) drm 256 drivers/gpu/drm/nouveau/dispnv04/dac.c testval = drm->vbios.dactestval; drm 290 drivers/gpu/drm/nouveau/dispnv04/dac.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE) { drm 337 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(encoder->dev); drm 345 drivers/gpu/drm/nouveau/dispnv04/dac.c NV_DEBUG(drm, "Load detected on output %c\n", drm 379 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(dev); drm 405 drivers/gpu/drm/nouveau/dispnv04/dac.c if (drm->client.device.info.chipset < 0x44) drm 414 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(encoder->dev); drm 420 drivers/gpu/drm/nouveau/dispnv04/dac.c NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", drm 462 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_drm *drm = nouveau_drm(encoder->dev); drm 468 drivers/gpu/drm/nouveau/dispnv04/dac.c NV_DEBUG(drm, "Setting dpms mode %d on vga encoder (output %d)\n", drm 285 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 296 drivers/gpu/drm/nouveau/dispnv04/dfp.c NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index); drm 304 drivers/gpu/drm/nouveau/dispnv04/dfp.c drm->vbios.digital_min_front_porch) drm 307 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1; drm 420 drivers/gpu/drm/nouveau/dispnv04/dfp.c if (drm->client.device.info.chipset == 0x11) drm 431 drivers/gpu/drm/nouveau/dispnv04/dfp.c if (drm->client.device.info.chipset != 0x11) { drm 448 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 467 drivers/gpu/drm/nouveau/dispnv04/dfp.c if (drm->client.device.info.chipset < 0x44) drm 480 drivers/gpu/drm/nouveau/dispnv04/dfp.c NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", drm 516 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 524 drivers/gpu/drm/nouveau/dispnv04/dfp.c NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n", drm 562 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_drm *drm = nouveau_drm(encoder->dev); drm 569 drivers/gpu/drm/nouveau/dispnv04/dfp.c NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n", drm 626 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 627 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 78 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 115 drivers/gpu/drm/nouveau/dispnv04/disp.c NV_ERROR(drm, "Could not pin framebuffer\n"); drm 127 drivers/gpu/drm/nouveau/dispnv04/disp.c NV_ERROR(drm, "Could not pin/map cursor.\n"); drm 166 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 184 drivers/gpu/drm/nouveau/dispnv04/disp.c nvif_object_unmap(&drm->client.device.object); drm 190 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 191 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 192 drivers/gpu/drm/nouveau/dispnv04/disp.c struct dcb_table *dcb = &drm->vbios.dcb; drm 204 drivers/gpu/drm/nouveau/dispnv04/disp.c nvif_object_map(&drm->client.device.object, NULL, 0); drm 215 drivers/gpu/drm/nouveau/dispnv04/disp.c if (drm->nvsw.client) { drm 216 drivers/gpu/drm/nouveau/dispnv04/disp.c nvif_notify_init(&drm->nvsw, nv04_flip_complete, drm 249 drivers/gpu/drm/nouveau/dispnv04/disp.c NV_WARN(drm, "DCB type %d not known\n", dcbent->type); drm 260 drivers/gpu/drm/nouveau/dispnv04/disp.c NV_WARN(drm, "%s has no encoders, removing\n", drm 128 drivers/gpu/drm/nouveau/dispnv04/disp.h struct nouveau_drm *drm = nouveau_drm(dev); drm 131 drivers/gpu/drm/nouveau/dispnv04/disp.h if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 && drm 147 drivers/gpu/drm/nouveau/dispnv04/disp.h struct nouveau_drm *drm = nouveau_drm(dev); drm 150 drivers/gpu/drm/nouveau/dispnv04/disp.h if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE) drm 86 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 91 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset == 0x11) { drm 102 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset == 0x11) { /* set me harder */ drm 134 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 151 drivers/gpu/drm/nouveau/dispnv04/hw.c else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { drm 166 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 167 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nvif_object *device = &drm->client.device.object; drm 168 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nvkm_bios *bios = nvxx_bios(&drm->client.device); drm 186 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { drm 258 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 259 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nvif_device *device = &drm->client.device; drm 275 drivers/gpu/drm/nouveau/dispnv04/hw.c NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); drm 310 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 326 drivers/gpu/drm/nouveau/dispnv04/hw.c NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); drm 331 drivers/gpu/drm/nouveau/dispnv04/hw.c NV_ERROR(drm, "Failed to map VRAM, " drm 394 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 398 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) drm 405 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset == 0x11) drm 412 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset >= 0x30) drm 454 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { drm 469 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 470 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nvkm_clk *clk = nvxx_clk(&drm->client.device); drm 475 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) drm 482 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset == 0x11) drm 489 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset >= 0x30) drm 526 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { drm 591 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 607 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) drm 610 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) drm 619 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { drm 623 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) drm 626 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 638 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { drm 666 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 667 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nvif_object *device = &drm->client.device.object; drm 672 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { drm 684 drivers/gpu/drm/nouveau/dispnv04/hw.c nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); drm 685 drivers/gpu/drm/nouveau/dispnv04/hw.c nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); drm 686 drivers/gpu/drm/nouveau/dispnv04/hw.c nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); drm 687 drivers/gpu/drm/nouveau/dispnv04/hw.c nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); drm 694 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) drm 697 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { drm 720 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) drm 723 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) drm 730 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 736 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { drm 744 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { drm 747 drivers/gpu/drm/nouveau/dispnv04/hw.c nvif_msec(&drm->client.device, 650, drm 751 drivers/gpu/drm/nouveau/dispnv04/hw.c nvif_msec(&drm->client.device, 650, drm 814 drivers/gpu/drm/nouveau/dispnv04/hw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 816 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.chipset == 0x11) drm 168 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 173 drivers/gpu/drm/nouveau/dispnv04/hw.h if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 184 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 188 drivers/gpu/drm/nouveau/dispnv04/hw.h if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 262 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 264 drivers/gpu/drm/nouveau/dispnv04/hw.h if (drm->client.device.info.chipset == 0x11) drm 314 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 320 drivers/gpu/drm/nouveau/dispnv04/hw.h if (drm->client.device.info.chipset == 0x11 && !nv_heads_tied(dev)) drm 335 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 337 drivers/gpu/drm/nouveau/dispnv04/hw.h return drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE; drm 355 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 359 drivers/gpu/drm/nouveau/dispnv04/hw.h if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) { drm 374 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 384 drivers/gpu/drm/nouveau/dispnv04/hw.h if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 391 drivers/gpu/drm/nouveau/dispnv04/hw.h struct nouveau_drm *drm = nouveau_drm(dev); drm 400 drivers/gpu/drm/nouveau/dispnv04/hw.h if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) drm 119 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct nouveau_drm *drm = nouveau_drm(plane->dev); drm 120 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct nvif_object *dev = &drm->client.device.object; drm 129 drivers/gpu/drm/nouveau/dispnv04/overlay.c unsigned shift = drm->client.device.info.chipset >= 0x30 ? 1 : 3; drm 279 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct nouveau_drm *drm = nouveau_drm(device); drm 287 drivers/gpu/drm/nouveau/dispnv04/overlay.c switch (drm->client.device.info.chipset) { drm 357 drivers/gpu/drm/nouveau/dispnv04/overlay.c NV_ERROR(drm, "Failed to create plane\n"); drm 468 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct nouveau_drm *drm = nouveau_drm(device); drm 504 drivers/gpu/drm/nouveau/dispnv04/overlay.c NV_ERROR(drm, "Failed to create plane\n"); drm 55 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nouveau_drm *drm = nouveau_drm(dev); drm 56 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 77 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nouveau_drm *drm = nouveau_drm(dev); drm 82 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c NV_DEBUG(drm, "Setting dpms mode %d on TV encoder (output %d)\n", drm 168 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nouveau_drm *drm = nouveau_drm(dev); drm 174 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", drm 207 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nouveau_drm *drm = nouveau_drm(dev); drm 208 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 48 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 49 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); drm 58 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c if (drm->vbios.tvdactestval) drm 59 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c testval = drm->vbios.tvdactestval; drm 132 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 133 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nvkm_device *device = nvxx_device(&drm->client.device); drm 147 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 157 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c if (drm->client.device.info.chipset == 0x42 || drm 158 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm->client.device.info.chipset == 0x43) drm 192 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c NV_INFO(drm, "Load detected on output %c\n", drm 364 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 365 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); drm 373 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n", drm 399 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 426 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm->vbios.fp.dual_link); drm 438 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) drm 462 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 495 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) { drm 575 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 590 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c if (drm->client.device.info.chipset < 0x44) drm 601 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n", drm 638 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_drm *drm = nouveau_drm(dev); drm 655 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c NV_WARN(drm, "Invalid TV norm setting \"%s\"\n", drm 27 drivers/gpu/drm/nouveau/dispnv50/base.c nv50_base_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw) drm 43 drivers/gpu/drm/nouveau/dispnv50/base.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 48 drivers/gpu/drm/nouveau/dispnv50/base.c NV_ERROR(drm, "No supported base class\n"); drm 52 drivers/gpu/drm/nouveau/dispnv50/base.c return bases[cid].new(drm, head, bases[cid].oclass, pwndw); drm 259 drivers/gpu/drm/nouveau/dispnv50/base507c.c struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data, drm 265 drivers/gpu/drm/nouveau/dispnv50/base507c.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 269 drivers/gpu/drm/nouveau/dispnv50/base507c.c ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_PRIMARY, drm 275 drivers/gpu/drm/nouveau/dispnv50/base507c.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, drm 279 drivers/gpu/drm/nouveau/dispnv50/base507c.c NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret); drm 299 drivers/gpu/drm/nouveau/dispnv50/base507c.c base507c_new(struct nouveau_drm *drm, int head, s32 oclass, drm 302 drivers/gpu/drm/nouveau/dispnv50/base507c.c return base507c_new_(&base507c, base507c_format, drm, head, oclass, drm 75 drivers/gpu/drm/nouveau/dispnv50/base827c.c base827c_new(struct nouveau_drm *drm, int head, s32 oclass, drm 78 drivers/gpu/drm/nouveau/dispnv50/base827c.c return base507c_new_(&base827c, base507c_format, drm, head, oclass, drm 171 drivers/gpu/drm/nouveau/dispnv50/base907c.c base907c_new(struct nouveau_drm *drm, int head, s32 oclass, drm 174 drivers/gpu/drm/nouveau/dispnv50/base907c.c return base507c_new_(&base907c, base507c_format, drm, head, oclass, drm 45 drivers/gpu/drm/nouveau/dispnv50/base917c.c base917c_new(struct nouveau_drm *drm, int head, s32 oclass, drm 48 drivers/gpu/drm/nouveau/dispnv50/base917c.c return base507c_new_(&base907c, base917c_format, drm, head, oclass, drm 38 drivers/gpu/drm/nouveau/dispnv50/core.c nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore) drm 61 drivers/gpu/drm/nouveau/dispnv50/core.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 66 drivers/gpu/drm/nouveau/dispnv50/core.c NV_ERROR(drm, "No supported core channel class\n"); drm 70 drivers/gpu/drm/nouveau/dispnv50/core.c return cores[cid].new(drm, cores[cid].oclass, pcore); drm 88 drivers/gpu/drm/nouveau/dispnv50/core507d.c core507d_new_(const struct nv50_core_func *func, struct nouveau_drm *drm, drm 92 drivers/gpu/drm/nouveau/dispnv50/core507d.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 100 drivers/gpu/drm/nouveau/dispnv50/core507d.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, drm 104 drivers/gpu/drm/nouveau/dispnv50/core507d.c NV_ERROR(drm, "core%04x allocation failed: %d\n", oclass, ret); drm 112 drivers/gpu/drm/nouveau/dispnv50/core507d.c core507d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) drm 114 drivers/gpu/drm/nouveau/dispnv50/core507d.c return core507d_new_(&core507d, drm, oclass, pcore); drm 38 drivers/gpu/drm/nouveau/dispnv50/core827d.c core827d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) drm 40 drivers/gpu/drm/nouveau/dispnv50/core827d.c return core507d_new_(&core827d, drm, oclass, pcore); drm 37 drivers/gpu/drm/nouveau/dispnv50/core907d.c core907d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) drm 39 drivers/gpu/drm/nouveau/dispnv50/core907d.c return core507d_new_(&core907d, drm, oclass, pcore); drm 37 drivers/gpu/drm/nouveau/dispnv50/core917d.c core917d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) drm 39 drivers/gpu/drm/nouveau/dispnv50/core917d.c return core507d_new_(&core917d, drm, oclass, pcore); drm 107 drivers/gpu/drm/nouveau/dispnv50/corec37d.c corec37d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) drm 109 drivers/gpu/drm/nouveau/dispnv50/corec37d.c return core507d_new_(&corec37d, drm, oclass, pcore); drm 58 drivers/gpu/drm/nouveau/dispnv50/corec57d.c corec57d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) drm 60 drivers/gpu/drm/nouveau/dispnv50/corec57d.c return core507d_new_(&corec57d, drm, oclass, pcore); drm 27 drivers/gpu/drm/nouveau/dispnv50/curs.c nv50_curs_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw) drm 43 drivers/gpu/drm/nouveau/dispnv50/curs.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 48 drivers/gpu/drm/nouveau/dispnv50/curs.c NV_ERROR(drm, "No supported cursor immediate class\n"); drm 52 drivers/gpu/drm/nouveau/dispnv50/curs.c return curses[cid].new(drm, head, curses[cid].oclass, pwndw); drm 109 drivers/gpu/drm/nouveau/dispnv50/curs507a.c curs507a_new_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, drm 116 drivers/gpu/drm/nouveau/dispnv50/curs507a.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 120 drivers/gpu/drm/nouveau/dispnv50/curs507a.c ret = nv50_wndw_new_(&curs507a_wndw, drm->dev, DRM_PLANE_TYPE_CURSOR, drm 129 drivers/gpu/drm/nouveau/dispnv50/curs507a.c NV_ERROR(drm, "curs%04x allocation failed: %d\n", oclass, ret); drm 140 drivers/gpu/drm/nouveau/dispnv50/curs507a.c curs507a_new(struct nouveau_drm *drm, int head, s32 oclass, drm 143 drivers/gpu/drm/nouveau/dispnv50/curs507a.c return curs507a_new_(&curs507a, drm, head, oclass, drm 25 drivers/gpu/drm/nouveau/dispnv50/curs907a.c curs907a_new(struct nouveau_drm *drm, int head, s32 oclass, drm 28 drivers/gpu/drm/nouveau/dispnv50/curs907a.c return curs507a_new_(&curs507a, drm, head, oclass, drm 45 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c cursc37a_new(struct nouveau_drm *drm, int head, s32 oclass, drm 48 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c return curs507a_new_(&cursc37a, drm, head, oclass, drm 280 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 281 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 295 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ERROR(drm, "error acquiring output path: %d\n", ret); drm 314 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(encoder->dev); drm 316 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); drm 452 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 453 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 557 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(encoder->dev); drm 640 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); drm 648 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", drm 690 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); drm 697 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); drm 700 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", drm 717 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); drm 724 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); drm 736 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); drm 752 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); drm 763 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", drm 768 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); drm 1108 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); drm 1112 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); drm 1132 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); drm 1136 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); drm 1159 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 1164 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); drm 1172 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 1174 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); drm 1248 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); drm 1249 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvif_object *disp = &drm->display->disp.object; drm 1472 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1474 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvbios *bios = &drm->vbios; drm 1576 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 1577 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvkm_bios *bios = nvxx_bios(&drm->client.device); drm 1578 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 1728 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 1729 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); drm 1777 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(state->dev); drm 1778 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 1783 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); drm 1785 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_for_each_encoder(encoder, drm->dev) { drm 1797 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ERROR(drm, "core notifier timeout\n"); drm 1799 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_for_each_encoder(encoder, drm->dev) { drm 1832 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1839 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); drm 1852 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, drm 1871 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, drm 1887 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, drm 1918 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, drm 1935 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, drm 1958 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, drm 1989 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ERROR(drm, "%s: timeout\n", plane->name); drm 2320 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 2321 drivers/gpu/drm/nouveau/dispnv50/disp.c struct dcb_table *dcb = &drm->vbios.dcb; drm 2343 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, drm 2360 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_core_new(drm, &disp->core); drm 2406 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", drm 2418 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_WARN(drm, "%s has no encoders, removing\n", drm 296 drivers/gpu/drm/nouveau/dispnv50/head.c struct nouveau_drm *drm = nouveau_drm(crtc->dev); drm 305 drivers/gpu/drm/nouveau/dispnv50/head.c NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); drm 479 drivers/gpu/drm/nouveau/dispnv50/head.c struct nouveau_drm *drm = nouveau_drm(dev); drm 494 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_base_new(drm, head->base.index, &base); drm 495 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_ovly_new(drm, head->base.index, &ovly); drm 497 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY, drm 499 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, drm 503 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_curs_new(drm, head->base.index, &curs); drm 520 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); drm 27 drivers/gpu/drm/nouveau/dispnv50/oimm.c nv50_oimm_init(struct nouveau_drm *drm, struct nv50_wndw *wndw) drm 41 drivers/gpu/drm/nouveau/dispnv50/oimm.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 46 drivers/gpu/drm/nouveau/dispnv50/oimm.c NV_ERROR(drm, "No supported overlay immediate class\n"); drm 50 drivers/gpu/drm/nouveau/dispnv50/oimm.c return oimms[cid].init(drm, oimms[cid].oclass, wndw); drm 27 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c oimm507b_init_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, drm 33 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 39 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c NV_ERROR(drm, "oimm%04x allocation failed: %d\n", oclass, ret); drm 49 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c oimm507b_init(struct nouveau_drm *drm, s32 oclass, struct nv50_wndw *wndw) drm 51 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c return oimm507b_init_(&curs507a, drm, oclass, wndw); drm 28 drivers/gpu/drm/nouveau/dispnv50/ovly.c nv50_ovly_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw) drm 43 drivers/gpu/drm/nouveau/dispnv50/ovly.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 48 drivers/gpu/drm/nouveau/dispnv50/ovly.c NV_ERROR(drm, "No supported overlay class\n"); drm 52 drivers/gpu/drm/nouveau/dispnv50/ovly.c ret = ovlys[cid].new(drm, head, ovlys[cid].oclass, pwndw); drm 56 drivers/gpu/drm/nouveau/dispnv50/ovly.c return nv50_oimm_init(drm, *pwndw); drm 170 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data, drm 176 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 180 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_OVERLAY, drm 187 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, drm 191 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c NV_ERROR(drm, "ovly%04x allocation failed: %d\n", oclass, ret); drm 211 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ovly507e_new(struct nouveau_drm *drm, int head, s32 oclass, drm 214 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c return ovly507e_new_(&ovly507e, ovly507e_format, drm, head, oclass, drm 99 drivers/gpu/drm/nouveau/dispnv50/ovly827e.c ovly827e_new(struct nouveau_drm *drm, int head, s32 oclass, drm 102 drivers/gpu/drm/nouveau/dispnv50/ovly827e.c return ovly507e_new_(&ovly827e, ovly827e_format, drm, head, oclass, drm 76 drivers/gpu/drm/nouveau/dispnv50/ovly907e.c ovly907e_new(struct nouveau_drm *drm, int head, s32 oclass, drm 79 drivers/gpu/drm/nouveau/dispnv50/ovly907e.c return ovly507e_new_(&ovly907e, ovly907e_format, drm, head, oclass, drm 37 drivers/gpu/drm/nouveau/dispnv50/ovly917e.c ovly917e_new(struct nouveau_drm *drm, int head, s32 oclass, drm 40 drivers/gpu/drm/nouveau/dispnv50/ovly917e.c return ovly507e_new_(&ovly907e, ovly917e_format, drm, head, oclass, drm 27 drivers/gpu/drm/nouveau/dispnv50/wimm.c nv50_wimm_init(struct nouveau_drm *drm, struct nv50_wndw *wndw) drm 38 drivers/gpu/drm/nouveau/dispnv50/wimm.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 43 drivers/gpu/drm/nouveau/dispnv50/wimm.c NV_ERROR(drm, "No supported window immediate class\n"); drm 47 drivers/gpu/drm/nouveau/dispnv50/wimm.c return wimms[cid].init(drm, wimms[cid].oclass, wndw); drm 5 drivers/gpu/drm/nouveau/dispnv50/wimm.h int nv50_wimm_init(struct nouveau_drm *drm, struct nv50_wndw *); drm 60 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c wimmc37b_init_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, drm 67 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 70 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, drm 74 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c NV_ERROR(drm, "wimm%04x allocation failed: %d\n", oclass, ret); drm 84 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c wimmc37b_init(struct nouveau_drm *drm, s32 oclass, struct nv50_wndw *wndw) drm 86 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c return wimmc37b_init_(&wimmc37b, drm, oclass, wndw); drm 44 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(fb->base.dev); drm 71 drivers/gpu/drm/nouveau/dispnv50/wndw.c args.base.limit = drm->client.device.info.ram_user - 1; drm 73 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (drm->client.device.info.chipset < 0x80) { drm 77 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (drm->client.device.info.chipset < 0xc0) { drm 82 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (drm->client.device.info.chipset < 0xd0) { drm 185 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); drm 186 drivers/gpu/drm/nouveau/dispnv50/wndw.c NV_ATOMIC(drm, "%s release\n", wndw->plane.name); drm 238 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); drm 241 drivers/gpu/drm/nouveau/dispnv50/wndw.c NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); drm 257 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (drm->client.device.info.chipset >= 0xc0) drm 392 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(plane->dev); drm 400 drivers/gpu/drm/nouveau/dispnv50/wndw.c NV_ATOMIC(drm, "%s atomic_check\n", plane->name); drm 468 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(plane->dev); drm 470 drivers/gpu/drm/nouveau/dispnv50/wndw.c NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); drm 481 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(plane->dev); drm 488 drivers/gpu/drm/nouveau/dispnv50/wndw.c NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb); drm 634 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(dev); drm 635 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nvif_mmu *mmu = &drm->client.mmu; drm 699 drivers/gpu/drm/nouveau/dispnv50/wndw.c nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, drm 712 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 717 drivers/gpu/drm/nouveau/dispnv50/wndw.c NV_ERROR(drm, "No supported window class\n"); drm 721 drivers/gpu/drm/nouveau/dispnv50/wndw.c ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); drm 725 drivers/gpu/drm/nouveau/dispnv50/wndw.c return nv50_wimm_init(drm, *pwndw); drm 276 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c wndwc37e_new_(const struct nv50_wndw_func *func, struct nouveau_drm *drm, drm 284 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c struct nv50_disp *disp = nv50_disp(drm->dev); drm 288 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c ret = nv50_wndw_new_(func, drm->dev, type, "wndw", index, drm 294 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, drm 298 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c NV_ERROR(drm, "qndw%04x allocation failed: %d\n", oclass, ret); drm 309 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c wndwc37e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, drm 312 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c return wndwc37e_new_(&wndwc37e, drm, type, index, oclass, drm 198 drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c wndwc57e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, drm 201 drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c return wndwc37e_new_(&wndwc57e, drm, type, index, oclass, drm 90 drivers/gpu/drm/nouveau/nouveau_abi16.c nouveau_abi16_swclass(struct nouveau_drm *drm) drm 92 drivers/gpu/drm/nouveau/nouveau_abi16.c switch (drm->client.device.info.family) { drm 180 drivers/gpu/drm/nouveau/nouveau_abi16.c struct nouveau_drm *drm = nouveau_drm(dev); drm 181 drivers/gpu/drm/nouveau/nouveau_abi16.c struct nvif_device *device = &drm->client.device; drm 219 drivers/gpu/drm/nouveau/nouveau_abi16.c getparam->value = drm->gem.vram_available; drm 222 drivers/gpu/drm/nouveau/nouveau_abi16.c getparam->value = drm->gem.gart_available; drm 252 drivers/gpu/drm/nouveau/nouveau_abi16.c struct nouveau_drm *drm = nouveau_drm(dev); drm 262 drivers/gpu/drm/nouveau/nouveau_abi16.c if (!drm->channel) drm 303 drivers/gpu/drm/nouveau/nouveau_abi16.c ret = nouveau_channel_new(drm, device, init->fb_ctxdma_handle, drm 518 drivers/gpu/drm/nouveau/nouveau_abi16.c struct nouveau_drm *drm = nouveau_drm(dev); drm 558 drivers/gpu/drm/nouveau/nouveau_abi16.c if (drm->agp.bridge) { drm 561 drivers/gpu/drm/nouveau/nouveau_abi16.c args.start += drm->agp.base + chan->ntfy->bo.offset; drm 562 drivers/gpu/drm/nouveau/nouveau_abi16.c args.limit += drm->agp.base + chan->ntfy->bo.offset; drm 69 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 70 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 81 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 82 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 103 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(encoder->base.base.dev); drm 104 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 119 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 120 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 134 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 135 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 155 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 156 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 173 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 174 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 202 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); drm 203 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_object *device = &drm->client.device.object; drm 208 drivers/gpu/drm/nouveau/nouveau_backlight.c if (drm->client.device.info.chipset <= 0xa0 || drm 209 drivers/gpu/drm/nouveau/nouveau_backlight.c drm->client.device.info.chipset == 0xaa || drm 210 drivers/gpu/drm/nouveau/nouveau_backlight.c drm->client.device.info.chipset == 0xac) drm 224 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 227 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nvif_device *device = &drm->client.device; drm 234 drivers/gpu/drm/nouveau/nouveau_backlight.c NV_INFO_ONCE(drm, "Apple GMUX detected: not registering Nouveau backlight interface\n"); drm 275 drivers/gpu/drm/nouveau/nouveau_backlight.c NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n"); drm 96 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 98 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "0x%04X: Parsing digital output script table\n", drm 109 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 110 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 146 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 147 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 192 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Pixel clock comparison table not found\n"); drm 199 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "LVDS output init script not found\n"); drm 215 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 216 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvif_object *device = &drm->client.device.object; drm 217 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 236 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "Calling LVDS script %d:\n", script); drm 269 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 275 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Pointer to LVDS manufacturer table invalid\n"); drm 289 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "LVDS table header not understood\n"); drm 297 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "LVDS table header not understood\n"); drm 303 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, drm 319 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 320 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvif_object *device = &drm->client.device.object; drm 334 drivers/gpu/drm/nouveau/nouveau_bios.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_MAXWELL) drm 337 drivers/gpu/drm/nouveau/nouveau_bios.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) drm 345 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 353 drivers/gpu/drm/nouveau/nouveau_bios.c NV_DEBUG(drm, "Pointer to flat panel table invalid\n"); drm 391 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, drm 410 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Pointer to flat panel xlat table invalid\n"); drm 420 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Bad flat panel table index\n"); drm 439 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", drm 449 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 450 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 520 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 521 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 582 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "LVDS table revision not currently supported\n"); drm 635 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 636 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvif_object *device = &drm->client.device.object; drm 637 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 658 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Pixel clock comparison table not found\n"); drm 665 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "TMDS output init script not found\n"); drm 703 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 708 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Do not understand BIT A table\n"); drm 715 drivers/gpu/drm/nouveau/nouveau_bios.c NV_DEBUG(drm, "Pointer to BIT loadval table invalid\n"); drm 722 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "BIT loadval table version %d.%d not supported\n", drm 732 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Do not understand BIT loadval table\n"); drm 752 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 755 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Do not understand BIT display table\n"); drm 771 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 774 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Do not understand init table\n"); drm 795 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 800 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "BIT i table too short for needed information\n"); drm 812 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "BIT i table not long enough for DAC load " drm 833 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "DAC load detection comparison table version " drm 853 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 856 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Do not understand BIT LVDS table\n"); drm 926 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 930 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Do not understand BIT TMDS table\n"); drm 936 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "Pointer to TMDS table not found\n"); drm 940 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "TMDS table version %d.%d\n", drm 954 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "TMDS table script pointers not stubbed\n"); drm 972 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 973 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 1002 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1008 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "BIT table '%c' not found\n", table->id); drm 1084 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1098 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "BMP version %d.%d\n", drm 1114 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "You have an unsupported BMP version. " drm 1163 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Bad BMP checksum\n"); drm 1250 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1253 drivers/gpu/drm/nouveau/nouveau_bios.c if (drm->client.device.info.family > NV_DEVICE_INFO_V0_TNT) drm 1254 drivers/gpu/drm/nouveau/nouveau_bios.c dcb = ROMPTR(dev, drm->vbios.data[0x36]); drm 1256 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "No DCB data found in VBIOS\n"); drm 1261 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "DCB version 0x%02x unknown\n", dcb[0]); drm 1293 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "No useful DCB data in VBIOS\n"); drm 1297 drivers/gpu/drm/nouveau/nouveau_bios.c NV_WARN(drm, "DCB header validation failed\n"); drm 1398 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1455 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Unknown LVDS configuration bits, " drm 1545 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1565 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Unknown DCB type %d\n", conn & 0x0000000f); drm 1604 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1622 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "Merging DCB entries %d and %d\n", drm 1648 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1649 drivers/gpu/drm/nouveau/nouveau_bios.c struct dcb_table *dcb = &drm->vbios.dcb; drm 1786 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1787 drivers/gpu/drm/nouveau/nouveau_bios.c struct dcb_table *dcb = &drm->vbios.dcb; drm 1795 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "DCB outp %02d: %08x %08x\n", idx, conn, conf); drm 1865 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1881 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf); drm 1898 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "DCB conn %02d: %04x\n", drm 1901 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "DCB conn %02d: %08x\n", drm 1920 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1921 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvif_object *device = &drm->client.device.object; drm 1927 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Too few entries in HW sequencer table for " drm 1935 drivers/gpu/drm/nouveau/nouveau_bios.c NV_ERROR(drm, "Unknown HW sequencer entry size\n"); drm 1939 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "Loading NV17 power sequencing microcode\n"); drm 1983 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1984 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 2007 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "Found EDID in BIOS\n"); drm 2014 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 2015 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvkm_bios *bios = nvxx_bios(&drm->client.device); drm 2016 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *legacy = &drm->vbios; drm 2043 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 2044 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 2064 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 2067 drivers/gpu/drm/nouveau/nouveau_bios.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) drm 2081 drivers/gpu/drm/nouveau/nouveau_bios.c struct nouveau_drm *drm = nouveau_drm(dev); drm 2082 drivers/gpu/drm/nouveau/nouveau_bios.c struct nvbios *bios = &drm->vbios; drm 2104 drivers/gpu/drm/nouveau/nouveau_bios.c NV_INFO(drm, "Adaptor not initialised, " drm 37 drivers/gpu/drm/nouveau/nouveau_bios.h struct nouveau_drm *drm = nouveau_drm((d)); \ drm 38 drivers/gpu/drm/nouveau/nouveau_bios.h ROM16(x) ? &drm->vbios.data[ROM16(x)] : NULL; \ drm 55 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_drm(dev); drm 56 drivers/gpu/drm/nouveau/nouveau_bo.c int i = reg - drm->tile.reg; drm 57 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvkm_fb *fb = nvxx_fb(&drm->client.device); drm 74 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_drm(dev); drm 75 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm_tile *tile = &drm->tile.reg[i]; drm 77 drivers/gpu/drm/nouveau/nouveau_bo.c spin_lock(&drm->tile.lock); drm 85 drivers/gpu/drm/nouveau/nouveau_bo.c spin_unlock(&drm->tile.lock); drm 93 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_drm(dev); drm 96 drivers/gpu/drm/nouveau/nouveau_bo.c spin_lock(&drm->tile.lock); drm 99 drivers/gpu/drm/nouveau/nouveau_bo.c spin_unlock(&drm->tile.lock); drm 107 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_drm(dev); drm 108 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvkm_fb *fb = nvxx_fb(&drm->client.device); drm 135 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 136 drivers/gpu/drm/nouveau/nouveau_bo.c struct drm_device *dev = drm->dev; drm 164 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 165 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvif_device *device = &drm->client.device; drm 198 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = cli->drm; drm 205 drivers/gpu/drm/nouveau/nouveau_bo.c NV_WARN(drm, "skipped size %016llx\n", *size); drm 215 drivers/gpu/drm/nouveau/nouveau_bo.c nvbo->bo.bdev = &drm->ttm.bdev; drm 225 drivers/gpu/drm/nouveau/nouveau_bo.c if (!nouveau_drm_use_coherent_gpu_mapping(drm)) drm 357 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 358 drivers/gpu/drm/nouveau/nouveau_bo.c u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; drm 361 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && drm 410 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 419 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && drm 430 drivers/gpu/drm/nouveau/nouveau_bo.c NV_ERROR(drm, "bo %p pinned elsewhere: " drm 461 drivers/gpu/drm/nouveau/nouveau_bo.c drm->gem.vram_available -= bo->mem.size; drm 464 drivers/gpu/drm/nouveau/nouveau_bo.c drm->gem.gart_available -= bo->mem.size; drm 480 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 499 drivers/gpu/drm/nouveau/nouveau_bo.c drm->gem.vram_available += bo->mem.size; drm 502 drivers/gpu/drm/nouveau/nouveau_bo.c drm->gem.gart_available += bo->mem.size; drm 541 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 553 drivers/gpu/drm/nouveau/nouveau_bo.c dma_sync_single_for_device(drm->dev->dev, drm 561 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 573 drivers/gpu/drm/nouveau/nouveau_bo.c dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], drm 639 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 641 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->agp.bridge) { drm 642 drivers/gpu/drm/nouveau/nouveau_bo.c return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); drm 660 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bdev); drm 661 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvif_mmu *mmu = &drm->client.mmu; drm 676 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { drm 678 drivers/gpu/drm/nouveau/nouveau_bo.c const u8 type = mmu->type[drm->ttm.type_vram].type; drm 692 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) drm 695 drivers/gpu/drm/nouveau/nouveau_bo.c if (!drm->agp.bridge) drm 700 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->agp.bridge) { drm 941 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, chan->drm->ntfy.handle); drm 1030 drivers/gpu/drm/nouveau/nouveau_bo.c OUT_RING (chan, chan->drm->ntfy.handle); drm 1092 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, drm 1097 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvif_vmm *vmm = &drm->client.vmm.vmm; drm 1127 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 1128 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_channel *chan = drm->ttm.chan; drm 1137 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { drm 1138 drivers/gpu/drm/nouveau/nouveau_bo.c ret = nouveau_bo_move_prep(drm, bo, new_reg); drm 1146 drivers/gpu/drm/nouveau/nouveau_bo.c ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); drm 1163 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_bo_move_init(struct nouveau_drm *drm) drm 1203 drivers/gpu/drm/nouveau/nouveau_bo.c chan = drm->cechan; drm 1205 drivers/gpu/drm/nouveau/nouveau_bo.c chan = drm->channel; drm 1212 drivers/gpu/drm/nouveau/nouveau_bo.c &drm->ttm.copy); drm 1214 drivers/gpu/drm/nouveau/nouveau_bo.c ret = mthd->init(chan, drm->ttm.copy.handle); drm 1216 drivers/gpu/drm/nouveau/nouveau_bo.c nvif_object_fini(&drm->ttm.copy); drm 1220 drivers/gpu/drm/nouveau/nouveau_bo.c drm->ttm.move = mthd->exec; drm 1221 drivers/gpu/drm/nouveau/nouveau_bo.c drm->ttm.chan = chan; drm 1227 drivers/gpu/drm/nouveau/nouveau_bo.c NV_INFO(drm, "MM: using %s for buffer copies\n", name); drm 1332 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 1333 drivers/gpu/drm/nouveau/nouveau_bo.c struct drm_device *dev = drm->dev; drm 1341 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { drm 1354 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 1355 drivers/gpu/drm/nouveau/nouveau_bo.c struct drm_device *dev = drm->dev; drm 1367 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 1378 drivers/gpu/drm/nouveau/nouveau_bo.c NV_WARN(drm, "Moving pinned object %p!\n", nvbo); drm 1380 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { drm 1395 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->ttm.move) { drm 1418 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { drm 1441 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bdev); drm 1442 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvkm_device *device = nvxx_device(&drm->client.device); drm 1458 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->agp.bridge) { drm 1460 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = drm->agp.base; drm 1461 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.is_iomem = !drm->agp.cma; drm 1464 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) drm 1472 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { drm 1519 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bdev); drm 1522 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { drm 1540 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 1542 drivers/gpu/drm/nouveau/nouveau_bo.c struct nvkm_device *device = nvxx_device(&drm->client.device); drm 1550 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || drm 1565 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || drm 1587 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm; drm 1604 drivers/gpu/drm/nouveau/nouveau_bo.c drm = nouveau_bdev(ttm->bdev); drm 1605 drivers/gpu/drm/nouveau/nouveau_bo.c dev = drm->dev->dev; drm 1608 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->agp.bridge) { drm 1649 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm *drm; drm 1657 drivers/gpu/drm/nouveau/nouveau_bo.c drm = nouveau_bdev(ttm->bdev); drm 1658 drivers/gpu/drm/nouveau/nouveau_bo.c dev = drm->dev->dev; drm 1661 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->agp.bridge) { drm 98 drivers/gpu/drm/nouveau/nouveau_chan.c nouveau_fence(chan->drm)->context_del(chan); drm 123 drivers/gpu/drm/nouveau/nouveau_chan.c nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, drm 137 drivers/gpu/drm/nouveau/nouveau_chan.c chan->drm = drm; drm 201 drivers/gpu/drm/nouveau/nouveau_chan.c if (chan->drm->agp.bridge) { drm 204 drivers/gpu/drm/nouveau/nouveau_chan.c args.start = chan->drm->agp.base; drm 205 drivers/gpu/drm/nouveau/nouveau_chan.c args.limit = chan->drm->agp.base + drm 206 drivers/gpu/drm/nouveau/nouveau_chan.c chan->drm->agp.size - 1; drm 226 drivers/gpu/drm/nouveau/nouveau_chan.c nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, drm 251 drivers/gpu/drm/nouveau/nouveau_chan.c ret = nouveau_channel_prep(drm, device, 0x12000, &chan); drm 317 drivers/gpu/drm/nouveau/nouveau_chan.c nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, drm 331 drivers/gpu/drm/nouveau/nouveau_chan.c ret = nouveau_channel_prep(drm, device, 0x10000, &chan); drm 358 drivers/gpu/drm/nouveau/nouveau_chan.c struct nouveau_drm *drm = chan->drm; drm 371 drivers/gpu/drm/nouveau/nouveau_chan.c NV_ERROR(drm, "Failed to request channel kill " drm 402 drivers/gpu/drm/nouveau/nouveau_chan.c if (chan->drm->agp.bridge) { drm 405 drivers/gpu/drm/nouveau/nouveau_chan.c args.start = chan->drm->agp.base; drm 406 drivers/gpu/drm/nouveau/nouveau_chan.c args.limit = chan->drm->agp.base + drm 407 drivers/gpu/drm/nouveau/nouveau_chan.c chan->drm->agp.size - 1; drm 470 drivers/gpu/drm/nouveau/nouveau_chan.c return nouveau_fence(chan->drm)->context_new(chan); drm 474 drivers/gpu/drm/nouveau/nouveau_chan.c nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, drm 486 drivers/gpu/drm/nouveau/nouveau_chan.c ret = nouveau_channel_ind(drm, device, arg0, priv, pchan); drm 489 drivers/gpu/drm/nouveau/nouveau_chan.c ret = nouveau_channel_dma(drm, device, pchan); drm 512 drivers/gpu/drm/nouveau/nouveau_chan.c nouveau_channels_init(struct nouveau_drm *drm) drm 524 drivers/gpu/drm/nouveau/nouveau_chan.c struct nvif_object *device = &drm->client.device.object; drm 531 drivers/gpu/drm/nouveau/nouveau_chan.c drm->chan.nr = args.v.channels.data; drm 532 drivers/gpu/drm/nouveau/nouveau_chan.c drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr); drm 10 drivers/gpu/drm/nouveau/nouveau_chan.h struct nouveau_drm *drm; drm 56 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 69 drivers/gpu/drm/nouveau/nouveau_connector.c NV_DEBUG(drm, "native mode from preferred\n"); drm 92 drivers/gpu/drm/nouveau/nouveau_connector.c NV_DEBUG(drm, "native mode from largest: %dx%d@%d\n", drm 505 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 512 drivers/gpu/drm/nouveau/nouveau_connector.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { drm 522 drivers/gpu/drm/nouveau/nouveau_connector.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_KELVIN || drm 523 drivers/gpu/drm/nouveau/nouveau_connector.c (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && drm 545 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(dev); drm 588 drivers/gpu/drm/nouveau/nouveau_connector.c NV_ERROR(drm, "DDC responded, but no EDID for %s\n", drm 659 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(dev); drm 676 drivers/gpu/drm/nouveau/nouveau_connector.c if (!drm->vbios.fp_no_ddc) { drm 702 drivers/gpu/drm/nouveau/nouveau_connector.c if (nouveau_bios_fp_mode(dev, NULL) && (drm->vbios.fp_no_ddc || drm 711 drivers/gpu/drm/nouveau/nouveau_connector.c if (!drm->vbios.fp_no_ddc) { drm 738 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 753 drivers/gpu/drm/nouveau/nouveau_connector.c NV_ERROR(drm, "can't find encoder to force %s on!\n", drm 857 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 860 drivers/gpu/drm/nouveau/nouveau_connector.c struct nvbios *bios = &drm->vbios; drm 923 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(dev); drm 941 drivers/gpu/drm/nouveau/nouveau_connector.c drm->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) { drm 991 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 1008 drivers/gpu/drm/nouveau/nouveau_connector.c if (drm->client.device.info.chipset >= 0x120) { drm 1016 drivers/gpu/drm/nouveau/nouveau_connector.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KEPLER) drm 1018 drivers/gpu/drm/nouveau/nouveau_connector.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) drm 1023 drivers/gpu/drm/nouveau/nouveau_connector.c drm->client.device.info.chipset >= 0x46) drm 1025 drivers/gpu/drm/nouveau/nouveau_connector.c else if (drm->client.device.info.chipset >= 0x40) drm 1027 drivers/gpu/drm/nouveau/nouveau_connector.c else if (drm->client.device.info.chipset >= 0x18) drm 1143 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(connector->dev); drm 1151 drivers/gpu/drm/nouveau/nouveau_connector.c NV_DEBUG(drm, "service %s\n", name); drm 1159 drivers/gpu/drm/nouveau/nouveau_connector.c ret = pm_runtime_get(drm->dev->dev); drm 1166 drivers/gpu/drm/nouveau/nouveau_connector.c NV_DEBUG(drm, "Deferring HPD on %s until runtime resume\n", drm 1168 drivers/gpu/drm/nouveau/nouveau_connector.c schedule_work(&drm->hpd_work); drm 1170 drivers/gpu/drm/nouveau/nouveau_connector.c pm_runtime_put_noidle(drm->dev->dev); drm 1173 drivers/gpu/drm/nouveau/nouveau_connector.c NV_WARN(drm, "HPD on %s dropped due to RPM failure: %d\n", drm 1180 drivers/gpu/drm/nouveau/nouveau_connector.c NV_DEBUG(drm, "%splugged %s\n", plugged ? "" : "un", name); drm 1188 drivers/gpu/drm/nouveau/nouveau_connector.c pm_runtime_mark_last_busy(drm->dev->dev); drm 1189 drivers/gpu/drm/nouveau/nouveau_connector.c pm_runtime_put_autosuspend(drm->dev->dev); drm 1259 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1296 drivers/gpu/drm/nouveau/nouveau_connector.c NV_WARN(drm, "unknown connector type %02x\n", drm 1320 drivers/gpu/drm/nouveau/nouveau_connector.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1321 drivers/gpu/drm/nouveau/nouveau_connector.c struct dcb_table *dcbt = &drm->vbios.dcb; drm 1357 drivers/gpu/drm/nouveau/nouveau_connector.c NV_ERROR(drm, "Error parsing LVDS table, disabling\n"); drm 1373 drivers/gpu/drm/nouveau/nouveau_connector.c NV_ERROR(drm, "failed to register aux channel\n"); drm 41 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct nouveau_drm *drm = nouveau_drm(node->minor->dev); drm 44 drivers/gpu/drm/nouveau/nouveau_debugfs.c for (i = 0; i < drm->vbios.length; i++) drm 45 drivers/gpu/drm/nouveau/nouveau_debugfs.c seq_printf(m, "%c", drm->vbios.data[i]); drm 53 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct nouveau_drm *drm = nouveau_drm(node->minor->dev); drm 56 drivers/gpu/drm/nouveau/nouveau_debugfs.c ret = pm_runtime_get_sync(drm->dev->dev); drm 61 drivers/gpu/drm/nouveau/nouveau_debugfs.c nvif_rd32(&drm->client.device.object, 0x101000)); drm 63 drivers/gpu/drm/nouveau/nouveau_debugfs.c pm_runtime_mark_last_busy(drm->dev->dev); drm 64 drivers/gpu/drm/nouveau/nouveau_debugfs.c pm_runtime_put_autosuspend(drm->dev->dev); drm 72 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct drm_device *drm = m->private; drm 73 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct nouveau_debugfs *debugfs = nouveau_debugfs(drm); drm 143 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct drm_device *drm = m->private; drm 144 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct nouveau_debugfs *debugfs = nouveau_debugfs(drm); drm 183 drivers/gpu/drm/nouveau/nouveau_debugfs.c ret = pm_runtime_get_sync(drm->dev); drm 187 drivers/gpu/drm/nouveau/nouveau_debugfs.c pm_runtime_put_autosuspend(drm->dev); drm 223 drivers/gpu/drm/nouveau/nouveau_debugfs.c struct nouveau_drm *drm = nouveau_drm(minor->dev); drm 249 drivers/gpu/drm/nouveau/nouveau_debugfs.c d_inode(dentry)->i_size = drm->vbios.length; drm 256 drivers/gpu/drm/nouveau/nouveau_debugfs.c nouveau_debugfs_init(struct nouveau_drm *drm) drm 260 drivers/gpu/drm/nouveau/nouveau_debugfs.c drm->debugfs = kzalloc(sizeof(*drm->debugfs), GFP_KERNEL); drm 261 drivers/gpu/drm/nouveau/nouveau_debugfs.c if (!drm->debugfs) drm 264 drivers/gpu/drm/nouveau/nouveau_debugfs.c ret = nvif_object_init(&drm->client.device.object, 0, drm 266 drivers/gpu/drm/nouveau/nouveau_debugfs.c &drm->debugfs->ctrl); drm 274 drivers/gpu/drm/nouveau/nouveau_debugfs.c nouveau_debugfs_fini(struct nouveau_drm *drm) drm 276 drivers/gpu/drm/nouveau/nouveau_debugfs.c if (drm->debugfs && drm->debugfs->ctrl.priv) drm 277 drivers/gpu/drm/nouveau/nouveau_debugfs.c nvif_object_fini(&drm->debugfs->ctrl); drm 279 drivers/gpu/drm/nouveau/nouveau_debugfs.c kfree(drm->debugfs); drm 280 drivers/gpu/drm/nouveau/nouveau_debugfs.c drm->debugfs = NULL; drm 32 drivers/gpu/drm/nouveau/nouveau_debugfs.h nouveau_debugfs_init(struct nouveau_drm *drm) drm 38 drivers/gpu/drm/nouveau/nouveau_debugfs.h nouveau_debugfs_fini(struct nouveau_drm *drm) drm 233 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_drm *drm = nouveau_drm(dev); drm 238 drivers/gpu/drm/nouveau/nouveau_display.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA && drm 351 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_drm *drm = container_of(work, typeof(*drm), hpd_work); drm 353 drivers/gpu/drm/nouveau/nouveau_display.c pm_runtime_get_sync(drm->dev->dev); drm 355 drivers/gpu/drm/nouveau/nouveau_display.c drm_helper_hpd_irq_event(drm->dev); drm 357 drivers/gpu/drm/nouveau/nouveau_display.c pm_runtime_mark_last_busy(drm->dev->dev); drm 358 drivers/gpu/drm/nouveau/nouveau_display.c pm_runtime_put_sync(drm->dev->dev); drm 367 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_drm *drm = container_of(nb, typeof(*drm), acpi_nb); drm 373 drivers/gpu/drm/nouveau/nouveau_display.c ret = pm_runtime_get(drm->dev->dev); drm 379 drivers/gpu/drm/nouveau/nouveau_display.c pm_runtime_put_autosuspend(drm->dev->dev); drm 385 drivers/gpu/drm/nouveau/nouveau_display.c NV_DEBUG(drm, "ACPI requested connector reprobe\n"); drm 386 drivers/gpu/drm/nouveau/nouveau_display.c schedule_work(&drm->hpd_work); drm 387 drivers/gpu/drm/nouveau/nouveau_display.c pm_runtime_put_noidle(drm->dev->dev); drm 389 drivers/gpu/drm/nouveau/nouveau_display.c NV_WARN(drm, "Dropped ACPI reprobe event due to RPM error: %d\n", drm 434 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_drm *drm = nouveau_drm(dev); drm 454 drivers/gpu/drm/nouveau/nouveau_display.c cancel_work_sync(&drm->hpd_work); drm 499 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_drm *drm = nouveau_drm(dev); drm 500 drivers/gpu/drm/nouveau/nouveau_display.c struct nvkm_device *device = nvxx_device(&drm->client.device); drm 504 drivers/gpu/drm/nouveau/nouveau_display.c disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL); drm 517 drivers/gpu/drm/nouveau/nouveau_display.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_CELSIUS) { drm 521 drivers/gpu/drm/nouveau/nouveau_display.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { drm 525 drivers/gpu/drm/nouveau/nouveau_display.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_FERMI) { drm 536 drivers/gpu/drm/nouveau/nouveau_display.c if (drm->client.device.info.chipset < 0x11) drm 544 drivers/gpu/drm/nouveau/nouveau_display.c if (nouveau_modeset != 2 && drm->vbios.dcb.entries) { drm 545 drivers/gpu/drm/nouveau/nouveau_display.c ret = nvif_disp_ctor(&drm->client.device, 0, &disp->disp); drm 568 drivers/gpu/drm/nouveau/nouveau_display.c INIT_WORK(&drm->hpd_work, nouveau_display_hpd_work); drm 570 drivers/gpu/drm/nouveau/nouveau_display.c drm->acpi_nb.notifier_call = nouveau_display_acpi_ntfy; drm 571 drivers/gpu/drm/nouveau/nouveau_display.c register_acpi_notifier(&drm->acpi_nb); drm 87 drivers/gpu/drm/nouveau/nouveau_dma.c struct nvif_user *user = &chan->drm->client.device.user; drm 53 drivers/gpu/drm/nouveau/nouveau_dmem.c typedef int (*nouveau_migrate_copy_t)(struct nouveau_drm *drm, u64 npages, drm 60 drivers/gpu/drm/nouveau/nouveau_dmem.c struct nouveau_drm *drm; drm 73 drivers/gpu/drm/nouveau/nouveau_dmem.c struct nouveau_drm *drm; drm 131 drivers/gpu/drm/nouveau/nouveau_dmem.c static vm_fault_t nouveau_dmem_fault_copy_one(struct nouveau_drm *drm, drm 135 drivers/gpu/drm/nouveau/nouveau_dmem.c struct device *dev = drm->dev->dev; drm 151 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->dmem->migrate.copy_func(drm, 1, NOUVEAU_APER_HOST, *dma_addr, drm 168 drivers/gpu/drm/nouveau/nouveau_dmem.c struct nouveau_drm *drm = dmem->drm; drm 191 drivers/gpu/drm/nouveau/nouveau_dmem.c ret = nouveau_dmem_fault_copy_one(drm, vmf, &args, &dma_addr); drm 198 drivers/gpu/drm/nouveau/nouveau_dmem.c dma_unmap_page(drm->dev->dev, dma_addr, PAGE_SIZE, DMA_BIDIRECTIONAL); drm 210 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_chunk_alloc(struct nouveau_drm *drm) drm 215 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->dmem == NULL) drm 218 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 219 drivers/gpu/drm/nouveau/nouveau_dmem.c chunk = list_first_entry_or_null(&drm->dmem->chunk_empty, drm 223 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 228 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 230 drivers/gpu/drm/nouveau/nouveau_dmem.c ret = nouveau_bo_new(&drm->client, DMEM_CHUNK_SIZE, 0, drm 246 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 248 drivers/gpu/drm/nouveau/nouveau_dmem.c list_add(&chunk->list, &drm->dmem->chunk_empty); drm 250 drivers/gpu/drm/nouveau/nouveau_dmem.c list_add_tail(&chunk->list, &drm->dmem->chunk_empty); drm 251 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 257 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_chunk_first_free_locked(struct nouveau_drm *drm) drm 261 drivers/gpu/drm/nouveau/nouveau_dmem.c chunk = list_first_entry_or_null(&drm->dmem->chunk_free, drm 267 drivers/gpu/drm/nouveau/nouveau_dmem.c chunk = list_first_entry_or_null(&drm->dmem->chunk_empty, drm 277 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_pages_alloc(struct nouveau_drm *drm, drm 287 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 291 drivers/gpu/drm/nouveau/nouveau_dmem.c chunk = nouveau_dmem_chunk_first_free_locked(drm); drm 293 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 294 drivers/gpu/drm/nouveau/nouveau_dmem.c ret = nouveau_dmem_chunk_alloc(drm); drm 300 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 317 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 323 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_page_alloc_locked(struct nouveau_drm *drm) drm 330 drivers/gpu/drm/nouveau/nouveau_dmem.c ret = nouveau_dmem_pages_alloc(drm, 1, pfns); drm 341 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_page_free_locked(struct nouveau_drm *drm, struct page *page) drm 348 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_resume(struct nouveau_drm *drm) drm 353 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->dmem == NULL) drm 356 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 357 drivers/gpu/drm/nouveau/nouveau_dmem.c list_for_each_entry (chunk, &drm->dmem->chunk_free, list) { drm 362 drivers/gpu/drm/nouveau/nouveau_dmem.c list_for_each_entry (chunk, &drm->dmem->chunk_full, list) { drm 367 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 371 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_suspend(struct nouveau_drm *drm) drm 375 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->dmem == NULL) drm 378 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 379 drivers/gpu/drm/nouveau/nouveau_dmem.c list_for_each_entry (chunk, &drm->dmem->chunk_free, list) { drm 382 drivers/gpu/drm/nouveau/nouveau_dmem.c list_for_each_entry (chunk, &drm->dmem->chunk_full, list) { drm 385 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 389 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_fini(struct nouveau_drm *drm) drm 393 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->dmem == NULL) drm 396 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_lock(&drm->dmem->mutex); drm 398 drivers/gpu/drm/nouveau/nouveau_dmem.c WARN_ON(!list_empty(&drm->dmem->chunk_free)); drm 399 drivers/gpu/drm/nouveau/nouveau_dmem.c WARN_ON(!list_empty(&drm->dmem->chunk_full)); drm 401 drivers/gpu/drm/nouveau/nouveau_dmem.c list_for_each_entry_safe (chunk, tmp, &drm->dmem->chunk_empty, list) { drm 410 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_unlock(&drm->dmem->mutex); drm 414 drivers/gpu/drm/nouveau/nouveau_dmem.c nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, drm 418 drivers/gpu/drm/nouveau/nouveau_dmem.c struct nouveau_channel *chan = drm->dmem->migrate.chan; drm 473 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_migrate_init(struct nouveau_drm *drm) drm 475 drivers/gpu/drm/nouveau/nouveau_dmem.c switch (drm->ttm.copy.oclass) { drm 480 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem->migrate.copy_func = nvc0b5_migrate_copy; drm 481 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem->migrate.chan = drm->ttm.chan; drm 490 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_init(struct nouveau_drm *drm) drm 492 drivers/gpu/drm/nouveau/nouveau_dmem.c struct device *device = drm->dev->dev; drm 498 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_PASCAL) drm 501 drivers/gpu/drm/nouveau/nouveau_dmem.c if (!(drm->dmem = kzalloc(sizeof(*drm->dmem), GFP_KERNEL))) drm 504 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem->drm = drm; drm 505 drivers/gpu/drm/nouveau/nouveau_dmem.c mutex_init(&drm->dmem->mutex); drm 506 drivers/gpu/drm/nouveau/nouveau_dmem.c INIT_LIST_HEAD(&drm->dmem->chunk_free); drm 507 drivers/gpu/drm/nouveau/nouveau_dmem.c INIT_LIST_HEAD(&drm->dmem->chunk_full); drm 508 drivers/gpu/drm/nouveau/nouveau_dmem.c INIT_LIST_HEAD(&drm->dmem->chunk_empty); drm 510 drivers/gpu/drm/nouveau/nouveau_dmem.c size = ALIGN(drm->client.device.info.ram_user, DMEM_CHUNK_SIZE); drm 513 drivers/gpu/drm/nouveau/nouveau_dmem.c ret = nouveau_dmem_migrate_init(drm); drm 526 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem->pagemap.type = MEMORY_DEVICE_PRIVATE; drm 527 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem->pagemap.res = *res; drm 528 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem->pagemap.ops = &nouveau_dmem_pagemap_ops; drm 529 drivers/gpu/drm/nouveau/nouveau_dmem.c if (IS_ERR(devm_memremap_pages(device, &drm->dmem->pagemap))) drm 540 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_fini(drm); drm 544 drivers/gpu/drm/nouveau/nouveau_dmem.c chunk->drm = drm; drm 546 drivers/gpu/drm/nouveau/nouveau_dmem.c list_add_tail(&chunk->list, &drm->dmem->chunk_empty); drm 553 drivers/gpu/drm/nouveau/nouveau_dmem.c NV_INFO(drm, "DMEM: registered %ldMB of device memory\n", size >> 20); drm 556 drivers/gpu/drm/nouveau/nouveau_dmem.c kfree(drm->dmem); drm 557 drivers/gpu/drm/nouveau/nouveau_dmem.c drm->dmem = NULL; drm 560 drivers/gpu/drm/nouveau/nouveau_dmem.c static unsigned long nouveau_dmem_migrate_copy_one(struct nouveau_drm *drm, drm 563 drivers/gpu/drm/nouveau/nouveau_dmem.c struct device *dev = drm->dev->dev; drm 570 drivers/gpu/drm/nouveau/nouveau_dmem.c dpage = nouveau_dmem_page_alloc_locked(drm); drm 578 drivers/gpu/drm/nouveau/nouveau_dmem.c if (drm->dmem->migrate.copy_func(drm, 1, NOUVEAU_APER_VRAM, drm 588 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_page_free_locked(drm, dpage); drm 593 drivers/gpu/drm/nouveau/nouveau_dmem.c static void nouveau_dmem_migrate_chunk(struct nouveau_drm *drm, drm 600 drivers/gpu/drm/nouveau/nouveau_dmem.c args->dst[i] = nouveau_dmem_migrate_copy_one(drm, args->src[i], drm 607 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_fence_new(drm->dmem->migrate.chan, false, &fence); drm 612 drivers/gpu/drm/nouveau/nouveau_dmem.c dma_unmap_page(drm->dev->dev, dma_addrs[nr_dma], PAGE_SIZE, drm 623 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_migrate_vma(struct nouveau_drm *drm, drm 657 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_migrate_chunk(drm, &args, dma_addrs); drm 673 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_page(struct nouveau_drm *drm, struct page *page) drm 675 drivers/gpu/drm/nouveau/nouveau_dmem.c return is_device_private_page(page) && drm->dmem == page_to_dmem(page); drm 679 drivers/gpu/drm/nouveau/nouveau_dmem.c nouveau_dmem_convert_pfn(struct nouveau_drm *drm, drm 697 drivers/gpu/drm/nouveau/nouveau_dmem.c if (!nouveau_dmem_page(drm, page)) { drm 36 drivers/gpu/drm/nouveau/nouveau_dmem.h int nouveau_dmem_migrate_vma(struct nouveau_drm *drm, drm 41 drivers/gpu/drm/nouveau/nouveau_dmem.h void nouveau_dmem_convert_pfn(struct nouveau_drm *drm, drm 44 drivers/gpu/drm/nouveau/nouveau_dmem.h static inline void nouveau_dmem_init(struct nouveau_drm *drm) {} drm 45 drivers/gpu/drm/nouveau/nouveau_dmem.h static inline void nouveau_dmem_fini(struct nouveau_drm *drm) {} drm 46 drivers/gpu/drm/nouveau/nouveau_dmem.h static inline void nouveau_dmem_suspend(struct nouveau_drm *drm) {} drm 47 drivers/gpu/drm/nouveau/nouveau_dmem.h static inline void nouveau_dmem_resume(struct nouveau_drm *drm) {} drm 42 drivers/gpu/drm/nouveau/nouveau_dp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 49 drivers/gpu/drm/nouveau/nouveau_dp.c NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n", drm 53 drivers/gpu/drm/nouveau/nouveau_dp.c NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n", drm 62 drivers/gpu/drm/nouveau/nouveau_dp.c struct nouveau_drm *drm = nouveau_drm(dev); drm 78 drivers/gpu/drm/nouveau/nouveau_dp.c NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n", drm 80 drivers/gpu/drm/nouveau/nouveau_dp.c NV_DEBUG(drm, "encoder: %dx%d\n", drm 89 drivers/gpu/drm/nouveau/nouveau_dp.c NV_DEBUG(drm, "maximum: %dx%d\n", drm 183 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_lock(&cli->drm->master.lock); drm 185 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_unlock(&cli->drm->master.lock); drm 189 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_cli_init(struct nouveau_drm *drm, const char *sname, drm 215 drivers/gpu/drm/nouveau/nouveau_drm.c u64 device = nouveau_name(drm->dev); drm 219 drivers/gpu/drm/nouveau/nouveau_drm.c cli->drm = drm; drm 227 drivers/gpu/drm/nouveau/nouveau_drm.c if (cli == &drm->master) { drm 231 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_lock(&drm->master.lock); drm 232 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_client_init(&drm->master.base, cli->name, device, drm 234 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_unlock(&drm->master.lock); drm 290 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_ce_fini(struct nouveau_drm *drm) drm 292 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_channel_idle(drm->cechan); drm 293 drivers/gpu/drm/nouveau/nouveau_drm.c nvif_object_fini(&drm->ttm.copy); drm 294 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_channel_del(&drm->cechan); drm 298 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_ce_init(struct nouveau_drm *drm) drm 300 drivers/gpu/drm/nouveau/nouveau_drm.c struct nvif_device *device = &drm->client.device; drm 307 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_channel_new(drm, device, drm 309 drivers/gpu/drm/nouveau/nouveau_drm.c true, &drm->cechan); drm 319 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false, drm 320 drivers/gpu/drm/nouveau/nouveau_drm.c &drm->cechan); drm 324 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "failed to create ce channel, %d\n", ret); drm 328 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_fini(struct nouveau_drm *drm) drm 330 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_channel_idle(drm->channel); drm 331 drivers/gpu/drm/nouveau/nouveau_drm.c nvif_object_fini(&drm->ntfy); drm 332 drivers/gpu/drm/nouveau/nouveau_drm.c nvkm_gpuobj_del(&drm->notify); drm 333 drivers/gpu/drm/nouveau/nouveau_drm.c nvif_object_fini(&drm->nvsw); drm 334 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_channel_del(&drm->channel); drm 338 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_init(struct nouveau_drm *drm) drm 340 drivers/gpu/drm/nouveau/nouveau_drm.c struct nvif_device *device = &drm->client.device; drm 353 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_channel_new(drm, device, arg0, arg1, false, drm 354 drivers/gpu/drm/nouveau/nouveau_drm.c &drm->channel); drm 356 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); drm 357 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_fini(drm); drm 366 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW, drm 367 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_abi16_swclass(drm), NULL, 0, drm 368 drivers/gpu/drm/nouveau/nouveau_drm.c &drm->nvsw); drm 370 drivers/gpu/drm/nouveau/nouveau_drm.c ret = RING_SPACE(drm->channel, 2); drm 372 drivers/gpu/drm/nouveau/nouveau_drm.c BEGIN_NV04(drm->channel, NvSubSw, 0, 1); drm 373 drivers/gpu/drm/nouveau/nouveau_drm.c OUT_RING (drm->channel, drm->nvsw.handle); drm 378 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "failed to allocate sw class, %d\n", ret); drm 379 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_fini(drm); drm 390 drivers/gpu/drm/nouveau/nouveau_drm.c &drm->notify); drm 392 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); drm 393 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_fini(drm); drm 397 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_object_init(&drm->channel->user, NvNotify0, drm 402 drivers/gpu/drm/nouveau/nouveau_drm.c .start = drm->notify->addr, drm 403 drivers/gpu/drm/nouveau/nouveau_drm.c .limit = drm->notify->addr + 31 drm 405 drivers/gpu/drm/nouveau/nouveau_drm.c &drm->ntfy); drm 407 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_fini(drm); drm 414 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_fini(struct nouveau_drm *drm) drm 416 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_ce_fini(drm); drm 417 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_fini(drm); drm 418 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->fence) drm 419 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_fence(drm)->dtor(drm); drm 423 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_init(struct nouveau_drm *drm) drm 425 drivers/gpu/drm/nouveau/nouveau_drm.c struct nvif_device *device = &drm->client.device; drm 433 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_channels_init(drm); drm 447 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nv04_fence_create(drm); drm 450 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nv10_fence_create(drm); drm 454 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nv17_fence_create(drm); drm 457 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nv50_fence_create(drm); drm 460 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nv84_fence_create(drm); drm 469 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvc0_fence_create(drm); drm 478 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); drm 479 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_fini(drm); drm 484 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { drm 491 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_gr_init(drm); drm 492 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_ce_init(drm); drm 495 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_bo_move_init(drm); drm 501 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm; drm 504 drivers/gpu/drm/nouveau/nouveau_drm.c if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) drm 506 drivers/gpu/drm/nouveau/nouveau_drm.c dev->dev_private = drm; drm 507 drivers/gpu/drm/nouveau/nouveau_drm.c drm->dev = dev; drm 509 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_cli_init(drm, "DRM-master", &drm->master); drm 513 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_cli_init(drm, "DRM", &drm->client); drm 519 drivers/gpu/drm/nouveau/nouveau_drm.c nvxx_client(&drm->client.base)->debug = drm 522 drivers/gpu/drm/nouveau/nouveau_drm.c INIT_LIST_HEAD(&drm->clients); drm 523 drivers/gpu/drm/nouveau/nouveau_drm.c spin_lock_init(&drm->tile.lock); drm 529 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->client.device.info.chipset == 0xc1) drm 530 drivers/gpu/drm/nouveau/nouveau_drm.c nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); drm 532 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_vga_init(drm); drm 534 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_ttm_init(drm); drm 542 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_init(drm); drm 554 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_debugfs_init(drm); drm 556 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_svm_init(drm); drm 557 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_dmem_init(drm); drm 575 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_fini(drm); drm 578 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_ttm_fini(drm); drm 580 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_vga_fini(drm); drm 581 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_cli_fini(&drm->client); drm 583 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_cli_fini(&drm->master); drm 585 drivers/gpu/drm/nouveau/nouveau_drm.c kfree(drm); drm 592 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 601 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_dmem_fini(drm); drm 602 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_svm_fini(drm); drm 604 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_debugfs_fini(drm); drm 610 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_accel_fini(drm); drm 613 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_ttm_fini(drm); drm 614 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_vga_fini(drm); drm 616 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_cli_fini(&drm->client); drm 617 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_cli_fini(&drm->master); drm 618 drivers/gpu/drm/nouveau/nouveau_drm.c kfree(drm); drm 664 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 672 drivers/gpu/drm/nouveau/nouveau_drm.c drm->old_pm_cap = pdev->pm_cap; drm 674 drivers/gpu/drm/nouveau/nouveau_drm.c NV_INFO(drm, "Disabling PCI power management to avoid bug\n"); drm 778 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 785 drivers/gpu/drm/nouveau/nouveau_drm.c client = nvxx_client(&drm->client.base); drm 798 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 801 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->old_pm_cap) drm 802 drivers/gpu/drm/nouveau/nouveau_drm.c pdev->pm_cap = drm->old_pm_cap; drm 809 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 812 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_svm_suspend(drm); drm 813 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_dmem_suspend(drm); drm 817 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "suspending console...\n"); drm 819 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "suspending display...\n"); drm 825 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "evicting buffers...\n"); drm 826 drivers/gpu/drm/nouveau/nouveau_drm.c ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); drm 828 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); drm 829 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->cechan) { drm 830 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_channel_idle(drm->cechan); drm 835 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->channel) { drm 836 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_channel_idle(drm->channel); drm 841 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "suspending fence...\n"); drm 842 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->fence && nouveau_fence(drm)->suspend) { drm 843 drivers/gpu/drm/nouveau/nouveau_drm.c if (!nouveau_fence(drm)->suspend(drm)) { drm 849 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "suspending object tree...\n"); drm 850 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_client_suspend(&drm->master.base); drm 857 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->fence && nouveau_fence(drm)->resume) drm 858 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_fence(drm)->resume(drm); drm 862 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "resuming display...\n"); drm 872 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 874 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "resuming object tree...\n"); drm 875 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_client_resume(&drm->master.base); drm 877 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "Client resume failed with error: %d\n", ret); drm 881 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "resuming fence...\n"); drm 882 drivers/gpu/drm/nouveau/nouveau_drm.c if (drm->fence && nouveau_fence(drm)->resume) drm 883 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_fence(drm)->resume(drm); drm 888 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "resuming display...\n"); drm 890 drivers/gpu/drm/nouveau/nouveau_drm.c NV_DEBUG(drm, "resuming console...\n"); drm 895 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_dmem_resume(drm); drm 896 drivers/gpu/drm/nouveau/nouveau_drm.c nouveau_svm_resume(drm); drm 999 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 1017 drivers/gpu/drm/nouveau/nouveau_drm.c NV_ERROR(drm, "resume failed with: %d\n", ret); drm 1048 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1066 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_cli_init(drm, name, cli); drm 1074 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_lock(&drm->client.mutex); drm 1075 drivers/gpu/drm/nouveau/nouveau_drm.c list_add(&cli->head, &drm->clients); drm 1076 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_unlock(&drm->client.mutex); drm 1093 drivers/gpu/drm/nouveau/nouveau_drm.c struct nouveau_drm *drm = nouveau_drm(dev); drm 1102 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_lock(&drm->client.mutex); drm 1104 drivers/gpu/drm/nouveau/nouveau_drm.c mutex_unlock(&drm->client.mutex); drm 1282 drivers/gpu/drm/nouveau/nouveau_drm.c struct drm_device *drm; drm 1290 drivers/gpu/drm/nouveau/nouveau_drm.c drm = drm_dev_alloc(&driver_platform, &pdev->dev); drm 1291 drivers/gpu/drm/nouveau/nouveau_drm.c if (IS_ERR(drm)) { drm 1292 drivers/gpu/drm/nouveau/nouveau_drm.c err = PTR_ERR(drm); drm 1296 drivers/gpu/drm/nouveau/nouveau_drm.c err = nouveau_drm_device_init(drm); drm 1300 drivers/gpu/drm/nouveau/nouveau_drm.c platform_set_drvdata(pdev, drm); drm 1302 drivers/gpu/drm/nouveau/nouveau_drm.c return drm; drm 1305 drivers/gpu/drm/nouveau/nouveau_drm.c drm_dev_put(drm); drm 94 drivers/gpu/drm/nouveau/nouveau_drv.h struct nouveau_drm *drm; drm 225 drivers/gpu/drm/nouveau/nouveau_drv.h nouveau_drm_use_coherent_gpu_mapping(struct nouveau_drm *drm) drm 227 drivers/gpu/drm/nouveau/nouveau_drv.h struct nvif_mmu *mmu = &drm->client.mmu; drm 228 drivers/gpu/drm/nouveau/nouveau_drv.h return !(mmu->type[drm->ttm.type_host[0]].type & NVIF_MEM_UNCACHED); drm 244 drivers/gpu/drm/nouveau/nouveau_drv.h dev_##l(_cli->drm->dev->dev, "%s: "f, _cli->name, ##a); \ drm 247 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_FATAL(drm,f,a...) NV_PRINTK(crit, &(drm)->client, f, ##a) drm 248 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_ERROR(drm,f,a...) NV_PRINTK(err, &(drm)->client, f, ##a) drm 249 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_WARN(drm,f,a...) NV_PRINTK(warn, &(drm)->client, f, ##a) drm 250 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_INFO(drm,f,a...) NV_PRINTK(info, &(drm)->client, f, ##a) drm 252 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_DEBUG(drm,f,a...) do { \ drm 254 drivers/gpu/drm/nouveau/nouveau_drv.h NV_PRINTK(info, &(drm)->client, f, ##a); \ drm 256 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_ATOMIC(drm,f,a...) do { \ drm 258 drivers/gpu/drm/nouveau/nouveau_drv.h NV_PRINTK(info, &(drm)->client, f, ##a); \ drm 263 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_ERROR_ONCE(drm,f,a...) NV_PRINTK_ONCE(err, &(drm)->client, f, ##a) drm 264 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_WARN_ONCE(drm,f,a...) NV_PRINTK_ONCE(warn, &(drm)->client, f, ##a) drm 265 drivers/gpu/drm/nouveau/nouveau_drv.h #define NV_INFO_ONCE(drm,f,a...) NV_PRINTK_ONCE(info, &(drm)->client, f, ##a) drm 67 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 68 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nvif_device *device = &drm->client.device; drm 76 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_trylock(&drm->client.mutex)) { drm 84 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_unlock(&drm->client.mutex); drm 99 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 100 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nvif_device *device = &drm->client.device; drm 108 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_trylock(&drm->client.mutex)) { drm 116 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_unlock(&drm->client.mutex); drm 131 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 132 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nvif_device *device = &drm->client.device; drm 140 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_trylock(&drm->client.mutex)) { drm 148 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_unlock(&drm->client.mutex); drm 163 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 164 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_channel *chan = drm->channel; drm 172 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (!mutex_trylock(&drm->client.mutex)) drm 176 drivers/gpu/drm/nouveau/nouveau_fbcon.c mutex_unlock(&drm->client.mutex); drm 190 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 191 drivers/gpu/drm/nouveau/nouveau_fbcon.c int ret = pm_runtime_get_sync(drm->dev->dev); drm 201 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 202 drivers/gpu/drm/nouveau/nouveau_fbcon.c pm_runtime_put(drm->dev->dev); drm 230 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 231 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (drm->fbcon && drm->fbcon->helper.fbdev) { drm 232 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm->fbcon->saved_flags = drm->fbcon->helper.fbdev->flags; drm 233 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm->fbcon->helper.fbdev->flags |= FBINFO_HWACCEL_DISABLED; drm 240 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 241 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (drm->fbcon && drm->fbcon->helper.fbdev) { drm 242 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm->fbcon->helper.fbdev->flags = drm->fbcon->saved_flags; drm 249 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 250 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_fbdev *fbcon = drm->fbcon; drm 251 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (fbcon && drm->channel) { drm 256 drivers/gpu/drm/nouveau/nouveau_fbcon.c nouveau_channel_idle(drm->channel); drm 270 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 271 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_fbdev *fbcon = drm->fbcon; drm 275 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) drm 278 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_FERMI) drm 312 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 313 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nvif_device *device = &drm->client.device; drm 330 drivers/gpu/drm/nouveau/nouveau_fbcon.c ret = nouveau_gem_new(&drm->client, mode_cmd.pitches[0] * drm 334 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_ERROR(drm, "failed to allocate framebuffer\n"); drm 344 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_ERROR(drm, "failed to pin fb: %d\n", ret); drm 350 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_ERROR(drm, "failed to map fb: %d\n", ret); drm 354 drivers/gpu/drm/nouveau/nouveau_fbcon.c chan = nouveau_nofbaccel ? NULL : drm->channel; drm 358 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_ERROR(drm, "failed to map fb into chan: %d\n", ret); drm 395 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_INFO(drm, "allocated %dx%d fb: 0x%llx, bo %p\n", drm 434 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); drm 436 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_ERROR(drm, "GPU lockup - switching to software fbcon\n"); drm 447 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = container_of(work, typeof(*drm), fbcon_work); drm 448 drivers/gpu/drm/nouveau/nouveau_fbcon.c int state = READ_ONCE(drm->fbcon_new_state); drm 451 drivers/gpu/drm/nouveau/nouveau_fbcon.c pm_runtime_get_sync(drm->dev->dev); drm 455 drivers/gpu/drm/nouveau/nouveau_fbcon.c nouveau_fbcon_accel_restore(drm->dev); drm 456 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm_fb_helper_set_suspend(&drm->fbcon->helper, state); drm 458 drivers/gpu/drm/nouveau/nouveau_fbcon.c nouveau_fbcon_accel_save_disable(drm->dev); drm 462 drivers/gpu/drm/nouveau/nouveau_fbcon.c nouveau_fbcon_hotplug_resume(drm->fbcon); drm 463 drivers/gpu/drm/nouveau/nouveau_fbcon.c pm_runtime_mark_last_busy(drm->dev->dev); drm 464 drivers/gpu/drm/nouveau/nouveau_fbcon.c pm_runtime_put_sync(drm->dev->dev); drm 471 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 473 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (!drm->fbcon) drm 476 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm->fbcon_new_state = state; drm 481 drivers/gpu/drm/nouveau/nouveau_fbcon.c schedule_work(&drm->fbcon_work); drm 487 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 488 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_fbdev *fbcon = drm->fbcon; drm 509 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_DEBUG(drm, "fbcon HPD event deferred until runtime resume\n"); drm 511 drivers/gpu/drm/nouveau/nouveau_fbcon.c pm_runtime_put_noidle(drm->dev->dev); drm 523 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm; drm 527 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm = nouveau_drm(fbcon->helper.dev); drm 533 drivers/gpu/drm/nouveau/nouveau_fbcon.c NV_DEBUG(drm, "Handling deferred fbcon HPD events\n"); drm 542 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 555 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm->fbcon = fbcon; drm 556 drivers/gpu/drm/nouveau/nouveau_fbcon.c INIT_WORK(&drm->fbcon_work, nouveau_fbcon_set_suspend_work); drm 570 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (drm->client.device.info.ram_size <= 32 * 1024 * 1024) drm 573 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (drm->client.device.info.ram_size <= 64 * 1024 * 1024) drm 601 drivers/gpu/drm/nouveau/nouveau_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 603 drivers/gpu/drm/nouveau/nouveau_fbcon.c if (!drm->fbcon) drm 607 drivers/gpu/drm/nouveau/nouveau_fbcon.c nouveau_fbcon_destroy(dev, drm->fbcon); drm 608 drivers/gpu/drm/nouveau/nouveau_fbcon.c kfree(drm->fbcon); drm 609 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm->fbcon = NULL; drm 76 drivers/gpu/drm/nouveau/nouveau_fence.c nouveau_local_fence(struct dma_fence *fence, struct nouveau_drm *drm) drm 82 drivers/gpu/drm/nouveau/nouveau_fence.c if (fence->context < drm->chan.context_base || drm 83 drivers/gpu/drm/nouveau/nouveau_fence.c fence->context >= drm->chan.context_base + drm->chan.nr) drm 170 drivers/gpu/drm/nouveau/nouveau_fence.c struct nouveau_fence_priv *priv = (void*)chan->drm->fence; drm 177 drivers/gpu/drm/nouveau/nouveau_fence.c fctx->context = chan->drm->chan.context_base + chan->chid; drm 179 drivers/gpu/drm/nouveau/nouveau_fence.c if (chan == chan->drm->cechan) drm 181 drivers/gpu/drm/nouveau/nouveau_fence.c else if (chan == chan->drm->channel) drm 204 drivers/gpu/drm/nouveau/nouveau_fence.c struct nouveau_fence_priv *priv = (void*)chan->drm->fence; drm 356 drivers/gpu/drm/nouveau/nouveau_fence.c f = nouveau_local_fence(fence, chan->drm); drm 381 drivers/gpu/drm/nouveau/nouveau_fence.c f = nouveau_local_fence(fence, chan->drm); drm 61 drivers/gpu/drm/nouveau/nouveau_fence.h #define nouveau_fence(drm) ((struct nouveau_fence_priv *)(drm)->fence) drm 79 drivers/gpu/drm/nouveau/nouveau_fence.h void nv17_fence_resume(struct nouveau_drm *drm); drm 43 drivers/gpu/drm/nouveau/nouveau_gem.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 44 drivers/gpu/drm/nouveau/nouveau_gem.c struct device *dev = drm->dev->dev; drm 65 drivers/gpu/drm/nouveau/nouveau_gem.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 66 drivers/gpu/drm/nouveau/nouveau_gem.c struct device *dev = drm->dev->dev; drm 140 drivers/gpu/drm/nouveau/nouveau_gem.c struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); drm 141 drivers/gpu/drm/nouveau/nouveau_gem.c struct device *dev = drm->dev->dev; drm 172 drivers/gpu/drm/nouveau/nouveau_gem.c struct nouveau_drm *drm = cli->drm; drm 194 drivers/gpu/drm/nouveau/nouveau_gem.c ret = drm_gem_object_init(drm->dev, &nvbo->bo.base, size); drm 212 drivers/gpu/drm/nouveau/nouveau_gem.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) drm 490 drivers/gpu/drm/nouveau/nouveau_gem.c struct nouveau_drm *drm = chan->drm; drm 521 drivers/gpu/drm/nouveau/nouveau_gem.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { drm 693 drivers/gpu/drm/nouveau/nouveau_gem.c struct nouveau_drm *drm = nouveau_drm(dev); drm 715 drivers/gpu/drm/nouveau/nouveau_gem.c req->vram_available = drm->gem.vram_available; drm 716 drivers/gpu/drm/nouveau/nouveau_gem.c req->gart_available = drm->gem.gart_available; drm 790 drivers/gpu/drm/nouveau/nouveau_gem.c if (drm->client.device.info.chipset >= 0x25) { drm 863 drivers/gpu/drm/nouveau/nouveau_gem.c if (drm->client.device.info.chipset >= 0x25) { drm 54 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 55 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 66 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 67 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 87 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 88 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 99 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 100 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 120 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 121 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 136 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 137 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 152 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 153 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 175 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 176 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 300 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data); drm 301 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); drm 325 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data); drm 326 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 349 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data); drm 350 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 368 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data); drm 369 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_volt *volt = nvxx_volt(&drm->client.device); drm 388 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm((struct drm_device *)data); drm 389 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 420 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 421 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 469 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 470 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 492 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 493 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_volt *volt = nvxx_volt(&drm->client.device); drm 523 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 524 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 549 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 550 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); drm 578 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 579 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 612 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 613 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 717 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 718 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); drm 719 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_therm *therm = nvxx_therm(&drm->client.device); drm 720 drivers/gpu/drm/nouveau/nouveau_hwmon.c struct nvkm_volt *volt = nvxx_volt(&drm->client.device); drm 728 drivers/gpu/drm/nouveau/nouveau_hwmon.c NV_DEBUG(drm, "Skipping hwmon registration\n"); drm 732 drivers/gpu/drm/nouveau/nouveau_hwmon.c hwmon = drm->hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL); drm 750 drivers/gpu/drm/nouveau/nouveau_hwmon.c NV_ERROR(drm, "Unable to register hwmon device: %d\n", ret); drm 40 drivers/gpu/drm/nouveau/nouveau_led.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 41 drivers/gpu/drm/nouveau/nouveau_led.c struct nvif_object *device = &drm->client.device.object; drm 57 drivers/gpu/drm/nouveau/nouveau_led.c struct nouveau_drm *drm = nouveau_drm(drm_dev); drm 58 drivers/gpu/drm/nouveau/nouveau_led.c struct nvif_object *device = &drm->client.device.object; drm 80 drivers/gpu/drm/nouveau/nouveau_led.c struct nouveau_drm *drm = nouveau_drm(dev); drm 81 drivers/gpu/drm/nouveau/nouveau_led.c struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); drm 92 drivers/gpu/drm/nouveau/nouveau_led.c drm->led = kzalloc(sizeof(*drm->led), GFP_KERNEL); drm 93 drivers/gpu/drm/nouveau/nouveau_led.c if (!drm->led) drm 95 drivers/gpu/drm/nouveau/nouveau_led.c drm->led->dev = dev; drm 97 drivers/gpu/drm/nouveau/nouveau_led.c drm->led->led.name = "nvidia-logo"; drm 98 drivers/gpu/drm/nouveau/nouveau_led.c drm->led->led.max_brightness = 255; drm 99 drivers/gpu/drm/nouveau/nouveau_led.c drm->led->led.brightness_get = nouveau_led_get_brightness; drm 100 drivers/gpu/drm/nouveau/nouveau_led.c drm->led->led.brightness_set = nouveau_led_set_brightness; drm 102 drivers/gpu/drm/nouveau/nouveau_led.c ret = led_classdev_register(dev->dev, &drm->led->led); drm 104 drivers/gpu/drm/nouveau/nouveau_led.c kfree(drm->led); drm 105 drivers/gpu/drm/nouveau/nouveau_led.c drm->led = NULL; drm 115 drivers/gpu/drm/nouveau/nouveau_led.c struct nouveau_drm *drm = nouveau_drm(dev); drm 117 drivers/gpu/drm/nouveau/nouveau_led.c if (drm->led) drm 118 drivers/gpu/drm/nouveau/nouveau_led.c led_classdev_suspend(&drm->led->led); drm 124 drivers/gpu/drm/nouveau/nouveau_led.c struct nouveau_drm *drm = nouveau_drm(dev); drm 126 drivers/gpu/drm/nouveau/nouveau_led.c if (drm->led) drm 127 drivers/gpu/drm/nouveau/nouveau_led.c led_classdev_resume(&drm->led->led); drm 133 drivers/gpu/drm/nouveau/nouveau_led.c struct nouveau_drm *drm = nouveau_drm(dev); drm 135 drivers/gpu/drm/nouveau/nouveau_led.c if (drm->led) { drm 136 drivers/gpu/drm/nouveau/nouveau_led.c led_classdev_unregister(&drm->led->led); drm 137 drivers/gpu/drm/nouveau/nouveau_led.c kfree(drm->led); drm 138 drivers/gpu/drm/nouveau/nouveau_led.c drm->led = NULL; drm 87 drivers/gpu/drm/nouveau/nouveau_mem.c nvif_vmm_put(&mem->cli->drm->client.vmm.vmm, &mem->vma[1]); drm 88 drivers/gpu/drm/nouveau/nouveau_mem.c nvif_vmm_put(&mem->cli->drm->client.vmm.vmm, &mem->vma[0]); drm 89 drivers/gpu/drm/nouveau/nouveau_mem.c mutex_lock(&mem->cli->drm->master.lock); drm 91 drivers/gpu/drm/nouveau/nouveau_mem.c mutex_unlock(&mem->cli->drm->master.lock); drm 99 drivers/gpu/drm/nouveau/nouveau_mem.c struct nouveau_drm *drm = cli->drm; drm 106 drivers/gpu/drm/nouveau/nouveau_mem.c if (!nouveau_drm_use_coherent_gpu_mapping(drm)) drm 107 drivers/gpu/drm/nouveau/nouveau_mem.c type = drm->ttm.type_ncoh[!!mem->kind]; drm 109 drivers/gpu/drm/nouveau/nouveau_mem.c type = drm->ttm.type_host[0]; drm 122 drivers/gpu/drm/nouveau/nouveau_mem.c mutex_lock(&drm->master.lock); drm 128 drivers/gpu/drm/nouveau/nouveau_mem.c mutex_unlock(&drm->master.lock); drm 137 drivers/gpu/drm/nouveau/nouveau_mem.c struct nouveau_drm *drm = cli->drm; drm 143 drivers/gpu/drm/nouveau/nouveau_mem.c mutex_lock(&drm->master.lock); drm 148 drivers/gpu/drm/nouveau/nouveau_mem.c drm->ttm.type_vram, page, size, drm 156 drivers/gpu/drm/nouveau/nouveau_mem.c drm->ttm.type_vram, page, size, drm 169 drivers/gpu/drm/nouveau/nouveau_mem.c mutex_unlock(&drm->master.lock); drm 28 drivers/gpu/drm/nouveau/nouveau_platform.c struct drm_device *drm; drm 33 drivers/gpu/drm/nouveau/nouveau_platform.c drm = nouveau_platform_device_create(func, pdev, &device); drm 34 drivers/gpu/drm/nouveau/nouveau_platform.c if (IS_ERR(drm)) drm 35 drivers/gpu/drm/nouveau/nouveau_platform.c return PTR_ERR(drm); drm 37 drivers/gpu/drm/nouveau/nouveau_platform.c ret = drm_dev_register(drm, 0); drm 39 drivers/gpu/drm/nouveau/nouveau_platform.c drm_dev_put(drm); drm 62 drivers/gpu/drm/nouveau/nouveau_prime.c struct nouveau_drm *drm = nouveau_drm(dev); drm 74 drivers/gpu/drm/nouveau/nouveau_prime.c nvbo = nouveau_bo_alloc(&drm->client, &size, &align, flags, 0, 0); drm 87 drivers/gpu/drm/nouveau/nouveau_sgdma.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 94 drivers/gpu/drm/nouveau/nouveau_sgdma.c if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) drm 40 drivers/gpu/drm/nouveau/nouveau_svm.c struct nouveau_drm *drm; drm 70 drivers/gpu/drm/nouveau/nouveau_svm.c #define SVM_DBG(s,f,a...) NV_DEBUG((s)->drm, "svm: "f"\n", ##a) drm 71 drivers/gpu/drm/nouveau/nouveau_svm.c #define SVM_ERR(s,f,a...) NV_WARN((s)->drm, "svm: "f"\n", ##a) drm 104 drivers/gpu/drm/nouveau/nouveau_svm.c NV_DEBUG((s)->vmm->cli->drm, "svm-%p: "f"\n", (s), ##a) drm 106 drivers/gpu/drm/nouveau/nouveau_svm.c NV_WARN((s)->vmm->cli->drm, "svm-%p: "f"\n", (s), ##a) drm 192 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_dmem_migrate_vma(cli->drm, vma, addr, next); drm 215 drivers/gpu/drm/nouveau/nouveau_svm.c mutex_lock(&svmm->vmm->cli->drm->svm->mutex); drm 216 drivers/gpu/drm/nouveau/nouveau_svm.c ivmm = nouveau_ivmm_find(svmm->vmm->cli->drm->svm, inst); drm 221 drivers/gpu/drm/nouveau/nouveau_svm.c mutex_unlock(&svmm->vmm->cli->drm->svm->mutex); drm 236 drivers/gpu/drm/nouveau/nouveau_svm.c mutex_lock(&svmm->vmm->cli->drm->svm->mutex); drm 237 drivers/gpu/drm/nouveau/nouveau_svm.c list_add(&ivmm->head, &svmm->vmm->cli->drm->svm->inst); drm 238 drivers/gpu/drm/nouveau/nouveau_svm.c mutex_unlock(&svmm->vmm->cli->drm->svm->mutex); drm 384 drivers/gpu/drm/nouveau/nouveau_svm.c WARN_ON(nvif_object_mthd(&svm->drm->client.vmm.vmm.object, drm 400 drivers/gpu/drm/nouveau/nouveau_svm.c WARN_ON(nvif_object_mthd(&svm->drm->client.vmm.vmm.object, drm 530 drivers/gpu/drm/nouveau/nouveau_svm.c struct nvif_object *device = &svm->drm->client.device.object; drm 704 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_dmem_convert_pfn(svm->drm, &range); drm 752 drivers/gpu/drm/nouveau/nouveau_svm.c struct nvif_object *device = &svm->drm->client.device.object; drm 781 drivers/gpu/drm/nouveau/nouveau_svm.c struct nouveau_drm *drm = svm->drm; drm 782 drivers/gpu/drm/nouveau/nouveau_svm.c struct nvif_object *device = &drm->client.device.object; drm 814 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_resume(struct nouveau_drm *drm) drm 816 drivers/gpu/drm/nouveau/nouveau_svm.c struct nouveau_svm *svm = drm->svm; drm 822 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_suspend(struct nouveau_drm *drm) drm 824 drivers/gpu/drm/nouveau/nouveau_svm.c struct nouveau_svm *svm = drm->svm; drm 830 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_fini(struct nouveau_drm *drm) drm 832 drivers/gpu/drm/nouveau/nouveau_svm.c struct nouveau_svm *svm = drm->svm; drm 835 drivers/gpu/drm/nouveau/nouveau_svm.c kfree(drm->svm); drm 836 drivers/gpu/drm/nouveau/nouveau_svm.c drm->svm = NULL; drm 841 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_init(struct nouveau_drm *drm) drm 855 drivers/gpu/drm/nouveau/nouveau_svm.c if (drm->client.device.info.family > NV_DEVICE_INFO_V0_PASCAL) drm 858 drivers/gpu/drm/nouveau/nouveau_svm.c if (!(drm->svm = svm = kzalloc(sizeof(*drm->svm), GFP_KERNEL))) drm 861 drivers/gpu/drm/nouveau/nouveau_svm.c drm->svm->drm = drm; drm 862 drivers/gpu/drm/nouveau/nouveau_svm.c mutex_init(&drm->svm->mutex); drm 863 drivers/gpu/drm/nouveau/nouveau_svm.c INIT_LIST_HEAD(&drm->svm->inst); drm 865 drivers/gpu/drm/nouveau/nouveau_svm.c ret = nvif_mclass(&drm->client.device.object, buffers); drm 868 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_fini(drm); drm 874 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_fini(drm); drm 22 drivers/gpu/drm/nouveau/nouveau_svm.h static inline void nouveau_svm_init(struct nouveau_drm *drm) {} drm 23 drivers/gpu/drm/nouveau/nouveau_svm.h static inline void nouveau_svm_fini(struct nouveau_drm *drm) {} drm 24 drivers/gpu/drm/nouveau/nouveau_svm.h static inline void nouveau_svm_suspend(struct nouveau_drm *drm) {} drm 25 drivers/gpu/drm/nouveau/nouveau_svm.h static inline void nouveau_svm_resume(struct nouveau_drm *drm) {} drm 65 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 68 drivers/gpu/drm/nouveau/nouveau_ttm.c if (drm->client.device.info.ram_size == 0) drm 71 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg); drm 103 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 106 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg); drm 129 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nouveau_drm *drm = nouveau_bdev(bo->bdev); drm 133 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg); drm 165 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev); drm 167 drivers/gpu/drm/nouveau/nouveau_ttm.c return ttm_bo_mmap(filp, vma, &drm->ttm.bdev); drm 171 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_ttm_init_host(struct nouveau_drm *drm, u8 kind) drm 173 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nvif_mmu *mmu = &drm->client.mmu; drm 181 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->ttm.type_host[!!kind] = typei; drm 187 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->ttm.type_ncoh[!!kind] = typei; drm 192 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_ttm_init(struct nouveau_drm *drm) drm 194 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nvkm_device *device = nvxx_device(&drm->client.device); drm 196 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nvif_mmu *mmu = &drm->client.mmu; drm 197 drivers/gpu/drm/nouveau/nouveau_ttm.c struct drm_device *dev = drm->dev; drm 200 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_ttm_init_host(drm, 0); drm 204 drivers/gpu/drm/nouveau/nouveau_ttm.c if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && drm 205 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->client.device.info.chipset != 0x50) { drm 206 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_ttm_init_host(drm, NVIF_MEM_KIND); drm 211 drivers/gpu/drm/nouveau/nouveau_ttm.c if (drm->client.device.info.platform != NV_DEVICE_INFO_V0_SOC && drm 212 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { drm 220 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->ttm.type_vram = typei; drm 222 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->ttm.type_vram = -1; drm 226 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->agp.bridge = pci->agp.bridge; drm 227 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->agp.base = pci->agp.base; drm 228 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->agp.size = pci->agp.size; drm 229 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->agp.cma = pci->agp.cma; drm 232 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = ttm_bo_device_init(&drm->ttm.bdev, drm 235 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->client.mmu.dmabits <= 32 ? true : false); drm 237 drivers/gpu/drm/nouveau/nouveau_ttm.c NV_ERROR(drm, "error initialising bo driver, %d\n", ret); drm 242 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->gem.vram_available = drm->client.device.info.ram_user; drm 247 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM, drm 248 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->gem.vram_available >> PAGE_SHIFT); drm 250 drivers/gpu/drm/nouveau/nouveau_ttm.c NV_ERROR(drm, "VRAM mm init failed, %d\n", ret); drm 254 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1), drm 258 drivers/gpu/drm/nouveau/nouveau_ttm.c if (!drm->agp.bridge) { drm 259 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->gem.gart_available = drm->client.vmm.vmm.limit; drm 261 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->gem.gart_available = drm->agp.size; drm 264 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT, drm 265 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->gem.gart_available >> PAGE_SHIFT); drm 267 drivers/gpu/drm/nouveau/nouveau_ttm.c NV_ERROR(drm, "GART mm init failed, %d\n", ret); drm 271 drivers/gpu/drm/nouveau/nouveau_ttm.c NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20)); drm 272 drivers/gpu/drm/nouveau/nouveau_ttm.c NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20)); drm 277 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_ttm_fini(struct nouveau_drm *drm) drm 279 drivers/gpu/drm/nouveau/nouveau_ttm.c struct nvkm_device *device = nvxx_device(&drm->client.device); drm 281 drivers/gpu/drm/nouveau/nouveau_ttm.c ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM); drm 282 drivers/gpu/drm/nouveau/nouveau_ttm.c ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT); drm 284 drivers/gpu/drm/nouveau/nouveau_ttm.c ttm_bo_device_release(&drm->ttm.bdev); drm 286 drivers/gpu/drm/nouveau/nouveau_ttm.c arch_phys_wc_del(drm->ttm.mtrr); drm 287 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->ttm.mtrr = 0; drm 18 drivers/gpu/drm/nouveau/nouveau_ttm.h int nouveau_ttm_init(struct nouveau_drm *drm); drm 19 drivers/gpu/drm/nouveau/nouveau_ttm.h void nouveau_ttm_fini(struct nouveau_drm *drm); drm 16 drivers/gpu/drm/nouveau/nouveau_vga.c struct nouveau_drm *drm = nouveau_drm(priv); drm 17 drivers/gpu/drm/nouveau/nouveau_vga.c struct nvif_object *device = &drm->client.device.object; drm 19 drivers/gpu/drm/nouveau/nouveau_vga.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE && drm 20 drivers/gpu/drm/nouveau/nouveau_vga.c drm->client.device.info.chipset >= 0x4c) drm 23 drivers/gpu/drm/nouveau/nouveau_vga.c if (drm->client.device.info.chipset >= 0x40) drm 86 drivers/gpu/drm/nouveau/nouveau_vga.c nouveau_vga_init(struct nouveau_drm *drm) drm 88 drivers/gpu/drm/nouveau/nouveau_vga.c struct drm_device *dev = drm->dev; drm 104 drivers/gpu/drm/nouveau/nouveau_vga.c vga_switcheroo_init_domain_pm_ops(drm->dev->dev, &drm->vga_pm_domain); drm 108 drivers/gpu/drm/nouveau/nouveau_vga.c nouveau_vga_fini(struct nouveau_drm *drm) drm 110 drivers/gpu/drm/nouveau/nouveau_vga.c struct drm_device *dev = drm->dev; drm 124 drivers/gpu/drm/nouveau/nouveau_vga.c vga_switcheroo_fini_domain_pm_ops(drm->dev->dev); drm 33 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 34 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_channel *chan = drm->channel; drm 53 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 54 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_channel *chan = drm->channel; drm 80 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 81 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_channel *chan = drm->channel; drm 137 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 138 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nouveau_channel *chan = drm->channel; drm 139 drivers/gpu/drm/nouveau/nv04_fbcon.c struct nvif_device *device = &drm->client.device; drm 93 drivers/gpu/drm/nouveau/nv04_fence.c nv04_fence_destroy(struct nouveau_drm *drm) drm 95 drivers/gpu/drm/nouveau/nv04_fence.c struct nv04_fence_priv *priv = drm->fence; drm 96 drivers/gpu/drm/nouveau/nv04_fence.c drm->fence = NULL; drm 101 drivers/gpu/drm/nouveau/nv04_fence.c nv04_fence_create(struct nouveau_drm *drm) drm 105 drivers/gpu/drm/nouveau/nv04_fence.c priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); drm 83 drivers/gpu/drm/nouveau/nv10_fence.c nv10_fence_destroy(struct nouveau_drm *drm) drm 85 drivers/gpu/drm/nouveau/nv10_fence.c struct nv10_fence_priv *priv = drm->fence; drm 90 drivers/gpu/drm/nouveau/nv10_fence.c drm->fence = NULL; drm 95 drivers/gpu/drm/nouveau/nv10_fence.c nv10_fence_create(struct nouveau_drm *drm) drm 99 drivers/gpu/drm/nouveau/nv10_fence.c priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); drm 38 drivers/gpu/drm/nouveau/nv17_fence.c struct nv10_fence_priv *priv = chan->drm->fence; drm 77 drivers/gpu/drm/nouveau/nv17_fence.c struct nv10_fence_priv *priv = chan->drm->fence; drm 107 drivers/gpu/drm/nouveau/nv17_fence.c nv17_fence_resume(struct nouveau_drm *drm) drm 109 drivers/gpu/drm/nouveau/nv17_fence.c struct nv10_fence_priv *priv = drm->fence; drm 115 drivers/gpu/drm/nouveau/nv17_fence.c nv17_fence_create(struct nouveau_drm *drm) drm 120 drivers/gpu/drm/nouveau/nv17_fence.c priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); drm 130 drivers/gpu/drm/nouveau/nv17_fence.c ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, drm 144 drivers/gpu/drm/nouveau/nv17_fence.c nv10_fence_destroy(drm); drm 34 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 35 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_channel *chan = drm->channel; drm 69 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 70 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_channel *chan = drm->channel; drm 97 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 98 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_channel *chan = drm->channel; drm 154 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 155 drivers/gpu/drm/nouveau/nv50_fbcon.c struct nouveau_channel *chan = drm->channel; drm 38 drivers/gpu/drm/nouveau/nv50_fence.c struct nv10_fence_priv *priv = chan->drm->fence; drm 68 drivers/gpu/drm/nouveau/nv50_fence.c nv50_fence_create(struct nouveau_drm *drm) drm 73 drivers/gpu/drm/nouveau/nv50_fence.c priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); drm 83 drivers/gpu/drm/nouveau/nv50_fence.c ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, drm 97 drivers/gpu/drm/nouveau/nv50_fence.c nv10_fence_destroy(drm); drm 90 drivers/gpu/drm/nouveau/nv84_fence.c struct nv84_fence_priv *priv = chan->drm->fence; drm 97 drivers/gpu/drm/nouveau/nv84_fence.c struct nv84_fence_priv *priv = chan->drm->fence; drm 112 drivers/gpu/drm/nouveau/nv84_fence.c struct nv84_fence_priv *priv = chan->drm->fence; drm 138 drivers/gpu/drm/nouveau/nv84_fence.c nv84_fence_suspend(struct nouveau_drm *drm) drm 140 drivers/gpu/drm/nouveau/nv84_fence.c struct nv84_fence_priv *priv = drm->fence; drm 143 drivers/gpu/drm/nouveau/nv84_fence.c priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan.nr)); drm 145 drivers/gpu/drm/nouveau/nv84_fence.c for (i = 0; i < drm->chan.nr; i++) drm 153 drivers/gpu/drm/nouveau/nv84_fence.c nv84_fence_resume(struct nouveau_drm *drm) drm 155 drivers/gpu/drm/nouveau/nv84_fence.c struct nv84_fence_priv *priv = drm->fence; drm 159 drivers/gpu/drm/nouveau/nv84_fence.c for (i = 0; i < drm->chan.nr; i++) drm 167 drivers/gpu/drm/nouveau/nv84_fence.c nv84_fence_destroy(struct nouveau_drm *drm) drm 169 drivers/gpu/drm/nouveau/nv84_fence.c struct nv84_fence_priv *priv = drm->fence; drm 174 drivers/gpu/drm/nouveau/nv84_fence.c drm->fence = NULL; drm 179 drivers/gpu/drm/nouveau/nv84_fence.c nv84_fence_create(struct nouveau_drm *drm) drm 185 drivers/gpu/drm/nouveau/nv84_fence.c priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); drm 200 drivers/gpu/drm/nouveau/nv84_fence.c domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : drm 206 drivers/gpu/drm/nouveau/nv84_fence.c ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0, drm 220 drivers/gpu/drm/nouveau/nv84_fence.c nv84_fence_destroy(drm); drm 34 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 35 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_channel *chan = drm->channel; drm 69 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 70 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_channel *chan = drm->channel; drm 97 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); drm 98 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_channel *chan = drm->channel; drm 154 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_drm *drm = nouveau_drm(dev); drm 155 drivers/gpu/drm/nouveau/nvc0_fbcon.c struct nouveau_channel *chan = drm->channel; drm 76 drivers/gpu/drm/nouveau/nvc0_fence.c nvc0_fence_create(struct nouveau_drm *drm) drm 78 drivers/gpu/drm/nouveau/nvc0_fence.c int ret = nv84_fence_create(drm); drm 80 drivers/gpu/drm/nouveau/nvc0_fence.c struct nv84_fence_priv *priv = drm->fence; drm 273 drivers/gpu/drm/panel/panel-arm-versatile.c mode = drm_mode_duplicate(panel->drm, &vpanel->panel_type->mode); drm 171 drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c mode = drm_mode_duplicate(panel->drm, &feiyang_default_mode); drm 666 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &srgb_320x240_mode); drm 669 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &srgb_360x240_mode); drm 673 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &prgb_320x240_mode); drm 676 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &yuv_640x320_mode); drm 679 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &yuv_720x360_mode); drm 682 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &itu_r_bt_656_720_mode); drm 685 drivers/gpu/drm/panel/panel-ilitek-ili9322.c mode = drm_mode_duplicate(panel->drm, &itu_r_bt_656_640_mode); drm 396 drivers/gpu/drm/panel/panel-ilitek-ili9881c.c mode = drm_mode_duplicate(panel->drm, &bananapi_default_mode); drm 214 drivers/gpu/drm/panel/panel-innolux-p079zca.c DRM_DEV_ERROR(panel->drm->dev, drm 412 drivers/gpu/drm/panel/panel-innolux-p079zca.c mode = drm_mode_duplicate(panel->drm, m); drm 414 drivers/gpu/drm/panel/panel-innolux-p079zca.c DRM_DEV_ERROR(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 309 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 313 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c DRM_DEV_ERROR(panel->drm->dev, drm 340 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 342 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c DRM_DEV_ERROR(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 149 drivers/gpu/drm/panel/panel-lg-lb035q02.c mode = drm_mode_duplicate(panel->drm, &lb035q02_mode); drm 217 drivers/gpu/drm/panel/panel-lg-lg4573.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 219 drivers/gpu/drm/panel/panel-lg-lg4573.c dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 115 drivers/gpu/drm/panel/panel-lvds.c mode = drm_mode_create(lvds->panel.drm); drm 131 drivers/gpu/drm/panel/panel-nec-nl8048hl11.c mode = drm_mode_duplicate(panel->drm, &nl8048_mode); drm 216 drivers/gpu/drm/panel/panel-novatek-nt39016.c mode = drm_mode_duplicate(drm_panel->drm, &panel_info->display_mode); drm 149 drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c struct drm_device *drm = lcd->panel.drm; drm 158 drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c mode = drm_mode_create(drm); drm 160 drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c dev_err(drm->dev, "failed to add mode %ux%u@%u\n", drm 356 drivers/gpu/drm/panel/panel-orisetech-otm8009a.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 120 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c mode = drm_mode_duplicate(panel->drm, osd101t2587->default_mode); drm 122 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 173 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 175 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 317 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c struct drm_device *drm = panel->drm; drm 325 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c mode = drm_mode_duplicate(drm, m); drm 327 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c dev_err(drm->dev, "failed to add mode %ux%u@%u\n", drm 444 drivers/gpu/drm/panel/panel-raydium-rm67191.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 342 drivers/gpu/drm/panel/panel-raydium-rm68200.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 238 drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 130 drivers/gpu/drm/panel/panel-ronbo-rb070d30.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 151 drivers/gpu/drm/panel/panel-samsung-s6d16d0.c mode = drm_mode_duplicate(panel->drm, &samsung_s6d16d0_mode); drm 654 drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c mode = drm_mode_duplicate(panel->drm, ctx->desc->mode); drm 408 drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 370 drivers/gpu/drm/panel/panel-samsung-s6e63m0.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 62 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c struct drm_device *drm = panel->base.drm; drm 74 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c mode = drm_mode_create(drm); drm 76 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c dev_err(drm->dev, "failed to add mode %ux%u\n", drm 95 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c mode = drm_mode_duplicate(drm, m); drm 97 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c dev_err(drm->dev, "failed to add mode %ux%u@%u\n", drm 285 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 287 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 108 drivers/gpu/drm/panel/panel-sharp-ls037v7dw01.c mode = drm_mode_duplicate(panel->drm, &ls037v7dw01_mode); drm 217 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 219 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 124 drivers/gpu/drm/panel/panel-simple.c struct drm_device *drm = panel->base.drm; drm 133 drivers/gpu/drm/panel/panel-simple.c mode = drm_mode_create(drm); drm 135 drivers/gpu/drm/panel/panel-simple.c dev_err(drm->dev, "failed to add mode %ux%u\n", drm 157 drivers/gpu/drm/panel/panel-simple.c struct drm_device *drm = panel->base.drm; drm 164 drivers/gpu/drm/panel/panel-simple.c mode = drm_mode_duplicate(drm, m); drm 166 drivers/gpu/drm/panel/panel-simple.c dev_err(drm->dev, "failed to add mode %ux%u@%u\n", drm 188 drivers/gpu/drm/panel/panel-simple.c struct drm_device *drm = panel->base.drm; drm 197 drivers/gpu/drm/panel/panel-simple.c mode = drm_mode_duplicate(drm, &panel->override_mode); drm 202 drivers/gpu/drm/panel/panel-simple.c dev_err(drm->dev, "failed to add override mode\n"); drm 273 drivers/gpu/drm/panel/panel-sitronix-st7701.c mode = drm_mode_duplicate(panel->drm, desc_mode); drm 178 drivers/gpu/drm/panel/panel-sitronix-st7789v.c mode = drm_mode_duplicate(panel->drm, &default_mode); drm 180 drivers/gpu/drm/panel/panel-sitronix-st7789v.c dev_err(panel->drm->dev, "failed to add mode %ux%ux@%u\n", drm 529 drivers/gpu/drm/panel/panel-sony-acx565akm.c mode = drm_mode_duplicate(panel->drm, &acx565akm_mode); drm 295 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c mode = drm_mode_duplicate(panel->drm, &td028ttec1_mode); drm 354 drivers/gpu/drm/panel/panel-tpo-td043mtea1.c mode = drm_mode_duplicate(panel->drm, &td043mtea1_mode); drm 397 drivers/gpu/drm/panel/panel-tpo-tpg110.c mode = drm_mode_duplicate(panel->drm, &tpg->panel_mode->mode); drm 54 drivers/gpu/drm/pl111/pl111_display.c struct drm_device *drm = crtc->dev; drm 55 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 125 drivers/gpu/drm/pl111/pl111_display.c struct drm_device *drm = crtc->dev; drm 126 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 140 drivers/gpu/drm/pl111/pl111_display.c dev_err(drm->dev, drm 347 drivers/gpu/drm/pl111/pl111_display.c priv->variant_display_enable(drm, fb->format->format); drm 360 drivers/gpu/drm/pl111/pl111_display.c struct drm_device *drm = crtc->dev; drm 361 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 381 drivers/gpu/drm/pl111/pl111_display.c priv->variant_display_disable(drm); drm 393 drivers/gpu/drm/pl111/pl111_display.c struct drm_device *drm = crtc->dev; drm 394 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 421 drivers/gpu/drm/pl111/pl111_display.c struct drm_device *drm = crtc->dev; drm 422 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 432 drivers/gpu/drm/pl111/pl111_display.c struct drm_device *drm = crtc->dev; drm 433 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 537 drivers/gpu/drm/pl111/pl111_display.c pl111_init_clock_divider(struct drm_device *drm) drm 539 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 540 drivers/gpu/drm/pl111/pl111_display.c struct clk *parent = devm_clk_get(drm->dev, "clcdclk"); drm 553 drivers/gpu/drm/pl111/pl111_display.c dev_err(drm->dev, "CLCD: unable to get clcdclk.\n"); drm 567 drivers/gpu/drm/pl111/pl111_display.c ret = devm_clk_hw_register(drm->dev, div); drm 573 drivers/gpu/drm/pl111/pl111_display.c int pl111_display_init(struct drm_device *drm) drm 575 drivers/gpu/drm/pl111/pl111_display.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 578 drivers/gpu/drm/pl111/pl111_display.c ret = pl111_init_clock_divider(drm); drm 587 drivers/gpu/drm/pl111/pl111_display.c ret = drm_simple_display_pipe_init(drm, &priv->pipe, drm 60 drivers/gpu/drm/pl111/pl111_drm.h struct drm_device *drm; drm 80 drivers/gpu/drm/pl111/pl111_drm.h void (*variant_display_enable) (struct drm_device *drm, u32 format); drm 81 drivers/gpu/drm/pl111/pl111_drm.h void (*variant_display_disable) (struct drm_device *drm); drm 258 drivers/gpu/drm/pl111/pl111_drv.c struct drm_device *drm; drm 265 drivers/gpu/drm/pl111/pl111_drv.c drm = drm_dev_alloc(&pl111_drm_driver, dev); drm 266 drivers/gpu/drm/pl111/pl111_drv.c if (IS_ERR(drm)) drm 267 drivers/gpu/drm/pl111/pl111_drv.c return PTR_ERR(drm); drm 268 drivers/gpu/drm/pl111/pl111_drv.c amba_set_drvdata(amba_dev, drm); drm 269 drivers/gpu/drm/pl111/pl111_drv.c priv->drm = drm; drm 270 drivers/gpu/drm/pl111/pl111_drv.c drm->dev_private = priv; drm 318 drivers/gpu/drm/pl111/pl111_drv.c ret = pl111_modeset_init(drm); drm 322 drivers/gpu/drm/pl111/pl111_drv.c ret = drm_dev_register(drm, 0); drm 326 drivers/gpu/drm/pl111/pl111_drv.c drm_fbdev_generic_setup(drm, priv->variant->fb_bpp); drm 331 drivers/gpu/drm/pl111/pl111_drv.c drm_dev_put(drm); drm 340 drivers/gpu/drm/pl111/pl111_drv.c struct drm_device *drm = amba_get_drvdata(amba_dev); drm 341 drivers/gpu/drm/pl111/pl111_drv.c struct pl111_drm_dev_private *priv = drm->dev_private; drm 343 drivers/gpu/drm/pl111/pl111_drv.c drm_dev_unregister(drm); drm 346 drivers/gpu/drm/pl111/pl111_drv.c drm_mode_config_cleanup(drm); drm 347 drivers/gpu/drm/pl111/pl111_drv.c drm_dev_put(drm); drm 95 drivers/gpu/drm/pl111/pl111_versatile.c static void pl111_integrator_enable(struct drm_device *drm, u32 format) drm 99 drivers/gpu/drm/pl111/pl111_versatile.c dev_info(drm->dev, "enable Integrator CLCD connectors\n"); drm 117 drivers/gpu/drm/pl111/pl111_versatile.c dev_err(drm->dev, "unhandled format on Integrator 0x%08x\n", drm 145 drivers/gpu/drm/pl111/pl111_versatile.c static void pl111_versatile_disable(struct drm_device *drm) drm 147 drivers/gpu/drm/pl111/pl111_versatile.c dev_info(drm->dev, "disable Versatile CLCD connectors\n"); drm 154 drivers/gpu/drm/pl111/pl111_versatile.c static void pl111_versatile_enable(struct drm_device *drm, u32 format) drm 158 drivers/gpu/drm/pl111/pl111_versatile.c dev_info(drm->dev, "enable Versatile CLCD connectors\n"); drm 180 drivers/gpu/drm/pl111/pl111_versatile.c dev_err(drm->dev, "unhandled format on Versatile 0x%08x\n", drm 198 drivers/gpu/drm/pl111/pl111_versatile.c static void pl111_realview_clcd_disable(struct drm_device *drm) drm 200 drivers/gpu/drm/pl111/pl111_versatile.c dev_info(drm->dev, "disable RealView CLCD connectors\n"); drm 207 drivers/gpu/drm/pl111/pl111_versatile.c static void pl111_realview_clcd_enable(struct drm_device *drm, u32 format) drm 209 drivers/gpu/drm/pl111/pl111_versatile.c dev_info(drm->dev, "enable RealView CLCD connectors\n"); drm 208 drivers/gpu/drm/radeon/radeon_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/radeon drm 492 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c struct drm_device *drm = data; drm 515 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); drm 547 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs, drm 603 drivers/gpu/drm/rockchip/inno_hdmi.c static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) drm 608 drivers/gpu/drm/rockchip/inno_hdmi.c encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); drm 620 drivers/gpu/drm/rockchip/inno_hdmi.c drm_encoder_init(drm, encoder, &inno_hdmi_encoder_funcs, drm 627 drivers/gpu/drm/rockchip/inno_hdmi.c drm_connector_init(drm, &hdmi->connector, &inno_hdmi_connector_funcs, drm 813 drivers/gpu/drm/rockchip/inno_hdmi.c struct drm_device *drm = data; drm 824 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi->drm_dev = drm; drm 868 drivers/gpu/drm/rockchip/inno_hdmi.c ret = inno_hdmi_register(drm, hdmi); drm 542 drivers/gpu/drm/rockchip/rk3066_hdmi.c rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) drm 548 drivers/gpu/drm/rockchip/rk3066_hdmi.c drm_of_find_possible_crtcs(drm, dev->of_node); drm 560 drivers/gpu/drm/rockchip/rk3066_hdmi.c drm_encoder_init(drm, encoder, &rk3066_hdmi_encoder_funcs, drm 567 drivers/gpu/drm/rockchip/rk3066_hdmi.c drm_connector_init(drm, &hdmi->connector, drm 744 drivers/gpu/drm/rockchip/rk3066_hdmi.c struct drm_device *drm = data; drm 755 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi->drm_dev = drm; drm 807 drivers/gpu/drm/rockchip/rk3066_hdmi.c ret = rk3066_hdmi_register(drm, hdmi); drm 240 drivers/gpu/drm/rockchip/rockchip_drm_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 242 drivers/gpu/drm/rockchip/rockchip_drm_drv.c return drm_mode_config_helper_suspend(drm); drm 247 drivers/gpu/drm/rockchip/rockchip_drm_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 249 drivers/gpu/drm/rockchip/rockchip_drm_drv.c return drm_mode_config_helper_resume(drm); drm 443 drivers/gpu/drm/rockchip/rockchip_drm_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 445 drivers/gpu/drm/rockchip/rockchip_drm_drv.c if (drm) drm 446 drivers/gpu/drm/rockchip/rockchip_drm_drv.c drm_atomic_helper_shutdown(drm); drm 20 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = rk_obj->base.dev; drm 21 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct rockchip_drm_private *private = drm->dev_private; drm 61 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = rk_obj->base.dev; drm 62 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct rockchip_drm_private *private = drm->dev_private; drm 77 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = rk_obj->base.dev; drm 103 drivers/gpu/drm/rockchip/rockchip_drm_gem.c dma_sync_sg_for_device(drm->dev, rk_obj->sgt->sgl, rk_obj->sgt->nents, drm 157 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = obj->dev; drm 164 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj->kvaddr = dma_alloc_attrs(drm->dev, obj->size, drm 179 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = obj->dev; drm 180 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct rockchip_drm_private *private = drm->dev_private; drm 198 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = obj->dev; drm 200 drivers/gpu/drm/rockchip/rockchip_drm_gem.c dma_free_attrs(drm->dev, obj->size, rk_obj->kvaddr, rk_obj->dma_addr, drm 229 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = obj->dev; drm 231 drivers/gpu/drm/rockchip/rockchip_drm_gem.c return dma_mmap_attrs(drm->dev, vma, rk_obj->kvaddr, rk_obj->dma_addr, drm 298 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size) drm 311 drivers/gpu/drm/rockchip/rockchip_drm_gem.c drm_gem_object_init(drm, obj, size); drm 317 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rockchip_gem_create_object(struct drm_device *drm, unsigned int size, drm 323 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj = rockchip_gem_alloc_object(drm, size); drm 344 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = obj->dev; drm 345 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct rockchip_drm_private *private = drm->dev_private; drm 352 drivers/gpu/drm/rockchip/rockchip_drm_gem.c dma_unmap_sg(drm->dev, rk_obj->sgt->sgl, drm 372 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm, unsigned int size, drm 379 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj = rockchip_gem_create_object(drm, size, false); drm 439 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = obj->dev; drm 450 drivers/gpu/drm/rockchip/rockchip_drm_gem.c ret = dma_get_sgtable_attrs(drm->dev, sgt, rk_obj->kvaddr, drm 480 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rockchip_gem_iommu_map_sg(struct drm_device *drm, drm 490 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rockchip_gem_dma_map_sg(struct drm_device *drm, drm 495 drivers/gpu/drm/rockchip/rockchip_drm_gem.c int count = dma_map_sg(drm->dev, sg->sgl, sg->nents, drm 502 drivers/gpu/drm/rockchip/rockchip_drm_gem.c dma_unmap_sg(drm->dev, sg->sgl, sg->nents, drm 513 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rockchip_gem_prime_import_sg_table(struct drm_device *drm, drm 517 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct rockchip_drm_private *private = drm->dev_private; drm 521 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj = rockchip_gem_alloc_object(drm, attach->dmabuf->size); drm 526 drivers/gpu/drm/rockchip/rockchip_drm_gem.c ret = rockchip_gem_iommu_map_sg(drm, attach, sg, rk_obj); drm 528 drivers/gpu/drm/rockchip/rockchip_drm_gem.c ret = rockchip_gem_dma_map_sg(drm, attach, sg, rk_obj); drm 45 drivers/gpu/drm/rockchip/rockchip_drm_gem.h rockchip_gem_create_object(struct drm_device *drm, unsigned int size, drm 1408 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_device *drm = vop->drm_dev; drm 1411 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_lock(&drm->event_lock); drm 1417 drivers/gpu/drm/rockchip/rockchip_drm_vop.c spin_unlock(&drm->event_lock); drm 103 drivers/gpu/drm/scheduler/gpu_scheduler_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/scheduler drm 347 drivers/gpu/drm/stm/ltdc.c static inline u32 get_pixelformat_without_alpha(u32 drm) drm 349 drivers/gpu/drm/stm/ltdc.c switch (drm) { drm 491 drivers/gpu/drm/sun4i/sun4i_backend.c struct drm_device *drm = state->dev; drm 506 drivers/gpu/drm/sun4i/sun4i_backend.c drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { drm 783 drivers/gpu/drm/sun4i/sun4i_backend.c struct drm_device *drm = data; drm 784 drivers/gpu/drm/sun4i/sun4i_backend.c struct sun4i_drv *drv = drm->dev_private; drm 805 drivers/gpu/drm/sun4i/sun4i_backend.c ret = of_dma_configure(drm->dev, dev->of_node, true); drm 815 drivers/gpu/drm/sun4i/sun4i_backend.c drm->dev->dma_pfn_offset = PHYS_PFN_OFFSET; drm 186 drivers/gpu/drm/sun4i/sun4i_crtc.c struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm, drm 195 drivers/gpu/drm/sun4i/sun4i_crtc.c scrtc = devm_kzalloc(drm->dev, sizeof(*scrtc), GFP_KERNEL); drm 202 drivers/gpu/drm/sun4i/sun4i_crtc.c planes = sunxi_engine_layers_init(drm, engine); drm 204 drivers/gpu/drm/sun4i/sun4i_crtc.c dev_err(drm->dev, "Couldn't create the planes\n"); drm 224 drivers/gpu/drm/sun4i/sun4i_crtc.c ret = drm_crtc_init_with_planes(drm, &scrtc->crtc, drm 230 drivers/gpu/drm/sun4i/sun4i_crtc.c dev_err(drm->dev, "Couldn't init DRM CRTC\n"); drm 25 drivers/gpu/drm/sun4i/sun4i_crtc.h struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm, drm 32 drivers/gpu/drm/sun4i/sun4i_drv.c struct drm_device *drm, drm 38 drivers/gpu/drm/sun4i/sun4i_drv.c return drm_gem_cma_dumb_create_internal(file_priv, drm, args); drm 61 drivers/gpu/drm/sun4i/sun4i_drv.c struct drm_device *drm; drm 65 drivers/gpu/drm/sun4i/sun4i_drv.c drm = drm_dev_alloc(&sun4i_drv_driver, dev); drm 66 drivers/gpu/drm/sun4i/sun4i_drv.c if (IS_ERR(drm)) drm 67 drivers/gpu/drm/sun4i/sun4i_drv.c return PTR_ERR(drm); drm 75 drivers/gpu/drm/sun4i/sun4i_drv.c dev_set_drvdata(dev, drm); drm 76 drivers/gpu/drm/sun4i/sun4i_drv.c drm->dev_private = drv; drm 83 drivers/gpu/drm/sun4i/sun4i_drv.c dev_err(drm->dev, "Couldn't claim our memory region\n"); drm 87 drivers/gpu/drm/sun4i/sun4i_drv.c drm_mode_config_init(drm); drm 89 drivers/gpu/drm/sun4i/sun4i_drv.c ret = component_bind_all(drm->dev, drm); drm 91 drivers/gpu/drm/sun4i/sun4i_drv.c dev_err(drm->dev, "Couldn't bind all pipelines components\n"); drm 96 drivers/gpu/drm/sun4i/sun4i_drv.c ret = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 100 drivers/gpu/drm/sun4i/sun4i_drv.c drm->irq_enabled = true; drm 105 drivers/gpu/drm/sun4i/sun4i_drv.c sun4i_framebuffer_init(drm); drm 108 drivers/gpu/drm/sun4i/sun4i_drv.c drm_kms_helper_poll_init(drm); drm 110 drivers/gpu/drm/sun4i/sun4i_drv.c ret = drm_dev_register(drm, 0); drm 114 drivers/gpu/drm/sun4i/sun4i_drv.c drm_fbdev_generic_setup(drm, 32); drm 119 drivers/gpu/drm/sun4i/sun4i_drv.c drm_kms_helper_poll_fini(drm); drm 121 drivers/gpu/drm/sun4i/sun4i_drv.c drm_mode_config_cleanup(drm); drm 124 drivers/gpu/drm/sun4i/sun4i_drv.c drm_dev_put(drm); drm 130 drivers/gpu/drm/sun4i/sun4i_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 132 drivers/gpu/drm/sun4i/sun4i_drv.c drm_dev_unregister(drm); drm 133 drivers/gpu/drm/sun4i/sun4i_drv.c drm_kms_helper_poll_fini(drm); drm 134 drivers/gpu/drm/sun4i/sun4i_drv.c drm_atomic_helper_shutdown(drm); drm 135 drivers/gpu/drm/sun4i/sun4i_drv.c drm_mode_config_cleanup(drm); drm 140 drivers/gpu/drm/sun4i/sun4i_drv.c drm_dev_put(drm); drm 42 drivers/gpu/drm/sun4i/sun4i_framebuffer.c void sun4i_framebuffer_init(struct drm_device *drm) drm 44 drivers/gpu/drm/sun4i/sun4i_framebuffer.c drm_mode_config_reset(drm); drm 46 drivers/gpu/drm/sun4i/sun4i_framebuffer.c drm->mode_config.max_width = 8192; drm 47 drivers/gpu/drm/sun4i/sun4i_framebuffer.c drm->mode_config.max_height = 8192; drm 49 drivers/gpu/drm/sun4i/sun4i_framebuffer.c drm->mode_config.funcs = &sun4i_de_mode_config_funcs; drm 50 drivers/gpu/drm/sun4i/sun4i_framebuffer.c drm->mode_config.helper_private = &sun4i_de_mode_config_helpers; drm 12 drivers/gpu/drm/sun4i/sun4i_framebuffer.h void sun4i_framebuffer_init(struct drm_device *drm); drm 560 drivers/gpu/drm/sun4i/sun4i_frontend.c struct drm_device *drm = data; drm 561 drivers/gpu/drm/sun4i/sun4i_frontend.c struct sun4i_drv *drv = drm->dev_private; drm 492 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c struct drm_device *drm = data; drm 493 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c struct sun4i_drv *drv = drm->dev_private; drm 613 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c ret = drm_encoder_init(drm, drm 623 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, drm 643 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c ret = drm_connector_init_with_ddc(drm, &hdmi->connector, drm 189 drivers/gpu/drm/sun4i/sun4i_layer.c static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, drm 199 drivers/gpu/drm/sun4i/sun4i_layer.c layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); drm 212 drivers/gpu/drm/sun4i/sun4i_layer.c ret = drm_universal_plane_init(drm, &layer->plane, 0, drm 217 drivers/gpu/drm/sun4i/sun4i_layer.c dev_err(drm->dev, "Couldn't initialize layer\n"); drm 231 drivers/gpu/drm/sun4i/sun4i_layer.c struct drm_plane **sun4i_layers_init(struct drm_device *drm, drm 239 drivers/gpu/drm/sun4i/sun4i_layer.c planes = devm_kcalloc(drm->dev, SUN4I_BACKEND_NUM_LAYERS + 1, drm 248 drivers/gpu/drm/sun4i/sun4i_layer.c layer = sun4i_layer_init_one(drm, backend, type); drm 250 drivers/gpu/drm/sun4i/sun4i_layer.c dev_err(drm->dev, "Couldn't initialize %s plane\n", drm 39 drivers/gpu/drm/sun4i/sun4i_layer.h struct drm_plane **sun4i_layers_init(struct drm_device *drm, drm 102 drivers/gpu/drm/sun4i/sun4i_lvds.c int sun4i_lvds_init(struct drm_device *drm, struct sun4i_tcon *tcon) drm 109 drivers/gpu/drm/sun4i/sun4i_lvds.c lvds = devm_kzalloc(drm->dev, sizeof(*lvds), GFP_KERNEL); drm 117 drivers/gpu/drm/sun4i/sun4i_lvds.c dev_info(drm->dev, "No panel or bridge found... LVDS output disabled\n"); drm 123 drivers/gpu/drm/sun4i/sun4i_lvds.c ret = drm_encoder_init(drm, drm 129 drivers/gpu/drm/sun4i/sun4i_lvds.c dev_err(drm->dev, "Couldn't initialise the lvds encoder\n"); drm 139 drivers/gpu/drm/sun4i/sun4i_lvds.c ret = drm_connector_init(drm, &lvds->connector, drm 143 drivers/gpu/drm/sun4i/sun4i_lvds.c dev_err(drm->dev, "Couldn't initialise the lvds connector\n"); drm 152 drivers/gpu/drm/sun4i/sun4i_lvds.c dev_err(drm->dev, "Couldn't attach our panel\n"); drm 160 drivers/gpu/drm/sun4i/sun4i_lvds.c dev_err(drm->dev, "Couldn't attach our bridge\n"); drm 10 drivers/gpu/drm/sun4i/sun4i_lvds.h int sun4i_lvds_init(struct drm_device *drm, struct sun4i_tcon *tcon); drm 199 drivers/gpu/drm/sun4i/sun4i_rgb.c int sun4i_rgb_init(struct drm_device *drm, struct sun4i_tcon *tcon) drm 205 drivers/gpu/drm/sun4i/sun4i_rgb.c rgb = devm_kzalloc(drm->dev, sizeof(*rgb), GFP_KERNEL); drm 214 drivers/gpu/drm/sun4i/sun4i_rgb.c dev_info(drm->dev, "No panel or bridge found... RGB output disabled\n"); drm 220 drivers/gpu/drm/sun4i/sun4i_rgb.c ret = drm_encoder_init(drm, drm 226 drivers/gpu/drm/sun4i/sun4i_rgb.c dev_err(drm->dev, "Couldn't initialise the rgb encoder\n"); drm 236 drivers/gpu/drm/sun4i/sun4i_rgb.c ret = drm_connector_init(drm, &rgb->connector, drm 240 drivers/gpu/drm/sun4i/sun4i_rgb.c dev_err(drm->dev, "Couldn't initialise the rgb connector\n"); drm 249 drivers/gpu/drm/sun4i/sun4i_rgb.c dev_err(drm->dev, "Couldn't attach our panel\n"); drm 257 drivers/gpu/drm/sun4i/sun4i_rgb.c dev_err(drm->dev, "Couldn't attach our bridge\n"); drm 12 drivers/gpu/drm/sun4i/sun4i_rgb.h int sun4i_rgb_init(struct drm_device *drm, struct sun4i_tcon *tcon); drm 222 drivers/gpu/drm/sun4i/sun4i_tcon.c static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm) drm 224 drivers/gpu/drm/sun4i/sun4i_tcon.c struct sun4i_drv *drv = drm->dev_private; drm 231 drivers/gpu/drm/sun4i/sun4i_tcon.c dev_warn(drm->dev, drm 718 drivers/gpu/drm/sun4i/sun4i_tcon.c struct drm_device *drm = tcon->drm; drm 731 drivers/gpu/drm/sun4i/sun4i_tcon.c sun4i_tcon_finish_page_flip(drm, scrtc); drm 1086 drivers/gpu/drm/sun4i/sun4i_tcon.c struct drm_device *drm = data; drm 1087 drivers/gpu/drm/sun4i/sun4i_tcon.c struct sun4i_drv *drv = drm->dev_private; drm 1105 drivers/gpu/drm/sun4i/sun4i_tcon.c tcon->drm = drm; drm 1215 drivers/gpu/drm/sun4i/sun4i_tcon.c tcon->crtc = sun4i_crtc_init(drm, engine, tcon); drm 1231 drivers/gpu/drm/sun4i/sun4i_tcon.c ret = sun4i_lvds_init(drm, tcon); drm 1235 drivers/gpu/drm/sun4i/sun4i_tcon.c ret = sun4i_rgb_init(drm, tcon); drm 235 drivers/gpu/drm/sun4i/sun4i_tcon.h struct drm_device *drm; drm 546 drivers/gpu/drm/sun4i/sun4i_tv.c struct drm_device *drm = data; drm 547 drivers/gpu/drm/sun4i/sun4i_tv.c struct sun4i_drv *drv = drm->dev_private; drm 595 drivers/gpu/drm/sun4i/sun4i_tv.c ret = drm_encoder_init(drm, drm 605 drivers/gpu/drm/sun4i/sun4i_tv.c tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, drm 614 drivers/gpu/drm/sun4i/sun4i_tv.c ret = drm_connector_init(drm, &tv->connector, drm 1023 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c struct drm_device *drm = data; drm 1024 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c struct sun4i_drv *drv = drm->dev_private; drm 1035 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c ret = drm_encoder_init(drm, drm 1048 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c ret = drm_connector_init(drm, &dsi->connector, drm 68 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, drm 86 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c crtcs |= drm_of_crtc_port_mask(drm, remote_port); drm 91 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c crtcs = drm_of_find_possible_crtcs(drm, node); drm 129 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c struct drm_device *drm = data; drm 149 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node); drm 223 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs, drm 348 drivers/gpu/drm/sun4i/sun8i_mixer.c static struct drm_plane **sun8i_layers_init(struct drm_device *drm, drm 355 drivers/gpu/drm/sun4i/sun8i_mixer.c planes = devm_kcalloc(drm->dev, drm 364 drivers/gpu/drm/sun4i/sun8i_mixer.c layer = sun8i_vi_layer_init_one(drm, mixer, i); drm 366 drivers/gpu/drm/sun4i/sun8i_mixer.c dev_err(drm->dev, drm 377 drivers/gpu/drm/sun4i/sun8i_mixer.c layer = sun8i_ui_layer_init_one(drm, mixer, i); drm 379 drivers/gpu/drm/sun4i/sun8i_mixer.c dev_err(drm->dev, "Couldn't initialize %s plane\n", drm 426 drivers/gpu/drm/sun4i/sun8i_mixer.c struct drm_device *drm = data; drm 427 drivers/gpu/drm/sun4i/sun8i_mixer.c struct sun4i_drv *drv = drm->dev_private; drm 338 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm, drm 348 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); drm 356 drivers/gpu/drm/sun4i/sun8i_ui_layer.c ret = drm_universal_plane_init(drm, &layer->plane, 0, drm 362 drivers/gpu/drm/sun4i/sun8i_ui_layer.c dev_err(drm->dev, "Couldn't initialize layer\n"); drm 371 drivers/gpu/drm/sun4i/sun8i_ui_layer.c dev_err(drm->dev, "Couldn't add zpos property\n"); drm 59 drivers/gpu/drm/sun4i/sun8i_ui_layer.h struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm, drm 483 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, drm 493 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); drm 506 drivers/gpu/drm/sun4i/sun8i_vi_layer.c ret = drm_universal_plane_init(drm, &layer->plane, 0, drm 511 drivers/gpu/drm/sun4i/sun8i_vi_layer.c dev_err(drm->dev, "Couldn't initialize layer\n"); drm 520 drivers/gpu/drm/sun4i/sun8i_vi_layer.c dev_err(drm->dev, "Couldn't add zpos property\n"); drm 536 drivers/gpu/drm/sun4i/sun8i_vi_layer.c dev_err(drm->dev, "Couldn't add encoding and range properties!\n"); drm 58 drivers/gpu/drm/sun4i/sun8i_vi_layer.h struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, drm 76 drivers/gpu/drm/sun4i/sunxi_engine.h struct drm_plane **(*layers_init)(struct drm_device *drm, drm 149 drivers/gpu/drm/sun4i/sunxi_engine.h sunxi_engine_layers_init(struct drm_device *drm, struct sunxi_engine *engine) drm 152 drivers/gpu/drm/sun4i/sunxi_engine.h return engine->ops->layers_init(drm, engine); drm 740 drivers/gpu/drm/tegra/dc.c static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) drm 754 drivers/gpu/drm/tegra/dc.c return 1 << drm->mode_config.num_crtc; drm 757 drivers/gpu/drm/tegra/dc.c static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, drm 760 drivers/gpu/drm/tegra/dc.c unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); drm 781 drivers/gpu/drm/tegra/dc.c err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, drm 922 drivers/gpu/drm/tegra/dc.c static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, drm 925 drivers/gpu/drm/tegra/dc.c unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); drm 948 drivers/gpu/drm/tegra/dc.c err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, drm 1038 drivers/gpu/drm/tegra/dc.c static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, drm 1043 drivers/gpu/drm/tegra/dc.c unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); drm 1066 drivers/gpu/drm/tegra/dc.c err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, drm 1088 drivers/gpu/drm/tegra/dc.c static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, drm 1101 drivers/gpu/drm/tegra/dc.c plane = tegra_shared_plane_create(drm, dc, drm 1122 drivers/gpu/drm/tegra/dc.c static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, drm 1130 drivers/gpu/drm/tegra/dc.c primary = tegra_primary_plane_create(drm, dc); drm 1140 drivers/gpu/drm/tegra/dc.c planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, drm 1997 drivers/gpu/drm/tegra/dc.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 2000 drivers/gpu/drm/tegra/dc.c struct tegra_drm *tegra = drm->dev_private; drm 2025 drivers/gpu/drm/tegra/dc.c primary = tegra_dc_add_shared_planes(drm, dc); drm 2027 drivers/gpu/drm/tegra/dc.c primary = tegra_dc_add_planes(drm, dc); drm 2035 drivers/gpu/drm/tegra/dc.c cursor = tegra_dc_cursor_plane_create(drm, dc); drm 2042 drivers/gpu/drm/tegra/dc.c cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); drm 2049 drivers/gpu/drm/tegra/dc.c err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, drm 2063 drivers/gpu/drm/tegra/dc.c err = tegra_dc_rgb_init(drm, dc); drm 159 drivers/gpu/drm/tegra/dc.h int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); drm 45 drivers/gpu/drm/tegra/drm.c static int tegra_atomic_check(struct drm_device *drm, drm 50 drivers/gpu/drm/tegra/drm.c err = drm_atomic_helper_check(drm, state); drm 54 drivers/gpu/drm/tegra/drm.c return tegra_display_hub_atomic_check(drm, state); drm 68 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = old_state->dev; drm 69 drivers/gpu/drm/tegra/drm.c struct tegra_drm *tegra = drm->dev_private; drm 72 drivers/gpu/drm/tegra/drm.c drm_atomic_helper_commit_modeset_disables(drm, old_state); drm 73 drivers/gpu/drm/tegra/drm.c tegra_display_hub_atomic_commit(drm, old_state); drm 74 drivers/gpu/drm/tegra/drm.c drm_atomic_helper_commit_planes(drm, old_state, 0); drm 75 drivers/gpu/drm/tegra/drm.c drm_atomic_helper_commit_modeset_enables(drm, old_state); drm 77 drivers/gpu/drm/tegra/drm.c drm_atomic_helper_wait_for_vblanks(drm, old_state); drm 78 drivers/gpu/drm/tegra/drm.c drm_atomic_helper_cleanup_planes(drm, old_state); drm 89 drivers/gpu/drm/tegra/drm.c static int tegra_drm_load(struct drm_device *drm, unsigned long flags) drm 91 drivers/gpu/drm/tegra/drm.c struct host1x_device *device = to_host1x_device(drm->dev); drm 114 drivers/gpu/drm/tegra/drm.c drm->dev_private = tegra; drm 115 drivers/gpu/drm/tegra/drm.c tegra->drm = drm; drm 117 drivers/gpu/drm/tegra/drm.c drm_mode_config_init(drm); drm 119 drivers/gpu/drm/tegra/drm.c drm->mode_config.min_width = 0; drm 120 drivers/gpu/drm/tegra/drm.c drm->mode_config.min_height = 0; drm 122 drivers/gpu/drm/tegra/drm.c drm->mode_config.max_width = 4096; drm 123 drivers/gpu/drm/tegra/drm.c drm->mode_config.max_height = 4096; drm 125 drivers/gpu/drm/tegra/drm.c drm->mode_config.allow_fb_modifiers = true; drm 127 drivers/gpu/drm/tegra/drm.c drm->mode_config.normalize_zpos = true; drm 129 drivers/gpu/drm/tegra/drm.c drm->mode_config.funcs = &tegra_drm_mode_config_funcs; drm 130 drivers/gpu/drm/tegra/drm.c drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; drm 132 drivers/gpu/drm/tegra/drm.c err = tegra_drm_fb_prepare(drm); drm 136 drivers/gpu/drm/tegra/drm.c drm_kms_helper_poll_init(drm); drm 183 drivers/gpu/drm/tegra/drm.c drm->irq_enabled = true; drm 186 drivers/gpu/drm/tegra/drm.c drm->max_vblank_count = 0xffffffff; drm 188 drivers/gpu/drm/tegra/drm.c err = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 192 drivers/gpu/drm/tegra/drm.c drm_mode_config_reset(drm); drm 194 drivers/gpu/drm/tegra/drm.c err = tegra_drm_fb_init(drm); drm 213 drivers/gpu/drm/tegra/drm.c drm_kms_helper_poll_fini(drm); drm 214 drivers/gpu/drm/tegra/drm.c tegra_drm_fb_free(drm); drm 216 drivers/gpu/drm/tegra/drm.c drm_mode_config_cleanup(drm); drm 225 drivers/gpu/drm/tegra/drm.c static void tegra_drm_unload(struct drm_device *drm) drm 227 drivers/gpu/drm/tegra/drm.c struct host1x_device *device = to_host1x_device(drm->dev); drm 228 drivers/gpu/drm/tegra/drm.c struct tegra_drm *tegra = drm->dev_private; drm 231 drivers/gpu/drm/tegra/drm.c drm_kms_helper_poll_fini(drm); drm 232 drivers/gpu/drm/tegra/drm.c tegra_drm_fb_exit(drm); drm 233 drivers/gpu/drm/tegra/drm.c drm_atomic_helper_shutdown(drm); drm 234 drivers/gpu/drm/tegra/drm.c drm_mode_config_cleanup(drm); drm 251 drivers/gpu/drm/tegra/drm.c static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) drm 288 drivers/gpu/drm/tegra/drm.c struct drm_device *drm, drm 326 drivers/gpu/drm/tegra/drm.c struct drm_tegra_submit *args, struct drm_device *drm, drm 336 drivers/gpu/drm/tegra/drm.c struct host1x *host1x = dev_get_drvdata(drm->dev->parent); drm 431 drivers/gpu/drm/tegra/drm.c &user_relocs[num_relocs], drm, drm 506 drivers/gpu/drm/tegra/drm.c static int tegra_gem_create(struct drm_device *drm, void *data, drm 512 drivers/gpu/drm/tegra/drm.c bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, drm 520 drivers/gpu/drm/tegra/drm.c static int tegra_gem_mmap(struct drm_device *drm, void *data, drm 540 drivers/gpu/drm/tegra/drm.c static int tegra_syncpt_read(struct drm_device *drm, void *data, drm 543 drivers/gpu/drm/tegra/drm.c struct host1x *host = dev_get_drvdata(drm->dev->parent); drm 555 drivers/gpu/drm/tegra/drm.c static int tegra_syncpt_incr(struct drm_device *drm, void *data, drm 558 drivers/gpu/drm/tegra/drm.c struct host1x *host1x = dev_get_drvdata(drm->dev->parent); drm 569 drivers/gpu/drm/tegra/drm.c static int tegra_syncpt_wait(struct drm_device *drm, void *data, drm 572 drivers/gpu/drm/tegra/drm.c struct host1x *host1x = dev_get_drvdata(drm->dev->parent); drm 607 drivers/gpu/drm/tegra/drm.c static int tegra_open_channel(struct drm_device *drm, void *data, drm 611 drivers/gpu/drm/tegra/drm.c struct tegra_drm *tegra = drm->dev_private; drm 640 drivers/gpu/drm/tegra/drm.c static int tegra_close_channel(struct drm_device *drm, void *data, drm 664 drivers/gpu/drm/tegra/drm.c static int tegra_get_syncpt(struct drm_device *drm, void *data, drm 694 drivers/gpu/drm/tegra/drm.c static int tegra_submit(struct drm_device *drm, void *data, drm 710 drivers/gpu/drm/tegra/drm.c err = context->client->ops->submit(context, args, drm, file); drm 717 drivers/gpu/drm/tegra/drm.c static int tegra_get_syncpt_base(struct drm_device *drm, void *data, drm 755 drivers/gpu/drm/tegra/drm.c static int tegra_gem_set_tiling(struct drm_device *drm, void *data, drm 808 drivers/gpu/drm/tegra/drm.c static int tegra_gem_get_tiling(struct drm_device *drm, void *data, drm 848 drivers/gpu/drm/tegra/drm.c static int tegra_gem_set_flags(struct drm_device *drm, void *data, drm 873 drivers/gpu/drm/tegra/drm.c static int tegra_gem_get_flags(struct drm_device *drm, void *data, drm 950 drivers/gpu/drm/tegra/drm.c static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) drm 967 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = node->minor->dev; drm 970 drivers/gpu/drm/tegra/drm.c mutex_lock(&drm->mode_config.fb_lock); drm 972 drivers/gpu/drm/tegra/drm.c list_for_each_entry(fb, &drm->mode_config.fb_list, head) { drm 980 drivers/gpu/drm/tegra/drm.c mutex_unlock(&drm->mode_config.fb_lock); drm 988 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = node->minor->dev; drm 989 drivers/gpu/drm/tegra/drm.c struct tegra_drm *tegra = drm->dev_private; drm 1054 drivers/gpu/drm/tegra/drm.c client->drm = tegra; drm 1065 drivers/gpu/drm/tegra/drm.c client->drm = NULL; drm 1074 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 1075 drivers/gpu/drm/tegra/drm.c struct tegra_drm *tegra = drm->dev_private; drm 1112 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 1113 drivers/gpu/drm/tegra/drm.c struct tegra_drm *tegra = drm->dev_private; drm 1205 drivers/gpu/drm/tegra/drm.c struct drm_device *drm; drm 1208 drivers/gpu/drm/tegra/drm.c drm = drm_dev_alloc(driver, &dev->dev); drm 1209 drivers/gpu/drm/tegra/drm.c if (IS_ERR(drm)) drm 1210 drivers/gpu/drm/tegra/drm.c return PTR_ERR(drm); drm 1212 drivers/gpu/drm/tegra/drm.c dev_set_drvdata(&dev->dev, drm); drm 1218 drivers/gpu/drm/tegra/drm.c err = drm_dev_register(drm, 0); drm 1225 drivers/gpu/drm/tegra/drm.c drm_dev_put(drm); drm 1231 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = dev_get_drvdata(&dev->dev); drm 1233 drivers/gpu/drm/tegra/drm.c drm_dev_unregister(drm); drm 1234 drivers/gpu/drm/tegra/drm.c drm_dev_put(drm); drm 1242 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = dev_get_drvdata(dev); drm 1244 drivers/gpu/drm/tegra/drm.c return drm_mode_config_helper_suspend(drm); drm 1249 drivers/gpu/drm/tegra/drm.c struct drm_device *drm = dev_get_drvdata(dev); drm 1251 drivers/gpu/drm/tegra/drm.c return drm_mode_config_helper_resume(drm); drm 36 drivers/gpu/drm/tegra/drm.h struct drm_device *drm; drm 76 drivers/gpu/drm/tegra/drm.h struct drm_tegra_submit *args, struct drm_device *drm, drm 81 drivers/gpu/drm/tegra/drm.h struct drm_tegra_submit *args, struct drm_device *drm, drm 87 drivers/gpu/drm/tegra/drm.h struct tegra_drm *drm; drm 108 drivers/gpu/drm/tegra/drm.h int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); drm 145 drivers/gpu/drm/tegra/drm.h int tegra_output_init(struct drm_device *drm, struct tegra_output *output); drm 148 drivers/gpu/drm/tegra/drm.h struct drm_device *drm); drm 176 drivers/gpu/drm/tegra/drm.h struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, drm 179 drivers/gpu/drm/tegra/drm.h int tegra_drm_fb_prepare(struct drm_device *drm); drm 180 drivers/gpu/drm/tegra/drm.h void tegra_drm_fb_free(struct drm_device *drm); drm 181 drivers/gpu/drm/tegra/drm.h int tegra_drm_fb_init(struct drm_device *drm); drm 182 drivers/gpu/drm/tegra/drm.h void tegra_drm_fb_exit(struct drm_device *drm); drm 203 drivers/gpu/drm/tegra/dsi.c struct drm_device *drm = node->minor->dev; drm 207 drivers/gpu/drm/tegra/dsi.c drm_modeset_lock_all(drm); drm 222 drivers/gpu/drm/tegra/dsi.c drm_modeset_unlock_all(drm); drm 1033 drivers/gpu/drm/tegra/dsi.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 1041 drivers/gpu/drm/tegra/dsi.c drm_connector_init(drm, &dsi->output.connector, drm 1048 drivers/gpu/drm/tegra/dsi.c drm_encoder_init(drm, &dsi->output.encoder, drm 1058 drivers/gpu/drm/tegra/dsi.c err = tegra_output_init(drm, &dsi->output); drm 100 drivers/gpu/drm/tegra/fb.c static struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, drm 113 drivers/gpu/drm/tegra/fb.c drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd); drm 118 drivers/gpu/drm/tegra/fb.c err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs); drm 120 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to initialize framebuffer: %d\n", drm 129 drivers/gpu/drm/tegra/fb.c struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, drm 133 drivers/gpu/drm/tegra/fb.c const struct drm_format_info *info = drm_get_format_info(drm, cmd); drm 164 drivers/gpu/drm/tegra/fb.c fb = tegra_fb_alloc(drm, cmd, planes, i); drm 209 drivers/gpu/drm/tegra/fb.c struct drm_device *drm = helper->dev; drm 231 drivers/gpu/drm/tegra/fb.c bo = tegra_bo_create(drm, size, 0); drm 237 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to allocate framebuffer info\n"); drm 242 drivers/gpu/drm/tegra/fb.c fbdev->fb = tegra_fb_alloc(drm, &cmd, &bo, 1); drm 245 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n", drm 266 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to vmap() framebuffer\n"); drm 272 drivers/gpu/drm/tegra/fb.c drm->mode_config.fb_base = (resource_size_t)bo->paddr; drm 289 drivers/gpu/drm/tegra/fb.c static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm) drm 295 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to allocate DRM fbdev\n"); drm 299 drivers/gpu/drm/tegra/fb.c drm_fb_helper_prepare(drm, &fbdev->base, &tegra_fb_helper_funcs); drm 314 drivers/gpu/drm/tegra/fb.c struct drm_device *drm = fbdev->base.dev; drm 317 drivers/gpu/drm/tegra/fb.c err = drm_fb_helper_init(drm, &fbdev->base, max_connectors); drm 319 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to initialize DRM FB helper: %d\n", drm 326 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to add connectors: %d\n", err); drm 332 drivers/gpu/drm/tegra/fb.c dev_err(drm->dev, "failed to set initial configuration: %d\n", drm 365 drivers/gpu/drm/tegra/fb.c int tegra_drm_fb_prepare(struct drm_device *drm) drm 368 drivers/gpu/drm/tegra/fb.c struct tegra_drm *tegra = drm->dev_private; drm 370 drivers/gpu/drm/tegra/fb.c tegra->fbdev = tegra_fbdev_create(drm); drm 378 drivers/gpu/drm/tegra/fb.c void tegra_drm_fb_free(struct drm_device *drm) drm 381 drivers/gpu/drm/tegra/fb.c struct tegra_drm *tegra = drm->dev_private; drm 387 drivers/gpu/drm/tegra/fb.c int tegra_drm_fb_init(struct drm_device *drm) drm 390 drivers/gpu/drm/tegra/fb.c struct tegra_drm *tegra = drm->dev_private; drm 393 drivers/gpu/drm/tegra/fb.c err = tegra_fbdev_init(tegra->fbdev, 32, drm->mode_config.num_crtc, drm 394 drivers/gpu/drm/tegra/fb.c drm->mode_config.num_connector); drm 402 drivers/gpu/drm/tegra/fb.c void tegra_drm_fb_exit(struct drm_device *drm) drm 405 drivers/gpu/drm/tegra/fb.c struct tegra_drm *tegra = drm->dev_private; drm 131 drivers/gpu/drm/tegra/gem.c dev_err(tegra->drm->dev, "out of I/O virtual memory: %d\n", drm 141 drivers/gpu/drm/tegra/gem.c dev_err(tegra->drm->dev, "failed to map buffer\n"); drm 173 drivers/gpu/drm/tegra/gem.c static struct tegra_bo *tegra_bo_alloc_object(struct drm_device *drm, drm 186 drivers/gpu/drm/tegra/gem.c err = drm_gem_object_init(drm, &bo->gem, size); drm 203 drivers/gpu/drm/tegra/gem.c static void tegra_bo_free(struct drm_device *drm, struct tegra_bo *bo) drm 206 drivers/gpu/drm/tegra/gem.c dma_unmap_sg(drm->dev, bo->sgt->sgl, bo->sgt->nents, drm 212 drivers/gpu/drm/tegra/gem.c dma_free_wc(drm->dev, bo->gem.size, bo->vaddr, bo->paddr); drm 216 drivers/gpu/drm/tegra/gem.c static int tegra_bo_get_pages(struct drm_device *drm, struct tegra_bo *bo) drm 232 drivers/gpu/drm/tegra/gem.c err = dma_map_sg(drm->dev, bo->sgt->sgl, bo->sgt->nents, drm 249 drivers/gpu/drm/tegra/gem.c static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo) drm 251 drivers/gpu/drm/tegra/gem.c struct tegra_drm *tegra = drm->dev_private; drm 255 drivers/gpu/drm/tegra/gem.c err = tegra_bo_get_pages(drm, bo); drm 261 drivers/gpu/drm/tegra/gem.c tegra_bo_free(drm, bo); drm 267 drivers/gpu/drm/tegra/gem.c bo->vaddr = dma_alloc_wc(drm->dev, size, &bo->paddr, drm 270 drivers/gpu/drm/tegra/gem.c dev_err(drm->dev, drm 280 drivers/gpu/drm/tegra/gem.c struct tegra_bo *tegra_bo_create(struct drm_device *drm, size_t size, drm 286 drivers/gpu/drm/tegra/gem.c bo = tegra_bo_alloc_object(drm, size); drm 290 drivers/gpu/drm/tegra/gem.c err = tegra_bo_alloc(drm, bo); drm 309 drivers/gpu/drm/tegra/gem.c struct drm_device *drm, drm 317 drivers/gpu/drm/tegra/gem.c bo = tegra_bo_create(drm, size, flags); drm 332 drivers/gpu/drm/tegra/gem.c static struct tegra_bo *tegra_bo_import(struct drm_device *drm, drm 335 drivers/gpu/drm/tegra/gem.c struct tegra_drm *tegra = drm->dev_private; drm 340 drivers/gpu/drm/tegra/gem.c bo = tegra_bo_alloc_object(drm, buf->size); drm 344 drivers/gpu/drm/tegra/gem.c attach = dma_buf_attach(buf, drm->dev); drm 407 drivers/gpu/drm/tegra/gem.c int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm, drm 411 drivers/gpu/drm/tegra/gem.c struct tegra_drm *tegra = drm->dev_private; drm 417 drivers/gpu/drm/tegra/gem.c bo = tegra_bo_create_with_handle(file, drm, args->size, 0, drm 562 drivers/gpu/drm/tegra/gem.c struct drm_device *drm = gem->dev; drm 565 drivers/gpu/drm/tegra/gem.c dma_sync_sg_for_cpu(drm->dev, bo->sgt->sgl, bo->sgt->nents, drm 576 drivers/gpu/drm/tegra/gem.c struct drm_device *drm = gem->dev; drm 579 drivers/gpu/drm/tegra/gem.c dma_sync_sg_for_device(drm->dev, bo->sgt->sgl, bo->sgt->nents, drm 647 drivers/gpu/drm/tegra/gem.c struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm, drm 655 drivers/gpu/drm/tegra/gem.c if (gem->dev == drm) { drm 661 drivers/gpu/drm/tegra/gem.c bo = tegra_bo_import(drm, buf); drm 56 drivers/gpu/drm/tegra/gem.h struct tegra_bo *tegra_bo_create(struct drm_device *drm, size_t size, drm 59 drivers/gpu/drm/tegra/gem.h struct drm_device *drm, drm 64 drivers/gpu/drm/tegra/gem.h int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm, drm 74 drivers/gpu/drm/tegra/gem.h struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm, drm 37 drivers/gpu/drm/tegra/gr2d.c struct tegra_drm_client *drm = host1x_to_drm_client(client); drm 40 drivers/gpu/drm/tegra/gr2d.c struct gr2d *gr2d = to_gr2d(drm); drm 61 drivers/gpu/drm/tegra/gr2d.c err = tegra_drm_register_client(dev->dev_private, drm); drm 80 drivers/gpu/drm/tegra/gr2d.c struct tegra_drm_client *drm = host1x_to_drm_client(client); drm 83 drivers/gpu/drm/tegra/gr2d.c struct gr2d *gr2d = to_gr2d(drm); drm 86 drivers/gpu/drm/tegra/gr2d.c err = tegra_drm_unregister_client(tegra, drm); drm 46 drivers/gpu/drm/tegra/gr3d.c struct tegra_drm_client *drm = host1x_to_drm_client(client); drm 49 drivers/gpu/drm/tegra/gr3d.c struct gr3d *gr3d = to_gr3d(drm); drm 70 drivers/gpu/drm/tegra/gr3d.c err = tegra_drm_register_client(dev->dev_private, drm); drm 89 drivers/gpu/drm/tegra/gr3d.c struct tegra_drm_client *drm = host1x_to_drm_client(client); drm 91 drivers/gpu/drm/tegra/gr3d.c struct gr3d *gr3d = to_gr3d(drm); drm 94 drivers/gpu/drm/tegra/gr3d.c err = tegra_drm_unregister_client(dev->dev_private, drm); drm 1033 drivers/gpu/drm/tegra/hdmi.c struct drm_device *drm = node->minor->dev; drm 1037 drivers/gpu/drm/tegra/hdmi.c drm_modeset_lock_all(drm); drm 1052 drivers/gpu/drm/tegra/hdmi.c drm_modeset_unlock_all(drm); drm 1427 drivers/gpu/drm/tegra/hdmi.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 1433 drivers/gpu/drm/tegra/hdmi.c drm_connector_init(drm, &hdmi->output.connector, drm 1440 drivers/gpu/drm/tegra/hdmi.c drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs, drm 1449 drivers/gpu/drm/tegra/hdmi.c err = tegra_output_init(drm, &hdmi->output); drm 529 drivers/gpu/drm/tegra/hub.c struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, drm 535 drivers/gpu/drm/tegra/hub.c struct tegra_drm *tegra = drm->dev_private; drm 562 drivers/gpu/drm/tegra/hub.c err = drm_universal_plane_init(drm, p, possible_crtcs, drm 608 drivers/gpu/drm/tegra/hub.c struct drm_device *drm = dev_get_drvdata(hub->client.parent); drm 611 drivers/gpu/drm/tegra/hub.c WARN_ON(!drm_modeset_is_locked(&drm->mode_config.connection_mutex)); drm 620 drivers/gpu/drm/tegra/hub.c int tegra_display_hub_atomic_check(struct drm_device *drm, drm 623 drivers/gpu/drm/tegra/hub.c struct tegra_drm *tegra = drm->dev_private; drm 681 drivers/gpu/drm/tegra/hub.c void tegra_display_hub_atomic_commit(struct drm_device *drm, drm 684 drivers/gpu/drm/tegra/hub.c struct tegra_drm *tegra = drm->dev_private; drm 711 drivers/gpu/drm/tegra/hub.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 712 drivers/gpu/drm/tegra/hub.c struct tegra_drm *tegra = drm->dev_private; drm 719 drivers/gpu/drm/tegra/hub.c drm_atomic_private_obj_init(drm, &hub->base, &state->base, drm 729 drivers/gpu/drm/tegra/hub.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 730 drivers/gpu/drm/tegra/hub.c struct tegra_drm *tegra = drm->dev_private; drm 81 drivers/gpu/drm/tegra/hub.h struct drm_plane *tegra_shared_plane_create(struct drm_device *drm, drm 86 drivers/gpu/drm/tegra/hub.h int tegra_display_hub_atomic_check(struct drm_device *drm, drm 88 drivers/gpu/drm/tegra/hub.h void tegra_display_hub_atomic_commit(struct drm_device *drm, drm 185 drivers/gpu/drm/tegra/output.c int tegra_output_init(struct drm_device *drm, struct tegra_output *output) drm 219 drivers/gpu/drm/tegra/output.c struct drm_device *drm) drm 225 drivers/gpu/drm/tegra/output.c drm_for_each_crtc(crtc, drm) { drm 270 drivers/gpu/drm/tegra/rgb.c int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) drm 278 drivers/gpu/drm/tegra/rgb.c drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs, drm 284 drivers/gpu/drm/tegra/rgb.c drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs, drm 293 drivers/gpu/drm/tegra/rgb.c err = tegra_output_init(drm, output); drm 1268 drivers/gpu/drm/tegra/sor.c struct drm_device *drm = node->minor->dev; drm 1272 drivers/gpu/drm/tegra/sor.c drm_modeset_lock_all(drm); drm 1301 drivers/gpu/drm/tegra/sor.c drm_modeset_unlock_all(drm); drm 1430 drivers/gpu/drm/tegra/sor.c struct drm_device *drm = node->minor->dev; drm 1434 drivers/gpu/drm/tegra/sor.c drm_modeset_lock_all(drm); drm 1449 drivers/gpu/drm/tegra/sor.c drm_modeset_unlock_all(drm); drm 2808 drivers/gpu/drm/tegra/sor.c struct drm_device *drm = dev_get_drvdata(client->parent); drm 2838 drivers/gpu/drm/tegra/sor.c drm_connector_init(drm, &sor->output.connector, drm 2845 drivers/gpu/drm/tegra/sor.c drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, drm 2853 drivers/gpu/drm/tegra/sor.c err = tegra_output_init(drm, &sor->output); drm 2859 drivers/gpu/drm/tegra/sor.c tegra_output_find_possible_crtcs(&sor->output, drm); drm 66 drivers/gpu/drm/tegra/trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/tegra drm 183 drivers/gpu/drm/tegra/vic.c struct tegra_drm_client *drm = host1x_to_drm_client(client); drm 187 drivers/gpu/drm/tegra/vic.c struct vic *vic = to_vic(drm); drm 213 drivers/gpu/drm/tegra/vic.c err = tegra_drm_register_client(tegra, drm); drm 232 drivers/gpu/drm/tegra/vic.c struct tegra_drm_client *drm = host1x_to_drm_client(client); drm 236 drivers/gpu/drm/tegra/vic.c struct vic *vic = to_vic(drm); drm 239 drivers/gpu/drm/tegra/vic.c err = tegra_drm_unregister_client(tegra, drm); drm 266 drivers/gpu/drm/tegra/vic.c vic->falcon.data = vic->client.drm; drm 224 drivers/gpu/drm/tiny/hx8357d.c struct drm_device *drm; drm 233 drivers/gpu/drm/tiny/hx8357d.c drm = &dbidev->drm; drm 234 drivers/gpu/drm/tiny/hx8357d.c ret = devm_drm_dev_init(dev, drm, &hx8357d_driver); drm 240 drivers/gpu/drm/tiny/hx8357d.c drm_mode_config_init(drm); drm 262 drivers/gpu/drm/tiny/hx8357d.c drm_mode_config_reset(drm); drm 264 drivers/gpu/drm/tiny/hx8357d.c ret = drm_dev_register(drm, 0); drm 268 drivers/gpu/drm/tiny/hx8357d.c spi_set_drvdata(spi, drm); drm 270 drivers/gpu/drm/tiny/hx8357d.c drm_fbdev_generic_setup(drm, 0); drm 277 drivers/gpu/drm/tiny/hx8357d.c struct drm_device *drm = spi_get_drvdata(spi); drm 279 drivers/gpu/drm/tiny/hx8357d.c drm_dev_unplug(drm); drm 280 drivers/gpu/drm/tiny/hx8357d.c drm_atomic_helper_shutdown(drm); drm 382 drivers/gpu/drm/tiny/ili9225.c struct drm_device *drm; drm 393 drivers/gpu/drm/tiny/ili9225.c drm = &dbidev->drm; drm 394 drivers/gpu/drm/tiny/ili9225.c ret = devm_drm_dev_init(dev, drm, &ili9225_driver); drm 400 drivers/gpu/drm/tiny/ili9225.c drm_mode_config_init(drm); drm 427 drivers/gpu/drm/tiny/ili9225.c drm_mode_config_reset(drm); drm 429 drivers/gpu/drm/tiny/ili9225.c ret = drm_dev_register(drm, 0); drm 433 drivers/gpu/drm/tiny/ili9225.c spi_set_drvdata(spi, drm); drm 435 drivers/gpu/drm/tiny/ili9225.c drm_fbdev_generic_setup(drm, 0); drm 442 drivers/gpu/drm/tiny/ili9225.c struct drm_device *drm = spi_get_drvdata(spi); drm 444 drivers/gpu/drm/tiny/ili9225.c drm_dev_unplug(drm); drm 445 drivers/gpu/drm/tiny/ili9225.c drm_atomic_helper_shutdown(drm); drm 180 drivers/gpu/drm/tiny/ili9341.c struct drm_device *drm; drm 191 drivers/gpu/drm/tiny/ili9341.c drm = &dbidev->drm; drm 192 drivers/gpu/drm/tiny/ili9341.c ret = devm_drm_dev_init(dev, drm, &ili9341_driver); drm 198 drivers/gpu/drm/tiny/ili9341.c drm_mode_config_init(drm); drm 226 drivers/gpu/drm/tiny/ili9341.c drm_mode_config_reset(drm); drm 228 drivers/gpu/drm/tiny/ili9341.c ret = drm_dev_register(drm, 0); drm 232 drivers/gpu/drm/tiny/ili9341.c spi_set_drvdata(spi, drm); drm 234 drivers/gpu/drm/tiny/ili9341.c drm_fbdev_generic_setup(drm, 0); drm 241 drivers/gpu/drm/tiny/ili9341.c struct drm_device *drm = spi_get_drvdata(spi); drm 243 drivers/gpu/drm/tiny/ili9341.c drm_dev_unplug(drm); drm 244 drivers/gpu/drm/tiny/ili9341.c drm_atomic_helper_shutdown(drm); drm 184 drivers/gpu/drm/tiny/mi0283qt.c struct drm_device *drm; drm 195 drivers/gpu/drm/tiny/mi0283qt.c drm = &dbidev->drm; drm 196 drivers/gpu/drm/tiny/mi0283qt.c ret = devm_drm_dev_init(dev, drm, &mi0283qt_driver); drm 202 drivers/gpu/drm/tiny/mi0283qt.c drm_mode_config_init(drm); drm 234 drivers/gpu/drm/tiny/mi0283qt.c drm_mode_config_reset(drm); drm 236 drivers/gpu/drm/tiny/mi0283qt.c ret = drm_dev_register(drm, 0); drm 240 drivers/gpu/drm/tiny/mi0283qt.c spi_set_drvdata(spi, drm); drm 242 drivers/gpu/drm/tiny/mi0283qt.c drm_fbdev_generic_setup(drm, 0); drm 249 drivers/gpu/drm/tiny/mi0283qt.c struct drm_device *drm = spi_get_drvdata(spi); drm 251 drivers/gpu/drm/tiny/mi0283qt.c drm_dev_unplug(drm); drm 252 drivers/gpu/drm/tiny/mi0283qt.c drm_atomic_helper_shutdown(drm); drm 63 drivers/gpu/drm/tiny/repaper.c struct drm_device drm; drm 95 drivers/gpu/drm/tiny/repaper.c static inline struct repaper_epd *drm_to_epd(struct drm_device *drm) drm 97 drivers/gpu/drm/tiny/repaper.c return container_of(drm, struct repaper_epd, drm); drm 919 drivers/gpu/drm/tiny/repaper.c static void repaper_release(struct drm_device *drm) drm 921 drivers/gpu/drm/tiny/repaper.c struct repaper_epd *epd = drm_to_epd(drm); drm 925 drivers/gpu/drm/tiny/repaper.c drm_mode_config_cleanup(drm); drm 926 drivers/gpu/drm/tiny/repaper.c drm_dev_fini(drm); drm 1004 drivers/gpu/drm/tiny/repaper.c struct drm_device *drm; drm 1028 drivers/gpu/drm/tiny/repaper.c drm = &epd->drm; drm 1030 drivers/gpu/drm/tiny/repaper.c ret = devm_drm_dev_init(dev, drm, &repaper_driver); drm 1036 drivers/gpu/drm/tiny/repaper.c drm_mode_config_init(drm); drm 1037 drivers/gpu/drm/tiny/repaper.c drm->mode_config.funcs = &repaper_mode_config_funcs; drm 1150 drivers/gpu/drm/tiny/repaper.c drm->mode_config.min_width = mode->hdisplay; drm 1151 drivers/gpu/drm/tiny/repaper.c drm->mode_config.max_width = mode->hdisplay; drm 1152 drivers/gpu/drm/tiny/repaper.c drm->mode_config.min_height = mode->vdisplay; drm 1153 drivers/gpu/drm/tiny/repaper.c drm->mode_config.max_height = mode->vdisplay; drm 1156 drivers/gpu/drm/tiny/repaper.c ret = drm_connector_init(drm, &epd->connector, &repaper_connector_funcs, drm 1161 drivers/gpu/drm/tiny/repaper.c ret = drm_simple_display_pipe_init(drm, &epd->pipe, &repaper_pipe_funcs, drm 1167 drivers/gpu/drm/tiny/repaper.c drm_mode_config_reset(drm); drm 1169 drivers/gpu/drm/tiny/repaper.c ret = drm_dev_register(drm, 0); drm 1173 drivers/gpu/drm/tiny/repaper.c spi_set_drvdata(spi, drm); drm 1177 drivers/gpu/drm/tiny/repaper.c drm_fbdev_generic_setup(drm, 0); drm 1184 drivers/gpu/drm/tiny/repaper.c struct drm_device *drm = spi_get_drvdata(spi); drm 1186 drivers/gpu/drm/tiny/repaper.c drm_dev_unplug(drm); drm 1187 drivers/gpu/drm/tiny/repaper.c drm_atomic_helper_shutdown(drm); drm 322 drivers/gpu/drm/tiny/st7586.c struct drm_device *drm; drm 334 drivers/gpu/drm/tiny/st7586.c drm = &dbidev->drm; drm 335 drivers/gpu/drm/tiny/st7586.c ret = devm_drm_dev_init(dev, drm, &st7586_driver); drm 341 drivers/gpu/drm/tiny/st7586.c drm_mode_config_init(drm); drm 381 drivers/gpu/drm/tiny/st7586.c drm_mode_config_reset(drm); drm 383 drivers/gpu/drm/tiny/st7586.c ret = drm_dev_register(drm, 0); drm 387 drivers/gpu/drm/tiny/st7586.c spi_set_drvdata(spi, drm); drm 389 drivers/gpu/drm/tiny/st7586.c drm_fbdev_generic_setup(drm, 0); drm 396 drivers/gpu/drm/tiny/st7586.c struct drm_device *drm = spi_get_drvdata(spi); drm 398 drivers/gpu/drm/tiny/st7586.c drm_dev_unplug(drm); drm 399 drivers/gpu/drm/tiny/st7586.c drm_atomic_helper_shutdown(drm); drm 154 drivers/gpu/drm/tiny/st7735r.c struct drm_device *drm; drm 165 drivers/gpu/drm/tiny/st7735r.c drm = &dbidev->drm; drm 166 drivers/gpu/drm/tiny/st7735r.c ret = devm_drm_dev_init(dev, drm, &st7735r_driver); drm 172 drivers/gpu/drm/tiny/st7735r.c drm_mode_config_init(drm); drm 203 drivers/gpu/drm/tiny/st7735r.c drm_mode_config_reset(drm); drm 205 drivers/gpu/drm/tiny/st7735r.c ret = drm_dev_register(drm, 0); drm 209 drivers/gpu/drm/tiny/st7735r.c spi_set_drvdata(spi, drm); drm 211 drivers/gpu/drm/tiny/st7735r.c drm_fbdev_generic_setup(drm, 0); drm 218 drivers/gpu/drm/tiny/st7735r.c struct drm_device *drm = spi_get_drvdata(spi); drm 220 drivers/gpu/drm/tiny/st7735r.c drm_dev_unplug(drm); drm 221 drivers/gpu/drm/tiny/st7735r.c drm_atomic_helper_shutdown(drm); drm 62 drivers/gpu/drm/tve200/tve200_display.c dev_err(priv->drm->dev, "stray IRQ %08x\n", stat); drm 126 drivers/gpu/drm/tve200/tve200_display.c struct drm_device *drm = crtc->dev; drm 127 drivers/gpu/drm/tve200/tve200_display.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 157 drivers/gpu/drm/tve200/tve200_display.c dev_info(drm->dev, "CIF mode\n"); drm 160 drivers/gpu/drm/tve200/tve200_display.c dev_info(drm->dev, "VGA mode\n"); drm 164 drivers/gpu/drm/tve200/tve200_display.c dev_info(drm->dev, "D1 mode\n"); drm 212 drivers/gpu/drm/tve200/tve200_display.c dev_err(drm->dev, "Unknown FB format 0x%08x\n", drm 228 drivers/gpu/drm/tve200/tve200_display.c struct drm_device *drm = crtc->dev; drm 229 drivers/gpu/drm/tve200/tve200_display.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 243 drivers/gpu/drm/tve200/tve200_display.c struct drm_device *drm = crtc->dev; drm 244 drivers/gpu/drm/tve200/tve200_display.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 279 drivers/gpu/drm/tve200/tve200_display.c struct drm_device *drm = crtc->dev; drm 280 drivers/gpu/drm/tve200/tve200_display.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 289 drivers/gpu/drm/tve200/tve200_display.c struct drm_device *drm = crtc->dev; drm 290 drivers/gpu/drm/tve200/tve200_display.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 305 drivers/gpu/drm/tve200/tve200_display.c int tve200_display_init(struct drm_device *drm) drm 307 drivers/gpu/drm/tve200/tve200_display.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 329 drivers/gpu/drm/tve200/tve200_display.c ret = drm_simple_display_pipe_init(drm, &priv->pipe, drm 105 drivers/gpu/drm/tve200/tve200_drm.h struct drm_device *drm; drm 167 drivers/gpu/drm/tve200/tve200_drv.c struct drm_device *drm; drm 176 drivers/gpu/drm/tve200/tve200_drv.c drm = drm_dev_alloc(&tve200_drm_driver, dev); drm 177 drivers/gpu/drm/tve200/tve200_drv.c if (IS_ERR(drm)) drm 178 drivers/gpu/drm/tve200/tve200_drv.c return PTR_ERR(drm); drm 179 drivers/gpu/drm/tve200/tve200_drv.c platform_set_drvdata(pdev, drm); drm 180 drivers/gpu/drm/tve200/tve200_drv.c priv->drm = drm; drm 181 drivers/gpu/drm/tve200/tve200_drv.c drm->dev_private = priv; drm 227 drivers/gpu/drm/tve200/tve200_drv.c ret = tve200_modeset_init(drm); drm 231 drivers/gpu/drm/tve200/tve200_drv.c ret = drm_dev_register(drm, 0); drm 239 drivers/gpu/drm/tve200/tve200_drv.c drm_fbdev_generic_setup(drm, 16); drm 246 drivers/gpu/drm/tve200/tve200_drv.c drm_dev_put(drm); drm 252 drivers/gpu/drm/tve200/tve200_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 253 drivers/gpu/drm/tve200/tve200_drv.c struct tve200_drm_dev_private *priv = drm->dev_private; drm 255 drivers/gpu/drm/tve200/tve200_drv.c drm_dev_unregister(drm); drm 258 drivers/gpu/drm/tve200/tve200_drv.c drm_mode_config_cleanup(drm); drm 260 drivers/gpu/drm/tve200/tve200_drv.c drm_dev_put(drm); drm 96 drivers/gpu/drm/udl/udl_drv.c r = drm_dev_init(&udl->drm, &driver, &interface->dev); drm 103 drivers/gpu/drm/udl/udl_drv.c udl->drm.dev_private = udl; drm 107 drivers/gpu/drm/udl/udl_drv.c drm_dev_fini(&udl->drm); drm 126 drivers/gpu/drm/udl/udl_drv.c r = drm_dev_register(&udl->drm, 0); drm 130 drivers/gpu/drm/udl/udl_drv.c DRM_INFO("Initialized udl on minor %d\n", udl->drm.primary->index); drm 135 drivers/gpu/drm/udl/udl_drv.c drm_dev_put(&udl->drm); drm 56 drivers/gpu/drm/udl/udl_drv.h struct drm_device drm; drm 77 drivers/gpu/drm/udl/udl_drv.h #define to_udl(x) container_of(x, struct udl_device, drm) drm 212 drivers/gpu/drm/udl/udl_fb.c if (drm_dev_is_unplugged(&udl->drm)) drm 315 drivers/gpu/drm/udl/udl_main.c struct drm_device *dev = &udl->drm; drm 43 drivers/gpu/drm/v3d/v3d_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 44 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(drm); drm 55 drivers/gpu/drm/v3d/v3d_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 56 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(drm); drm 241 drivers/gpu/drm/v3d/v3d_drv.c struct drm_device *drm; drm 253 drivers/gpu/drm/v3d/v3d_drv.c drm = &v3d->drm; drm 308 drivers/gpu/drm/v3d/v3d_drv.c ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev); drm 312 drivers/gpu/drm/v3d/v3d_drv.c platform_set_drvdata(pdev, drm); drm 313 drivers/gpu/drm/v3d/v3d_drv.c drm->dev_private = v3d; drm 315 drivers/gpu/drm/v3d/v3d_drv.c ret = v3d_gem_init(drm); drm 323 drivers/gpu/drm/v3d/v3d_drv.c ret = drm_dev_register(drm, 0); drm 332 drivers/gpu/drm/v3d/v3d_drv.c v3d_gem_destroy(drm); drm 334 drivers/gpu/drm/v3d/v3d_drv.c drm_dev_put(drm); drm 344 drivers/gpu/drm/v3d/v3d_drv.c struct drm_device *drm = platform_get_drvdata(pdev); drm 345 drivers/gpu/drm/v3d/v3d_drv.c struct v3d_dev *v3d = to_v3d_dev(drm); drm 347 drivers/gpu/drm/v3d/v3d_drv.c drm_dev_unregister(drm); drm 349 drivers/gpu/drm/v3d/v3d_drv.c v3d_gem_destroy(drm); drm 351 drivers/gpu/drm/v3d/v3d_drv.c drm_dev_put(drm); drm 42 drivers/gpu/drm/v3d/v3d_drv.h struct drm_device drm; drm 14 drivers/gpu/drm/v3d/v3d_fence.c fence->dev = &v3d->drm; drm 112 drivers/gpu/drm/v3d/v3d_gem.c struct drm_device *dev = &v3d->drm; drm 191 drivers/gpu/drm/v3d/v3d_gem.c struct drm_device *dev = &v3d->drm; drm 536 drivers/gpu/drm/v3d/v3d_gem.c trace_v3d_submit_cl_ioctl(&v3d->drm, args->rcl_start, args->rcl_end); drm 651 drivers/gpu/drm/v3d/v3d_gem.c trace_v3d_submit_tfu_ioctl(&v3d->drm, args->iia); drm 747 drivers/gpu/drm/v3d/v3d_gem.c trace_v3d_submit_csd_ioctl(&v3d->drm, args->cfg[5], args->cfg[6]); drm 41 drivers/gpu/drm/v3d/v3d_irq.c struct drm_device *dev = &v3d->drm; drm 104 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_bcl_irq(&v3d->drm, fence->seqno); drm 113 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_rcl_irq(&v3d->drm, fence->seqno); drm 122 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_csd_irq(&v3d->drm, fence->seqno); drm 158 drivers/gpu/drm/v3d/v3d_irq.c trace_v3d_tfu_irq(&v3d->drm, fence->seqno); drm 92 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; drm 145 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; drm 188 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; drm 225 drivers/gpu/drm/v3d/v3d_sched.c struct drm_device *dev = &v3d->drm; drm 1078 drivers/gpu/drm/vc4/vc4_crtc.c static void vc4_set_crtc_possible_masks(struct drm_device *drm, drm 1086 drivers/gpu/drm/vc4/vc4_crtc.c drm_for_each_encoder(encoder, drm) { drm 1111 drivers/gpu/drm/vc4/vc4_crtc.c struct drm_device *drm = vc4_crtc->base.dev; drm 1112 drivers/gpu/drm/vc4/vc4_crtc.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 1127 drivers/gpu/drm/vc4/vc4_crtc.c struct drm_device *drm = dev_get_drvdata(master); drm 1159 drivers/gpu/drm/vc4/vc4_crtc.c primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); drm 1166 drivers/gpu/drm/vc4/vc4_crtc.c drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, drm 1189 drivers/gpu/drm/vc4/vc4_crtc.c vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY); drm 1201 drivers/gpu/drm/vc4/vc4_crtc.c cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); drm 1216 drivers/gpu/drm/vc4/vc4_crtc.c vc4_set_crtc_possible_masks(drm, crtc); drm 1226 drivers/gpu/drm/vc4/vc4_crtc.c vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name, drm 1233 drivers/gpu/drm/vc4/vc4_crtc.c &drm->mode_config.plane_list, head) { drm 83 drivers/gpu/drm/vc4/vc4_debugfs.c void vc4_debugfs_add_regset32(struct drm_device *drm, drm 87 drivers/gpu/drm/vc4/vc4_debugfs.c vc4_debugfs_add_file(drm, name, vc4_debugfs_regset32, regset); drm 260 drivers/gpu/drm/vc4/vc4_dpi.c struct drm_device *drm = dev_get_drvdata(master); drm 261 drivers/gpu/drm/vc4/vc4_dpi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 311 drivers/gpu/drm/vc4/vc4_dpi.c drm_encoder_init(drm, dpi->encoder, &vc4_dpi_encoder_funcs, drm 323 drivers/gpu/drm/vc4/vc4_dpi.c vc4_debugfs_add_regset32(drm, "dpi_regs", &dpi->regset); drm 336 drivers/gpu/drm/vc4/vc4_dpi.c struct drm_device *drm = dev_get_drvdata(master); drm 337 drivers/gpu/drm/vc4/vc4_dpi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 255 drivers/gpu/drm/vc4/vc4_drv.c struct drm_device *drm; drm 272 drivers/gpu/drm/vc4/vc4_drv.c drm = drm_dev_alloc(&vc4_drm_driver, dev); drm 273 drivers/gpu/drm/vc4/vc4_drv.c if (IS_ERR(drm)) drm 274 drivers/gpu/drm/vc4/vc4_drv.c return PTR_ERR(drm); drm 275 drivers/gpu/drm/vc4/vc4_drv.c platform_set_drvdata(pdev, drm); drm 276 drivers/gpu/drm/vc4/vc4_drv.c vc4->dev = drm; drm 277 drivers/gpu/drm/vc4/vc4_drv.c drm->dev_private = vc4; drm 282 drivers/gpu/drm/vc4/vc4_drv.c ret = vc4_bo_cache_init(drm); drm 286 drivers/gpu/drm/vc4/vc4_drv.c drm_mode_config_init(drm); drm 288 drivers/gpu/drm/vc4/vc4_drv.c vc4_gem_init(drm); drm 290 drivers/gpu/drm/vc4/vc4_drv.c ret = component_bind_all(dev, drm); drm 296 drivers/gpu/drm/vc4/vc4_drv.c ret = vc4_kms_load(drm); drm 300 drivers/gpu/drm/vc4/vc4_drv.c ret = drm_dev_register(drm, 0); drm 304 drivers/gpu/drm/vc4/vc4_drv.c drm_fbdev_generic_setup(drm, 16); drm 309 drivers/gpu/drm/vc4/vc4_drv.c component_unbind_all(dev, drm); drm 311 drivers/gpu/drm/vc4/vc4_drv.c vc4_gem_destroy(drm); drm 312 drivers/gpu/drm/vc4/vc4_drv.c vc4_bo_cache_destroy(drm); drm 314 drivers/gpu/drm/vc4/vc4_drv.c drm_dev_put(drm); drm 320 drivers/gpu/drm/vc4/vc4_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 321 drivers/gpu/drm/vc4/vc4_drv.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 323 drivers/gpu/drm/vc4/vc4_drv.c drm_dev_unregister(drm); drm 325 drivers/gpu/drm/vc4/vc4_drv.c drm_atomic_helper_shutdown(drm); drm 327 drivers/gpu/drm/vc4/vc4_drv.c drm_mode_config_cleanup(drm); drm 332 drivers/gpu/drm/vc4/vc4_drv.c drm_dev_put(drm); drm 759 drivers/gpu/drm/vc4/vc4_drv.h void vc4_debugfs_add_file(struct drm_device *drm, drm 763 drivers/gpu/drm/vc4/vc4_drv.h void vc4_debugfs_add_regset32(struct drm_device *drm, drm 767 drivers/gpu/drm/vc4/vc4_drv.h static inline void vc4_debugfs_add_file(struct drm_device *drm, drm 774 drivers/gpu/drm/vc4/vc4_drv.h static inline void vc4_debugfs_add_regset32(struct drm_device *drm, drm 1443 drivers/gpu/drm/vc4/vc4_dsi.c struct drm_device *drm = dev_get_drvdata(master); drm 1444 drivers/gpu/drm/vc4/vc4_dsi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 1598 drivers/gpu/drm/vc4/vc4_dsi.c drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs, drm 1615 drivers/gpu/drm/vc4/vc4_dsi.c vc4_debugfs_add_regset32(drm, "dsi0_regs", &dsi->regset); drm 1617 drivers/gpu/drm/vc4/vc4_dsi.c vc4_debugfs_add_regset32(drm, "dsi1_regs", &dsi->regset); drm 1627 drivers/gpu/drm/vc4/vc4_dsi.c struct drm_device *drm = dev_get_drvdata(master); drm 1628 drivers/gpu/drm/vc4/vc4_dsi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 427 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = encoder->dev; drm 428 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = drm->dev_private; drm 715 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = hdmi->encoder->dev; drm 716 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 736 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = encoder->dev; drm 737 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 805 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = encoder->dev; drm 807 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 839 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = encoder->dev; drm 841 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 912 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = encoder->dev; drm 913 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 1304 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = dev_get_drvdata(master); drm 1305 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = drm->dev_private; drm 1409 drivers/gpu/drm/vc4/vc4_hdmi.c drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, drm 1413 drivers/gpu/drm/vc4/vc4_hdmi.c hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); drm 1456 drivers/gpu/drm/vc4/vc4_hdmi.c vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); drm 1480 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_device *drm = dev_get_drvdata(master); drm 1481 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_dev *vc4 = drm->dev_private; drm 221 drivers/gpu/drm/vc4/vc4_hvs.c struct drm_device *drm = dev_get_drvdata(master); drm 222 drivers/gpu/drm/vc4/vc4_hvs.c struct vc4_dev *vc4 = drm->dev_private; drm 301 drivers/gpu/drm/vc4/vc4_hvs.c vc4_hvs_irq_handler, 0, "vc4 hvs", drm); drm 305 drivers/gpu/drm/vc4/vc4_hvs.c vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset); drm 306 drivers/gpu/drm/vc4/vc4_hvs.c vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, drm 315 drivers/gpu/drm/vc4/vc4_hvs.c struct drm_device *drm = dev_get_drvdata(master); drm 316 drivers/gpu/drm/vc4/vc4_hvs.c struct vc4_dev *vc4 = drm->dev_private; drm 32 drivers/gpu/drm/vc4/vc4_plane.c u32 drm; /* DRM_FORMAT_* */ drm 37 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, drm 41 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, drm 45 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, drm 49 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, drm 53 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565, drm 57 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565, drm 61 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, drm 65 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, drm 69 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888, drm 73 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888, drm 77 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_YUV422, drm 82 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_YVU422, drm 87 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_YUV420, drm 92 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_YVU420, drm 97 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_NV12, drm 102 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_NV21, drm 107 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_NV16, drm 112 drivers/gpu/drm/vc4/vc4_plane.c .drm = DRM_FORMAT_NV61, drm 123 drivers/gpu/drm/vc4/vc4_plane.c if (hvs_formats[i].drm == drm_format) drm 1251 drivers/gpu/drm/vc4/vc4_plane.c formats[i] = hvs_formats[i].drm; drm 59 drivers/gpu/drm/vc4/vc4_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/vc4 drm 372 drivers/gpu/drm/vc4/vc4_txp.c struct drm_device *drm = dev_get_drvdata(master); drm 373 drivers/gpu/drm/vc4/vc4_txp.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 396 drivers/gpu/drm/vc4/vc4_txp.c ret = drm_writeback_connector_init(drm, &txp->connector, drm 411 drivers/gpu/drm/vc4/vc4_txp.c vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset); drm 419 drivers/gpu/drm/vc4/vc4_txp.c struct drm_device *drm = dev_get_drvdata(master); drm 420 drivers/gpu/drm/vc4/vc4_txp.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 394 drivers/gpu/drm/vc4/vc4_v3d.c struct drm_device *drm = dev_get_drvdata(master); drm 395 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 449 drivers/gpu/drm/vc4/vc4_v3d.c vc4_v3d_init_hw(drm); drm 451 drivers/gpu/drm/vc4/vc4_v3d.c ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); drm 462 drivers/gpu/drm/vc4/vc4_v3d.c vc4_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL); drm 463 drivers/gpu/drm/vc4/vc4_v3d.c vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); drm 471 drivers/gpu/drm/vc4/vc4_v3d.c struct drm_device *drm = dev_get_drvdata(master); drm 472 drivers/gpu/drm/vc4/vc4_v3d.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 476 drivers/gpu/drm/vc4/vc4_v3d.c drm_irq_uninstall(drm); drm 528 drivers/gpu/drm/vc4/vc4_vec.c struct drm_device *drm = dev_get_drvdata(master); drm 529 drivers/gpu/drm/vc4/vc4_vec.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 534 drivers/gpu/drm/vc4/vc4_vec.c ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names), drm 569 drivers/gpu/drm/vc4/vc4_vec.c drm_encoder_init(drm, vec->encoder, &vc4_vec_encoder_funcs, drm 573 drivers/gpu/drm/vc4/vc4_vec.c vec->connector = vc4_vec_connector_init(drm, vec); drm 583 drivers/gpu/drm/vc4/vc4_vec.c vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset); drm 597 drivers/gpu/drm/vc4/vc4_vec.c struct drm_device *drm = dev_get_drvdata(master); drm 598 drivers/gpu/drm/vc4/vc4_vec.c struct vc4_dev *vc4 = to_vc4_dev(drm); drm 53 drivers/gpu/drm/vgem/vgem_drv.c struct drm_device drm; drm 355 drivers/gpu/drm/vgem/vgem_drv.c struct vgem_device *vgem = container_of(dev, typeof(*vgem), drm); drm 431 drivers/gpu/drm/vgem/vgem_drv.c struct vgem_device *vgem = container_of(dev, typeof(*vgem), drm); drm 434 drivers/gpu/drm/vgem/vgem_drv.c drm_dev_fini(&vgem->drm); drm 488 drivers/gpu/drm/vgem/vgem_drv.c ret = drm_dev_init(&vgem_device->drm, &vgem_driver, drm 494 drivers/gpu/drm/vgem/vgem_drv.c ret = drm_dev_register(&vgem_device->drm, 0); drm 501 drivers/gpu/drm/vgem/vgem_drv.c drm_dev_fini(&vgem_device->drm); drm 511 drivers/gpu/drm/vgem/vgem_drv.c drm_dev_unregister(&vgem_device->drm); drm 512 drivers/gpu/drm/vgem/vgem_drv.c drm_dev_put(&vgem_device->drm); drm 51 drivers/gpu/drm/virtio/virtgpu_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/virtio drm 60 drivers/gpu/drm/vkms/vkms_drv.c struct vkms_device *vkms = container_of(dev, struct vkms_device, drm); drm 63 drivers/gpu/drm/vkms/vkms_drv.c drm_atomic_helper_shutdown(&vkms->drm); drm 64 drivers/gpu/drm/vkms/vkms_drv.c drm_mode_config_cleanup(&vkms->drm); drm 65 drivers/gpu/drm/vkms/vkms_drv.c drm_dev_fini(&vkms->drm); drm 126 drivers/gpu/drm/vkms/vkms_drv.c struct drm_device *dev = &vkmsdev->drm; drm 155 drivers/gpu/drm/vkms/vkms_drv.c ret = drm_dev_init(&vkms_device->drm, &vkms_driver, drm 160 drivers/gpu/drm/vkms/vkms_drv.c vkms_device->drm.irq_enabled = true; drm 162 drivers/gpu/drm/vkms/vkms_drv.c ret = drm_vblank_init(&vkms_device->drm, 1); drm 172 drivers/gpu/drm/vkms/vkms_drv.c ret = drm_dev_register(&vkms_device->drm, 0); drm 179 drivers/gpu/drm/vkms/vkms_drv.c drm_dev_fini(&vkms_device->drm); drm 196 drivers/gpu/drm/vkms/vkms_drv.c drm_dev_unregister(&vkms_device->drm); drm 197 drivers/gpu/drm/vkms/vkms_drv.c drm_dev_put(&vkms_device->drm); drm 82 drivers/gpu/drm/vkms/vkms_drv.h struct drm_device drm; drm 99 drivers/gpu/drm/vkms/vkms_drv.h container_of(target, struct vkms_device, drm) drm 41 drivers/gpu/drm/vkms/vkms_output.c struct drm_device *dev = &vkmsdev->drm; drm 183 drivers/gpu/drm/vkms/vkms_plane.c struct drm_device *dev = &vkmsdev->drm; drm 59 drivers/gpu/drm/zte/zx_drm_drv.c struct drm_device *drm; drm 62 drivers/gpu/drm/zte/zx_drm_drv.c drm = drm_dev_alloc(&zx_drm_driver, dev); drm 63 drivers/gpu/drm/zte/zx_drm_drv.c if (IS_ERR(drm)) drm 64 drivers/gpu/drm/zte/zx_drm_drv.c return PTR_ERR(drm); drm 66 drivers/gpu/drm/zte/zx_drm_drv.c dev_set_drvdata(dev, drm); drm 68 drivers/gpu/drm/zte/zx_drm_drv.c drm_mode_config_init(drm); drm 69 drivers/gpu/drm/zte/zx_drm_drv.c drm->mode_config.min_width = 16; drm 70 drivers/gpu/drm/zte/zx_drm_drv.c drm->mode_config.min_height = 16; drm 71 drivers/gpu/drm/zte/zx_drm_drv.c drm->mode_config.max_width = 4096; drm 72 drivers/gpu/drm/zte/zx_drm_drv.c drm->mode_config.max_height = 4096; drm 73 drivers/gpu/drm/zte/zx_drm_drv.c drm->mode_config.funcs = &zx_drm_mode_config_funcs; drm 75 drivers/gpu/drm/zte/zx_drm_drv.c ret = component_bind_all(dev, drm); drm 81 drivers/gpu/drm/zte/zx_drm_drv.c ret = drm_vblank_init(drm, drm->mode_config.num_crtc); drm 91 drivers/gpu/drm/zte/zx_drm_drv.c drm->irq_enabled = true; drm 93 drivers/gpu/drm/zte/zx_drm_drv.c drm_mode_config_reset(drm); drm 94 drivers/gpu/drm/zte/zx_drm_drv.c drm_kms_helper_poll_init(drm); drm 96 drivers/gpu/drm/zte/zx_drm_drv.c ret = drm_dev_register(drm, 0); drm 100 drivers/gpu/drm/zte/zx_drm_drv.c drm_fbdev_generic_setup(drm, 32); drm 105 drivers/gpu/drm/zte/zx_drm_drv.c drm_kms_helper_poll_fini(drm); drm 106 drivers/gpu/drm/zte/zx_drm_drv.c drm_mode_config_cleanup(drm); drm 108 drivers/gpu/drm/zte/zx_drm_drv.c component_unbind_all(dev, drm); drm 111 drivers/gpu/drm/zte/zx_drm_drv.c drm_dev_put(drm); drm 117 drivers/gpu/drm/zte/zx_drm_drv.c struct drm_device *drm = dev_get_drvdata(dev); drm 119 drivers/gpu/drm/zte/zx_drm_drv.c drm_dev_unregister(drm); drm 120 drivers/gpu/drm/zte/zx_drm_drv.c drm_kms_helper_poll_fini(drm); drm 121 drivers/gpu/drm/zte/zx_drm_drv.c drm_atomic_helper_shutdown(drm); drm 122 drivers/gpu/drm/zte/zx_drm_drv.c drm_mode_config_cleanup(drm); drm 123 drivers/gpu/drm/zte/zx_drm_drv.c component_unbind_all(dev, drm); drm 125 drivers/gpu/drm/zte/zx_drm_drv.c drm_dev_put(drm); drm 42 drivers/gpu/drm/zte/zx_hdmi.c struct drm_device *drm; drm 310 drivers/gpu/drm/zte/zx_hdmi.c static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi) drm 316 drivers/gpu/drm/zte/zx_hdmi.c drm_encoder_init(drm, encoder, &zx_hdmi_encoder_funcs, drm 322 drivers/gpu/drm/zte/zx_hdmi.c drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs, drm 643 drivers/gpu/drm/zte/zx_hdmi.c struct drm_device *drm = data; drm 654 drivers/gpu/drm/zte/zx_hdmi.c hdmi->drm = drm; drm 703 drivers/gpu/drm/zte/zx_hdmi.c ret = zx_hdmi_register(drm, hdmi); drm 495 drivers/gpu/drm/zte/zx_plane.c int zx_plane_init(struct drm_device *drm, struct zx_plane *zplane, drm 522 drivers/gpu/drm/zte/zx_plane.c ret = drm_universal_plane_init(drm, plane, VOU_CRTC_MASK, drm 22 drivers/gpu/drm/zte/zx_plane.h int zx_plane_init(struct drm_device *drm, struct zx_plane *zplane, drm 277 drivers/gpu/drm/zte/zx_tvenc.c static int zx_tvenc_register(struct drm_device *drm, struct zx_tvenc *tvenc) drm 288 drivers/gpu/drm/zte/zx_tvenc.c drm_encoder_init(drm, encoder, &zx_tvenc_encoder_funcs, drm 294 drivers/gpu/drm/zte/zx_tvenc.c drm_connector_init(drm, connector, &zx_tvenc_connector_funcs, drm 334 drivers/gpu/drm/zte/zx_tvenc.c struct drm_device *drm = data; drm 360 drivers/gpu/drm/zte/zx_tvenc.c ret = zx_tvenc_register(drm, tvenc); drm 148 drivers/gpu/drm/zte/zx_vga.c static int zx_vga_register(struct drm_device *drm, struct zx_vga *vga) drm 157 drivers/gpu/drm/zte/zx_vga.c ret = drm_encoder_init(drm, encoder, &zx_vga_encoder_funcs, drm 168 drivers/gpu/drm/zte/zx_vga.c ret = drm_connector_init(drm, connector, &zx_vga_connector_funcs, drm 426 drivers/gpu/drm/zte/zx_vga.c struct drm_device *drm = data; drm 467 drivers/gpu/drm/zte/zx_vga.c ret = zx_vga_register(drm, vga); drm 531 drivers/gpu/drm/zte/zx_vou.c static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou, drm 584 drivers/gpu/drm/zte/zx_vou.c ret = zx_plane_init(drm, zplane, DRM_PLANE_TYPE_PRIMARY); drm 592 drivers/gpu/drm/zte/zx_vou.c ret = drm_crtc_init_with_planes(drm, &zcrtc->crtc, zcrtc->primary, NULL, drm 640 drivers/gpu/drm/zte/zx_vou.c static void zx_overlay_init(struct drm_device *drm, struct zx_vou_hw *vou) drm 663 drivers/gpu/drm/zte/zx_vou.c ret = zx_plane_init(drm, zplane, DRM_PLANE_TYPE_OVERLAY); drm 765 drivers/gpu/drm/zte/zx_vou.c struct drm_device *drm = data; drm 858 drivers/gpu/drm/zte/zx_vou.c ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN); drm 865 drivers/gpu/drm/zte/zx_vou.c ret = zx_crtc_init(drm, vou, VOU_CHN_AUX); drm 872 drivers/gpu/drm/zte/zx_vou.c zx_overlay_init(drm, vou); drm 240 drivers/hid/hid-wiimote-core.c void wiiproto_req_drm(struct wiimote_data *wdata, __u8 drm) drm 245 drivers/hid/hid-wiimote-core.c drm = wdata->state.drm; drm 246 drivers/hid/hid-wiimote-core.c else if (drm == WIIPROTO_REQ_NULL) drm 247 drivers/hid/hid-wiimote-core.c drm = select_drm(wdata); drm 251 drivers/hid/hid-wiimote-core.c cmd[2] = drm; drm 253 drivers/hid/hid-wiimote-core.c wdata->state.drm = drm; drm 1750 drivers/hid/hid-wiimote-core.c wdata->state.drm = WIIPROTO_REQ_DRM_K; drm 20 drivers/hid/hid-wiimote-debug.c struct dentry *drm; drm 103 drivers/hid/hid-wiimote-debug.c __u8 drm; drm 106 drivers/hid/hid-wiimote-debug.c drm = dbg->wdata->state.drm; drm 109 drivers/hid/hid-wiimote-debug.c if (drm < WIIPROTO_REQ_MAX) drm 110 drivers/hid/hid-wiimote-debug.c str = wiidebug_drmmap[drm]; drm 189 drivers/hid/hid-wiimote-debug.c dbg->drm = debugfs_create_file("drm", S_IRUSR, drm 191 drivers/hid/hid-wiimote-debug.c if (!dbg->drm) drm 219 drivers/hid/hid-wiimote-debug.c debugfs_remove(dbg->drm); drm 119 drivers/hid/hid-wiimote.h __u8 drm; drm 263 drivers/hid/hid-wiimote.h extern void wiiproto_req_drm(struct wiimote_data *wdata, __u8 drm); drm 86 drivers/media/cec/cec-adap.c conn_info->drm.card_no = connector->dev->primary->index; drm 87 drivers/media/cec/cec-adap.c conn_info->drm.connector_id = connector->base.id; drm 105 drivers/media/platform/vsp1/vsp1.h struct vsp1_drm *drm; drm 130 drivers/media/platform/vsp1/vsp1_drm.c crop = &vsp1->drm->inputs[rpf->entity.index].crop; drm 209 drivers/media/platform/vsp1/vsp1_drm.c sel.r = vsp1->drm->inputs[rpf->entity.index].compose; drm 363 drivers/media/platform/vsp1/vsp1_drm.c return vsp1->drm->inputs[rpf->entity.index].zpos; drm 652 drivers/media/platform/vsp1/vsp1_drm.c drm_pipe = &vsp1->drm->pipe[pipe_index]; drm 658 drivers/media/platform/vsp1/vsp1_drm.c mutex_lock(&vsp1->drm->lock); drm 699 drivers/media/platform/vsp1/vsp1_drm.c mutex_unlock(&vsp1->drm->lock); drm 717 drivers/media/platform/vsp1/vsp1_drm.c mutex_lock(&vsp1->drm->lock); drm 748 drivers/media/platform/vsp1/vsp1_drm.c mutex_unlock(&vsp1->drm->lock); drm 809 drivers/media/platform/vsp1/vsp1_drm.c struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index]; drm 855 drivers/media/platform/vsp1/vsp1_drm.c vsp1->drm->inputs[rpf_index].crop = cfg->src; drm 856 drivers/media/platform/vsp1/vsp1_drm.c vsp1->drm->inputs[rpf_index].compose = cfg->dst; drm 857 drivers/media/platform/vsp1/vsp1_drm.c vsp1->drm->inputs[rpf_index].zpos = cfg->zpos; drm 875 drivers/media/platform/vsp1/vsp1_drm.c struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index]; drm 881 drivers/media/platform/vsp1/vsp1_drm.c mutex_lock(&vsp1->drm->lock); drm 902 drivers/media/platform/vsp1/vsp1_drm.c mutex_unlock(&vsp1->drm->lock); drm 937 drivers/media/platform/vsp1/vsp1_drm.c vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL); drm 938 drivers/media/platform/vsp1/vsp1_drm.c if (!vsp1->drm) drm 941 drivers/media/platform/vsp1/vsp1_drm.c mutex_init(&vsp1->drm->lock); drm 945 drivers/media/platform/vsp1/vsp1_drm.c struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i]; drm 989 drivers/media/platform/vsp1/vsp1_drm.c mutex_destroy(&vsp1->drm->lock); drm 591 drivers/media/platform/vsp1/vsp1_drv.c if (!vsp1->drm) drm 609 drivers/media/platform/vsp1/vsp1_drv.c if (!vsp1->drm) drm 906 drivers/video/hdmi.c length = hdmi_drm_infoframe_pack_only(&frame->drm, drm 958 drivers/video/hdmi.c length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); drm 1533 drivers/video/hdmi.c hdmi_drm_infoframe_log(level, dev, &frame->drm); drm 1868 drivers/video/hdmi.c ret = hdmi_drm_infoframe_unpack(&frame->drm, buffer, size); drm 71 include/drm/drm_gem_cma_helper.h struct drm_device *drm, drm 76 include/drm/drm_gem_cma_helper.h struct drm_device *drm, drm 83 include/drm/drm_gem_cma_helper.h struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm, drm 129 include/drm/drm_gem_cma_helper.h drm_gem_cma_prime_import_sg_table_vmap(struct drm_device *drm, drm 80 include/drm/drm_mipi_dbi.h struct drm_device drm; drm 128 include/drm/drm_mipi_dbi.h static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm) drm 130 include/drm/drm_mipi_dbi.h return container_of(drm, struct mipi_dbi_dev, drm); drm 143 include/drm/drm_mipi_dbi.h void mipi_dbi_release(struct drm_device *drm); drm 119 include/drm/drm_panel.h struct drm_device *drm; drm 424 include/linux/hdmi.h struct hdmi_drm_infoframe drm; drm 173 include/media/cec.h struct cec_drm_connector_info drm;