dram_channel_width_in_bits  132 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 	DC_LOG_BANDWIDTH_CALCS("	[uint32_t] dram_channel_width_in_bits: %d", vbios->dram_channel_width_in_bits);
dram_channel_width_in_bits 1154 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					data->display_reads_required_dram_access_data = bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed((8 * vbios->dram_channel_width_in_bits / 8)), data->bytes_per_request[i]), bw_int_to_fixed(1)));
dram_channel_width_in_bits 1161 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->total_display_writes_required_dram_access_data = bw_add(data->total_display_writes_required_dram_access_data, bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits), data->bytes_per_request[i]), bw_int_to_fixed(1))));
dram_channel_width_in_bits 1188 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100)))));
dram_channel_width_in_bits 1190 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width))));
dram_channel_width_in_bits 1529 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
dram_channel_width_in_bits 1535 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
dram_channel_width_in_bits 1539 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[low]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
dram_channel_width_in_bits 1540 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				&& bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[low][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[low][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[low][s_high] == number_of_displays_enabled_with_margin))) {
dram_channel_width_in_bits 1543 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
dram_channel_width_in_bits 1545 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[mid]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
dram_channel_width_in_bits 1546 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				&& bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[mid][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[mid][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[mid][s_high] == number_of_displays_enabled_with_margin))) {
dram_channel_width_in_bits 1549 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
dram_channel_width_in_bits 1551 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[high]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
dram_channel_width_in_bits 1552 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				&& bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))) {
dram_channel_width_in_bits 1555 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
dram_channel_width_in_bits 1560 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
dram_channel_width_in_bits 2043 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.dram_channel_width_in_bits = 64;
dram_channel_width_in_bits 2044 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
dram_channel_width_in_bits 2159 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.dram_channel_width_in_bits = 32;
dram_channel_width_in_bits 2160 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
dram_channel_width_in_bits 2272 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.dram_channel_width_in_bits = 32;
dram_channel_width_in_bits 2273 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
dram_channel_width_in_bits 2388 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.dram_channel_width_in_bits = 32;
dram_channel_width_in_bits 2389 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
dram_channel_width_in_bits 2504 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.dram_channel_width_in_bits = 64;
dram_channel_width_in_bits 2505 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
dram_channel_width_in_bits 2617 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.dram_channel_width_in_bits = 128;
dram_channel_width_in_bits 2618 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
dram_channel_width_in_bits  194 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	uint32_t dram_channel_width_in_bits;