dpu_irq_map       252 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c static const struct dpu_irq_type dpu_irq_map[] = {
dpu_irq_map       762 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
dpu_irq_map       763 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		if (intr_type == dpu_irq_map[i].intr_type &&
dpu_irq_map       764 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 			instance_idx == dpu_irq_map[i].instance_idx)
dpu_irq_map       803 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 		if (start_idx >= ARRAY_SIZE(dpu_irq_map) ||
dpu_irq_map       804 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 				end_idx > ARRAY_SIZE(dpu_irq_map))
dpu_irq_map       815 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 			if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
dpu_irq_map       816 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 				(dpu_irq_map[irq_idx].reg_idx == reg_idx)) {
dpu_irq_map       835 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 				irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
dpu_irq_map       853 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
dpu_irq_map       858 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	irq = &dpu_irq_map[irq_idx];
dpu_irq_map       899 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
dpu_irq_map       904 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	irq = &dpu_irq_map[irq_idx];
dpu_irq_map       939 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
dpu_irq_map      1024 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	reg_idx = dpu_irq_map[irq_idx].reg_idx;
dpu_irq_map      1026 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 			dpu_irq_map[irq_idx].irq_mask);
dpu_irq_map      1042 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) {
dpu_irq_map      1049 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	reg_idx = dpu_irq_map[irq_idx].reg_idx;
dpu_irq_map      1052 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 					dpu_irq_map[irq_idx].irq_mask;
dpu_irq_map      1101 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);