dpu_intr_set 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c static const struct dpu_intr_reg dpu_intr_set[] = { dpu_intr_set 793 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { dpu_intr_set 860 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c reg = &dpu_intr_set[reg_idx]; dpu_intr_set 906 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c reg = &dpu_intr_set[reg_idx]; dpu_intr_set 958 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) dpu_intr_set 959 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, 0xffffffff); dpu_intr_set 974 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) dpu_intr_set 975 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].en_off, 0x00000000); dpu_intr_set 993 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { dpu_intr_set 996 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c dpu_intr_set[i].status_off); dpu_intr_set 999 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); dpu_intr_set 1003 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, dpu_intr_set 1025 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, dpu_intr_set 1051 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c dpu_intr_set[reg_idx].status_off) & dpu_intr_set 1054 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, dpu_intr_set 1103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), dpu_intr_set 1110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),