dpu_enc 406 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 409 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 410 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 415 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 416 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 425 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 433 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 434 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 436 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->enc_lock); dpu_enc 438 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 439 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 443 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c --dpu_enc->num_phys_encs; dpu_enc 444 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[i] = NULL; dpu_enc 448 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->num_phys_encs) dpu_enc 449 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", dpu_enc 450 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->num_phys_encs); dpu_enc 451 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->num_phys_encs = 0; dpu_enc 452 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->enc_lock); dpu_enc 455 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_destroy(&dpu_enc->enc_lock); dpu_enc 462 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 472 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(phys_enc->parent); dpu_enc 474 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c disp_info = &dpu_enc->disp_info; dpu_enc 500 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); dpu_enc 526 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc, dpu_enc 534 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->phys_encs[i]) dpu_enc 549 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 564 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 565 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 583 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 584 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 594 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, dpu_enc 600 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); dpu_enc 609 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c && dpu_enc->mode_set_complete) { dpu_enc 612 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->mode_set_complete = false; dpu_enc 622 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, dpu_enc 632 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc || !disp_info) { dpu_enc 634 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc != NULL, disp_info != NULL); dpu_enc 636 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { dpu_enc 638 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->num_phys_encs, dpu_enc 639 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c (int) ARRAY_SIZE(dpu_enc->hw_pp)); dpu_enc 643 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c drm_enc = &dpu_enc->base; dpu_enc 661 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) dpu_enc 662 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; dpu_enc 664 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c vsync_cfg.pp_count = dpu_enc->num_phys_encs; dpu_enc 676 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 684 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 686 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); dpu_enc 687 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 688 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 701 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 703 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 709 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->cur_master) { dpu_enc 734 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 743 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 745 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c is_vid_mode = dpu_enc->disp_info.capabilities & dpu_enc 752 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->idle_pc_supported && dpu_enc 758 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, dpu_enc 759 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state, "begin"); dpu_enc 764 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) dpu_enc 765 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", dpu_enc 768 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->rc_lock); dpu_enc 771 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { dpu_enc 774 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 776 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && dpu_enc 777 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { dpu_enc 780 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state); dpu_enc 781 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 785 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) dpu_enc 790 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; dpu_enc 793 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 796 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 806 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { dpu_enc 809 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state); dpu_enc 823 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, dpu_enc 824 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c msecs_to_jiffies(dpu_enc->idle_timeout)); dpu_enc 827 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 833 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) dpu_enc 834 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", dpu_enc 837 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->rc_lock); dpu_enc 840 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { dpu_enc 844 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || dpu_enc 845 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { dpu_enc 848 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state); dpu_enc 849 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 853 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; dpu_enc 856 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 859 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 863 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->rc_lock); dpu_enc 866 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { dpu_enc 869 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 871 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { dpu_enc 873 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(drm_enc), sw_event, dpu_enc->rc_state); dpu_enc 874 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 882 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) dpu_enc 885 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; dpu_enc 888 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 891 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 895 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->rc_lock); dpu_enc 897 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { dpu_enc 899 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(drm_enc), sw_event, dpu_enc->rc_state); dpu_enc 900 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 908 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->frame_busy_mask[0]) { dpu_enc 910 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(drm_enc), sw_event, dpu_enc->rc_state); dpu_enc 911 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 920 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; dpu_enc 923 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 926 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->rc_lock); dpu_enc 933 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 939 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported, dpu_enc->rc_state, dpu_enc 948 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 967 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 968 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 981 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); dpu_enc 984 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); dpu_enc 992 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); dpu_enc 998 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, dpu_enc 1005 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->hw_pp[i] = NULL; dpu_enc 1008 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) hw_iter.hw; dpu_enc 1038 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1039 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 1042 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->hw_pp[i]) { dpu_enc 1043 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "no pp block assigned" dpu_enc 1049 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "no ctl block assigned" dpu_enc 1054 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys->hw_pp = dpu_enc->hw_pp[i]; dpu_enc 1071 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, dpu_enc 1083 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->mode_set_complete = true; dpu_enc 1091 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 1107 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1108 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc || !dpu_enc->cur_master) { dpu_enc 1113 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->cur_master->hw_mdptop && dpu_enc 1114 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) dpu_enc 1115 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( dpu_enc 1116 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master->hw_mdptop, dpu_enc 1119 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); dpu_enc 1124 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1126 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->enc_lock); dpu_enc 1128 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->enabled) dpu_enc 1131 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) dpu_enc 1132 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); dpu_enc 1133 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) dpu_enc 1134 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); dpu_enc 1139 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->enc_lock); dpu_enc 1144 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 1152 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1154 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->enc_lock); dpu_enc 1155 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; dpu_enc 1161 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) dpu_enc 1162 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); dpu_enc 1164 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) dpu_enc 1165 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); dpu_enc 1169 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", dpu_enc 1176 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->enabled = true; dpu_enc 1179 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->enc_lock); dpu_enc 1184 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 1201 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1202 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 1204 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->enc_lock); dpu_enc 1205 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->enabled = false; dpu_enc 1219 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1220 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 1227 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { dpu_enc 1229 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c del_timer_sync(&dpu_enc->frame_done_timer); dpu_enc 1234 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1235 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->phys_encs[i]) dpu_enc 1236 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[i]->connector = NULL; dpu_enc 1239 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); dpu_enc 1243 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->enc_lock); dpu_enc 1264 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 1271 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1273 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1274 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->crtc) dpu_enc 1275 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_crtc_vblank_callback(dpu_enc->crtc); dpu_enc 1276 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1297 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1300 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1302 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c WARN_ON(crtc && dpu_enc->crtc); dpu_enc 1303 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc = crtc; dpu_enc 1304 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1310 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1316 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1317 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->crtc != crtc) { dpu_enc 1318 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1321 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1323 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1324 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 1335 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1347 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1348 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb = frame_event_cb; dpu_enc 1349 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; dpu_enc 1350 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1357 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1364 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->frame_busy_mask[0]) { dpu_enc 1375 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1376 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->phys_encs[i] == ready_phys) { dpu_enc 1378 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->frame_busy_mask[0]); dpu_enc 1379 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c clear_bit(i, dpu_enc->frame_busy_mask); dpu_enc 1383 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->frame_busy_mask[0]) { dpu_enc 1384 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c atomic_set(&dpu_enc->frame_done_timeout_ms, 0); dpu_enc 1385 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c del_timer(&dpu_enc->frame_done_timer); dpu_enc 1390 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->crtc_frame_event_cb) dpu_enc 1391 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb( dpu_enc 1392 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb_data, dpu_enc 1396 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->crtc_frame_event_cb) dpu_enc 1397 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb( dpu_enc 1398 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb_data, event); dpu_enc 1404 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = container_of(work, dpu_enc 1407 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc) { dpu_enc 1412 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_encoder_resource_control(&dpu_enc->base, dpu_enc 1415 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, dpu_enc 1521 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 1529 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(phys_enc->parent); dpu_enc 1540 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); dpu_enc 1554 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) dpu_enc 1563 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1566 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1567 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 1582 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c set_bit(i, dpu_enc->frame_busy_mask); dpu_enc 1586 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); dpu_enc 1592 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (pending_flush && dpu_enc->cur_master) { dpu_enc 1594 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c &dpu_enc->base, dpu_enc 1595 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master, dpu_enc 1599 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c _dpu_encoder_trigger_start(dpu_enc->cur_master); dpu_enc 1601 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); dpu_enc 1606 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 1616 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1617 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c disp_info = &dpu_enc->disp_info; dpu_enc 1619 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1620 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys = dpu_enc->phys_encs[i]; dpu_enc 1628 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if ((phys == dpu_enc->cur_master) && dpu_enc 1636 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, dpu_enc 1646 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->cur_master) dpu_enc 1649 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->cur_master->ops.get_line_count) { dpu_enc 1676 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, dpu_enc 1686 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 1692 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1700 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); dpu_enc 1704 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); dpu_enc 1721 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, dpu_enc 1731 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, dpu_enc 1733 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct drm_encoder *drm_enc = &dpu_enc->base; dpu_enc 1756 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c del_timer(&dpu_enc->vsync_event_timer); dpu_enc 1761 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = container_of(work, dpu_enc 1765 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc) { dpu_enc 1770 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) dpu_enc 1773 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); dpu_enc 1774 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mod_timer(&dpu_enc->vsync_event_timer, dpu_enc 1780 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 1785 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1791 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1792 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys = dpu_enc->phys_encs[i]; dpu_enc 1807 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1808 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); dpu_enc 1815 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 1822 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1829 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); dpu_enc 1830 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mod_timer(&dpu_enc->frame_done_timer, dpu_enc 1834 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c _dpu_encoder_kickoff_phys(dpu_enc); dpu_enc 1837 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1838 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys = dpu_enc->phys_encs[i]; dpu_enc 1843 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && dpu_enc 1847 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mod_timer(&dpu_enc->vsync_event_timer, dpu_enc 1856 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc; dpu_enc 1864 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1866 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1867 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys = dpu_enc->phys_encs[i]; dpu_enc 1876 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = s->private; dpu_enc 1879 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->enc_lock); dpu_enc 1880 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 1881 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 1903 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->enc_lock); dpu_enc 1916 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 1941 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->debugfs_root = debugfs_create_dir(name, dpu_enc 1946 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); dpu_enc 1948 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) dpu_enc 1949 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->phys_encs[i] && dpu_enc 1950 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[i]->ops.late_register) dpu_enc 1951 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[i]->ops.late_register( dpu_enc 1952 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[i], dpu_enc 1953 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->debugfs_root); dpu_enc 1971 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); dpu_enc 1973 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c debugfs_remove_recursive(dpu_enc->debugfs_root); dpu_enc 1978 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc, dpu_enc 1983 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 1989 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= dpu_enc 1990 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ARRAY_SIZE(dpu_enc->phys_encs)) { dpu_enc 1991 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", dpu_enc 1992 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->num_phys_encs); dpu_enc 2000 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", dpu_enc 2005 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; dpu_enc 2006 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++dpu_enc->num_phys_encs; dpu_enc 2013 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", dpu_enc 2018 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; dpu_enc 2019 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ++dpu_enc->num_phys_encs; dpu_enc 2023 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_slave = enc; dpu_enc 2025 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master = enc; dpu_enc 2036 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, dpu_enc 2045 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc || !dpu_kms) { dpu_enc 2047 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc != 0, dpu_kms != 0); dpu_enc 2051 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->cur_master = NULL; dpu_enc 2055 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_params.parent = &dpu_enc->base; dpu_enc 2057 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_params.enc_spinlock = &dpu_enc->enc_spinlock; dpu_enc 2066 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n"); dpu_enc 2076 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_pc_supported = dpu_enc 2079 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_lock(&dpu_enc->enc_lock); dpu_enc 2104 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", dpu_enc 2111 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc, dpu_enc 2114 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); dpu_enc 2118 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 2119 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 2126 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_unlock(&dpu_enc->enc_lock); dpu_enc 2133 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, dpu_enc 2135 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct drm_encoder *drm_enc = &dpu_enc->base; dpu_enc 2145 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { dpu_enc 2147 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); dpu_enc 2149 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { dpu_enc 2154 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); dpu_enc 2158 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); dpu_enc 2183 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 2186 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(enc); dpu_enc 2188 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_init(&dpu_enc->enc_lock); dpu_enc 2189 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); dpu_enc 2193 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c atomic_set(&dpu_enc->frame_done_timeout_ms, 0); dpu_enc 2194 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c timer_setup(&dpu_enc->frame_done_timer, dpu_enc 2198 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c timer_setup(&dpu_enc->vsync_event_timer, dpu_enc 2203 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mutex_init(&dpu_enc->rc_lock); dpu_enc 2204 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, dpu_enc 2206 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->idle_timeout = IDLE_TIMEOUT; dpu_enc 2208 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c kthread_init_work(&dpu_enc->vsync_event_work, dpu_enc 2211 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); dpu_enc 2213 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "created\n"); dpu_enc 2230 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 2233 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); dpu_enc 2234 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!dpu_enc) dpu_enc 2237 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, dpu_enc 2240 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c devm_kfree(dev->dev, dpu_enc); dpu_enc 2244 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); dpu_enc 2246 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c spin_lock_init(&dpu_enc->enc_spinlock); dpu_enc 2247 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc->enabled = false; dpu_enc 2249 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c return &dpu_enc->base; dpu_enc 2256 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 2263 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(drm_enc); dpu_enc 2264 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_ENC(dpu_enc, "\n"); dpu_enc 2266 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 2267 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; dpu_enc 2282 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", dpu_enc 2301 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_virt *dpu_enc = NULL; dpu_enc 2308 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(encoder); dpu_enc 2310 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_enc->cur_master) dpu_enc 2311 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c return dpu_enc->cur_master->intf_mode; dpu_enc 2313 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c for (i = 0; i < dpu_enc->num_phys_encs; i++) { dpu_enc 2314 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];