dpte_row_width_ub  391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	unsigned int dpte_row_width_ub = 0;
dpte_row_width_ub  608 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
dpte_row_width_ub  611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_row_width_ub  619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  624 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
dpte_row_width_ub  626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
dpte_row_width_ub  662 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
dpte_row_width_ub  391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	unsigned int dpte_row_width_ub = 0;
dpte_row_width_ub  608 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
dpte_row_width_ub  611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_row_width_ub  619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  624 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
dpte_row_width_ub  626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
dpte_row_width_ub  662 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
dpte_row_width_ub  193 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		unsigned int *dpte_row_width_ub,
dpte_row_width_ub 1276 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		unsigned int *dpte_row_width_ub,
dpte_row_width_ub 1417 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			*dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
dpte_row_width_ub 1418 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
dpte_row_width_ub 1421 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
dpte_row_width_ub 1422 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
dpte_row_width_ub 1425 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight;
dpte_row_width_ub 1426 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
dpte_row_width_ub  383 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	unsigned int dpte_row_width_ub = 0;
dpte_row_width_ub  610 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		dpte_row_width_ub = dml_round_to_multiple(
dpte_row_width_ub  614 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  620 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_row_width_ub  622 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  627 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
dpte_row_width_ub  629 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
dpte_row_width_ub  671 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			(double) dpte_row_width_ub / dpte_group_width,
dpte_row_width_ub  596 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int dpte_row_width_ub;
dpte_row_width_ub  790 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	dpte_row_width_ub = 0;
dpte_row_width_ub  846 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		dpte_row_width_ub = dml_round_to_multiple(
dpte_row_width_ub  850 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  855 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
dpte_row_width_ub  857 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
dpte_row_width_ub  862 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
dpte_row_width_ub  864 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
dpte_row_width_ub  906 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			(double) dpte_row_width_ub / dpte_group_width,